CN103021445B - A kind of primary particle inversion resistant sense amplifier - Google Patents
A kind of primary particle inversion resistant sense amplifier Download PDFInfo
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- CN103021445B CN103021445B CN201210500359.6A CN201210500359A CN103021445B CN 103021445 B CN103021445 B CN 103021445B CN 201210500359 A CN201210500359 A CN 201210500359A CN 103021445 B CN103021445 B CN 103021445B
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Abstract
The invention discloses a kind of primary particle inversion resistant sense amplifier, comprise pre-charge circuit, input control structure and latch cicuit; The input port of pre-charge circuit connects precharging signal line and two complementary data input lines respectively, two complementary data input lines are connected with power supply by pre-charge circuit respectively, and two complementary data input lines are connected, make complementary data input line precharge balance.Compared with traditional sense amplifier, the primary particle inversion resistant sense amplifier of one provided by the invention, while realizing sense amplifier function, has anti-single particle overturn reinforcement ability; According to TSMC? 0.18um process simulation results, the present invention can realize turn threshold and be greater than 500MeVcm
2mg
-1.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of primary particle inversion resistant sense amplifier.
Background technology
The critical size of integrated circuit constantly reduces along with the development of technology, and node critical charge is also reduced thereupon, and the soft error that therefore single particle effect causes will be more remarkable.Single particle effect has become one of main integrity problem of aerospace field electronic system.In order to ensure the reliability of spacecraft under irradiation space environment, radiation hardened measure must be taked to integrated circuit.
As the auxiliary circuit sense amplifier that memory cell data reads, data read errors may be caused because of single-particle inversion.Therefore need to carry out single-particle inversion reinforcing to sense amplifier, improve the capability of resistance to radiation of system.High performance sense amplifier requires that voltage gain is high, and time delay is short, and circuit structure is simple.Traditional sense amplifier is divided three classes: difference type sense amplifier, cross-couplings type sense amplifier, latch type sense amplifier.But this three classes sense amplifier does not all have anti-single particle overturn ability.
Summary of the invention
The problem that the present invention solves is to provide a kind of primary particle inversion resistant sense amplifier, overcomes existing sense amplifier and does not have immunocompetent defect to single-particle inversion, can be applicable to radioresistance memory circuit.
The present invention is achieved through the following technical solutions:
A kind of primary particle inversion resistant sense amplifier, comprises pre-charge circuit, input control structure and latch cicuit;
The input port of pre-charge circuit connects precharging signal line and two complementary data input lines respectively, two complementary data input lines are connected with power supply by pre-charge circuit respectively, and two complementary data input lines are connected, make complementary data input line precharge balance;
The input end of input control structure connects working control signal line, and the output terminal of the complementary data input line of pre-charge circuit; The output terminal of input control structure connects internal node and the earth point of latch cicuit;
Latch cicuit comprises the latch structure of multiple cross-linked phase inverter composition and the phase inverter of multiple two-way feedback inverter composition, latch structure and phase inverter arranged in a crossed manner, internal node is arranged in the inside of latch structure, phase inverter; The output terminal of latch cicuit connects two complementary data output lines respectively.
Described pre-charge circuit comprises three PMOS, and wherein two complementary data input lines are connected with power supply by two PMOS respectively, and two articles of complementary data input lines are connected by the 3rd PMOS.
Described input control structure is managed by multiple POMS and a NMOS tube forms, and POMS pipe is all connected with working control signal line with the grid of NMOS tube; The drain electrode of each PMOS is connected with one of latch cicuit internal node respectively, and source electrode is connected with one of two complementary data output lines; NMOS tube source ground, drain electrode connects latch cicuit internal node.
Described pre-charge circuit comprises three PMOS, consists of:
The grid of the 9th PMOS connects precharging signal line, and drain electrode connects the first complementary data input line, and source electrode connects the second complementary data input line, and substrate connects power supply;
The grid of the tenth PMOS connects precharging signal line, and drain electrode connects the first complementary data input line, and source electrode and substrate connect power supply;
The grid of the 11 PMOS connects precharging signal line, and drain electrode connects the second complementary data input line, and source electrode and substrate connect power supply.
Described input control structure comprises the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS and the 5th NMOS tube;
The grid of the 5th PMOS connects working control signal line, and drain electrode connects the first complementary data output line, and source electrode connects the first complementary data input line, and substrate connects power supply;
The grid of the 6th PMOS connects working control signal line, and drain electrode meets internal node Bb, and source electrode connects the second complementary data input line, and substrate connects power supply;
The grid of the 7th PMOS connects working control signal line, and drain electrode meets internal node B, and source electrode connects the first complementary data input line, and substrate connects power supply;
The grid of the 8th PMOS connects working control signal line, and drain electrode connects the second complementary data output line, and source electrode connects the second complementary data input line, and substrate connects power supply;
5th NMOS tube grid connects working control signal line, and drain electrode meets internal node N, source electrode and Substrate ground;
Latch cicuit is made up of the first PMOS, the first NMOS tube, the second PMOS, the second NMOS tube, the 3rd PMOS, the 3rd NMOS tube, the 4th PMOS and the 4th NMOS tube;
The grid of the first PMOS connects the second complementary data output line, and drain electrode connects the first complementary data output line, and source electrode and substrate connect power supply;
The grid of the first NMOS tube meets internal node Bb, and drain electrode meets the first complementary data output line OUT), source electrode meets internal node N, Substrate ground;
Second PMOS P2) grid connect the first complementary data output line, drain electrode meet internal node Bb, source electrode and substrate connect power supply;
The grid of the second NMOS tube meets internal node B, and drain electrode meets internal node Bb, and source electrode meets internal node N, Substrate ground;
The grid of the 3rd PMOS meets internal node Bb, and drain electrode meets internal node B, and source electrode and substrate connect power supply;
The grid of the 3rd NMOS tube connects the second complementary data output line, and drain electrode meets internal node B, and source electrode meets internal node N, Substrate ground;
The grid of the 4th PMOS meets internal node B, and drain electrode connects the second complementary data output line, and source electrode and substrate connect power supply;
The grid of the 4th NMOS tube connects the first complementary data output line, and drain electrode connects the second complementary data output line, and source electrode meets internal node N, Substrate ground.
In the course of the work, the 5th NMOS tube conducting, the 5th PMOS, the 6th PMOS, the 7th PMOS and the 8th PMOS turn off; If internal node Q and B voltage are " 1 ", internal node Bb and Qb voltage are " 0 ", then the drain electrode of a NMOS, the 3rd NMOS, the 2nd PMOS and the 4th PMOS is reverse-biased; Internal node Q, B, Qb and Bb are sensitive nodes.
Described internal node Q when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of a NMOS is subject to high-energy particle bombardment, the voltage at internal node Q place is driven high, and make the data variation of storage for " 1 ", cause the 4th NMOS tube conducting, the 2nd PMOS turns off; After 4th NMOS tube conducting, internal node Qb place voltage is also drop-down, makes it overturn; Internal node Q, Qb place overturns the state of maintenance " 1 " and " 0 " simultaneously; And internal node B and Bb place can not change still for " 0 " and " 1 ", make the 4th PMOS and the first NMOS tube conducting, namely discharge gradually and charge in internal node Q and Qb place, and final Q, Qb have returned to original current potential, and Data flipping returns " 0 " and " 1 ";
Internal node Q when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of a PMOS is subject to high-energy particle bombardment, the voltage at internal node Q place is dragged down, and makes the data variation of storage for " 0 ", causes the 4th NMOS tube to turn off, the 2nd PMOS conducting; 4th NMOS tube is closed and is had no progeny, and internal node Qb is in high-impedance state, makes data keep " 0 "; After second PMOS conducting, the current potential at internal node Bb place is driven high, and overturns, and data become " 1 "; The noble potential at internal node Bb place makes the 3rd PMOS turn off, and internal node B point is equally in high-impedance state with internal node Qb point, keeps one state; And the noble potential of internal node B point makes the second NMOS tube conducting simultaneously, absorb the electric charge at Bb point place; The electronegative potential of internal node Qb point makes the first PMOS conducting, and absorb the electric charge at internal node Q point place, final internal node Q, Bb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Internal node Bb when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 2nd NMOS is subject to high-energy particle bombardment, internal node Bb place current potential is driven high, and roll data occurs and becomes " 1 ", make the first NMOS tube conducting simultaneously, the 3rd PMOS turns off; After first NMOS tube conducting, internal node Q point voltage is dragged down, and data become " 0 ", causes the 4th NMOS tube to turn off, the 2nd PMOS conducting; 4th NMOS tube is closed and is had no progeny, and internal node Qb is in high-impedance state, makes data keep " 0 "; After 2nd PMOS conducting, the current potential at internal node Bb place is driven high, and overturns, and data become " 1 "; The noble potential at internal node Bb place makes the 3rd PMOS turn off, and internal node B point is equally in high-impedance state with internal node Qb point, keeps one state; And the noble potential of internal node B point makes the second NMOS tube conducting simultaneously, absorb the electric charge at Bb point place; The electronegative potential of internal node Qb point makes the first PMOS conducting, and absorb the electric charge at internal node Q point place, final internal node Q, Bb have returned to original current potential, and Data flipping returns " 1 " and " 0 ";
Internal node Bb when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 2nd PMOS is subject to high-energy particle bombardment, internal node Bb place current potential is dragged down, and roll data occurs and becomes " 0 ", makes the first NMOS tube turn off, the 3rd PMOS conducting simultaneously; After first NMOS tube conducting, internal node Q point is in high-impedance state, keeps the data " 0 " of electronegative potential; And after the 3rd PMOS conducting, the current potential at internal node B place is driven high, data become " 1 "; And then allowing the 4th PMOS turn off, internal node Qb is in high-impedance state, and data remain " 1 "; It is still " 0 " and " 1 " that the data of internal node Q and Qb point can not change, make the second PMOS and the 3rd NMOS tube conducting, internal node Bb and B point charging and discharging gradually, final internal node Bb, B have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Internal node B when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd NMOS is subject to high-energy particle bombardment, internal node B place current potential is driven high, and roll data occurs and becomes " 1 ", make the second NMOS tube conducting simultaneously, the 4th PMOS turns off; After second NMOS tube conducting, internal node Bb voltage is dragged down, and data variation is " 0 "; Make the first NMOS tube turn off, the 3rd PMOS conducting simultaneously; After first NMOS tube conducting, internal node Q point is in high-impedance state, keeps the data " 0 " of electronegative potential; And after the 3rd PMOS conducting, the current potential at internal node B place is driven high, data become " 1 "; And then allowing the 4th PMOS turn off, internal node Qb is in high-impedance state, and data remain " 1 "; It is still " 0 " and " 1 " that the data of internal node Q and Qb point can not change, make the second PMOS and the 3rd NMOS tube conducting, internal node Bb and B point charging and discharging gradually, final internal node Bb, B have returned to original current potential, and Data flipping returns " 1 " and " 0 ";
Internal node B when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd PMOS is subject to high-energy particle bombardment, internal node B place current potential is dragged down, and roll data occurs and becomes " 0 ", makes the second NMOS tube turn off, the 4th PMOS conducting simultaneously; Second NMOS tube is closed and is had no progeny, and internal node Bb is in high-impedance state, and keep current potential constant, data are still " 0 "; After 4th PMOS conducting, the voltage at internal node Qb place is dragged down, and data become " 1 ", and internal node B, Qb point overturns the state of maintenance " 0 " and " 1 " simultaneously; And the data of internal node Q and Bb point can not change still for " 1 " and " 0 ", make the 4th NMOS tube and the 3rd PMOS conducting, i.e. internal node B and Qb point charging and discharging gradually, final B, Qb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Internal node Qb when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 4th PMOS is subject to high-energy particle bombardment, internal node Qb place current potential is driven high, and roll data occurs and becomes " 0 ", makes the 3rd NMOS tube turn off, a PMOS conducting simultaneously; 3rd NMOS tube is closed and is had no progeny, and internal node B is in high-impedance state, and current potential remains unchanged, and data remain " 1 "; After one PMOS conducting, Q point voltage is driven high, and Data flipping is " 1 ", causes the 4th NMOS tube conducting, and the 2nd PMOS turns off; After 4th NMOS tube conducting, internal node Qb place voltage is also drop-down, makes it overturn; Internal node Q, Qb place overturns the state of maintenance " 1 " and " 0 " simultaneously; And internal node B and Bb place can not change still for " 0 " and " 1 ", make the 4th PMOS and the first NMOS tube conducting, namely discharge gradually and charge in internal node Q and Qb place, and final Q, Qb have returned to original current potential, and Data flipping returns " 0 " and " 1 ";
Internal node Qb when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 4th NMOS is subject to high-energy particle bombardment, internal node Qb place current potential is dragged down, and roll data occurs and becomes " 1 ", make the 3rd NMOS tube conducting simultaneously, a PMOS turns off; After 3rd NMOS tube conducting, internal node B current potential is dragged down, and data variation is " 0 "; One PMOS closes and has no progeny, and internal node Q is in high-impedance state, and current potential remains unchanged, and the second NMOS tube turns off, the 4th PMOS conducting; Second NMOS tube is closed and is had no progeny, and internal node Bb is in high-impedance state, and keep current potential constant, data are still " 0 "; After 4th PMOS conducting, the voltage at internal node Qb place is dragged down, and data become " 1 ", and internal node B, Qb point overturns the state of maintenance " 0 " and " 1 " simultaneously; And the data of internal node Q and Bb point can not change still for " 1 " and " 0 ", make the 4th NMOS tube and the 3rd PMOS conducting, i.e. internal node B and Qb point charging and discharging gradually, final B, Qb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Compared with prior art, the present invention has following useful technique effect:
Compared with traditional sense amplifier, the primary particle inversion resistant sense amplifier of one provided by the invention, while realizing sense amplifier function, has anti-single particle overturn reinforcement ability; According to TSMC 0.18um process simulation results, the present invention can realize turn threshold and be greater than 500MeVcm
2mg
-1.
The primary particle inversion resistant sense amplifier of one provided by the invention, circuit structure is simple, and time delay is short.Available standards manufacture technics of the present invention, does not need to increase extra special procedure.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention;
Wherein: 1 is pre-charge circuit, 2 is input control structure, and 3 is latch cicuit;
SE is working control signal line, and EN is that precharge controls letter wire size, and BL is the first complementary data input line, and BL# is the second complementary data input line, and OUT is the first complementary data output line, and OUT# is the second complementary data input line;
P1 ~ P11 is the first PMOS ~ the 11 PMOS, and N1 ~ N5 is the first NMOS tube ~ the 5th NMOS tube.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.
See Fig. 1, primary particle inversion resistant sense amplifier provided by the invention, comprises pre-charge circuit 1, input control structure 2 and latch cicuit 3;
The input port of pre-charge circuit 1 connects precharging signal line EN and two complementary data input line BL, BL# respectively, two complementary data input lines are connected with power supply by pre-charge circuit respectively, and two complementary data input lines are connected, make complementary data input line precharge balance;
The input end of input control structure 2 connects working control signal line SE, and the output terminal of the complementary data input line of pre-charge circuit; The output terminal of input control structure connects the internal node of latch cicuit, internal node and ground connection;
Latch cicuit 3 comprises multiple latch structure of cross-linked phase inverter composition and the phase inverter of multiple two-way feedback inverter composition, latch structure and phase inverter arranged in a crossed manner, internal node is arranged in the inside of latch structure, phase inverter, and internal node is between latch structure and phase inverter; The output terminal of latch cicuit connects two complementary data output lines OUT, OUT# respectively.
Further, pre-charge circuit 1 comprises three PMOS, and wherein two complementary data input lines are connected with power supply by two PMOS respectively, and two articles of complementary data input lines are connected by the 3rd PMOS;
Input control structure 2 is managed by multiple POMS and a NMOS tube forms, and POMS pipe is all connected with working control signal line SE with the grid of NMOS tube; The drain electrode of each PMOS is connected with one of latch cicuit internal node respectively, and source electrode is connected with one of two complementary data output lines; NMOS tube source ground, drain electrode connects latch cicuit internal node.
Concrete see Fig. 1, primary particle inversion resistant sense amplifier comprises: 5 NMOS tube and 11 PMOS, and wherein B, Bb, Q, Qb, N are internal node, consist of:
The grid of NMOS tube N1 meets Node B b, and drain electrode meets OUT, and source electrode meets node N, Substrate ground;
The grid of NMOS tube N2 connects Node B, and drain electrode meets Node B b, and source electrode meets node N, Substrate ground;
The grid of NMOS tube N3 meets OUT#, and drain electrode connects Node B, and source electrode meets node N, Substrate ground;
The grid of NMOS tube N4 meets OUT, and drain electrode meets OUT#, and source electrode meets node N, Substrate ground;
NMOS tube N5 grid meets SE, and drain electrode meets node N, source electrode and Substrate ground;
The grid of PMOS P1 meets OUT#, and drain electrode meets OUT, and source electrode and substrate meet power vd D;
The grid of PMOS P2 meets OUT, and drain electrode meets Node B b, and source electrode and substrate meet power vd D;
The grid of PMOS P3 meets Node B b, and drain electrode connects Node B, and source electrode and substrate meet power vd D;
The grid of PMOS P4 connects Node B, and drain electrode meets OUT#, and source electrode and substrate meet power vd D;
The grid of PMOS P5 meets SE, and drain electrode meets OUT, and source electrode meets BL, and substrate meets power vd D;
The grid of PMOS P6 meets SE, and drain electrode meets Node B b, and source electrode meets BL#, and substrate meets power vd D;
The grid of PMOS P7 meets SE, and drain electrode connects Node B, and source electrode meets BL, and substrate meets power vd D;
The grid of PMOS P8 meets SE, and drain electrode meets OUT#, and source electrode meets BL#, and substrate meets power vd D;
The grid of PMOS P9 meets EN, and drain electrode meets BL, and source electrode meets BL#, and substrate meets power vd D;
The grid of PMOS P10 meets EN, and drain electrode meets BL, and source electrode and substrate meet power vd D;
The grid of PMOS P11 meets EN, and drain electrode meets BL#, and source electrode and substrate meet power vd D.
In the sense amplifier course of work, now N5 conducting, P5, P6, P7 and P8 turn off.If node Q and B voltage are " 1 ", Node B b and Qb voltage are " 0 ".Then the drain junction of N1, N3, P2 and P4 is reverse-biased, therefore node Q, and B, Qb and Bb are sensitive nodes.
Its upset rejuvenation is as follows:
Internal node Q when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the first NMOS tube N1 is subject to high-energy particle bombardment, the voltage at internal node Q place is driven high, and makes the data variation of storage for " 1 ".This behavior causes the 4th NMOS tube N4 conducting, and the second PMOS P2 turns off; After 4th NMOS tube N4 conducting, internal node Qb voltage is also drop-down, makes it overturn; Therefore Q, Qb point overturns the state of maintenance " 1 " and " 0 " simultaneously.But it is still " 0 " and " 1 " that the data due to B and Bb point can not change, and make the 4th PMOS P4 and the first NMOS tube N1 conducting, namely Q and Qb point discharges gradually and charges.Finally, Q, Qb have returned to original current potential, and Data flipping returns " 0 " and " 1 ".
Internal node Q when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the first PMOS P1 is subject to high-energy particle bombardment, the voltage at internal node Q place is dragged down, and makes the data variation of storage for " 0 ".This behavior causes the 4th NMOS tube N4 to turn off, the second PMOS P2 conducting; 4th NMOS tube N4 closes and has no progeny, and internal node Qb is in high-impedance state, makes data keep " 0 "; After second PMOS P2 conducting, the current potential at Node B b place is driven high, and overturns, and data become " 1 ".The noble potential of Bb point makes the 3rd PMOS P3 turn off, and B point is equally in high-impedance state with Qb point, keeps one state.And the noble potential of B point makes the second NMOS tube N2 pipe conducting simultaneously, absorb the electric charge at Bb point place; The electronegative potential of Qb point makes the first PMOS conducting, absorbs the electric charge at Q point place.Finally, Q, Bb have returned to original current potential, and Data flipping returns " 1 " and " 0 "
Internal node Bb when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the second NMOS tube N2 is subject to high-energy particle bombardment, internal node Bb place current potential is driven high, and roll data occurs and becomes " 1 ".Make the first NMOS tube N1 conducting, the 3rd PMOS P3 turns off simultaneously; After first NMOS tube N1 conducting, internal node Q point voltage is dragged down, and data become " 0 ".After this rejuvenation after circuit reaction overturns by ionizing radiation when occuring as " 1 " with potential change and internal node Q is identical.
Internal node Bb when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the second PMOS P2 is subject to high-energy particle bombardment, internal node Bb place current potential is dragged down, and roll data occurs and becomes " 0 ".Make the first NMOS tube N1 turn off, the 3rd PMOS P3 conducting simultaneously; After first NMOS tube N1 conducting, internal node Q point is in high-impedance state, keeps the data " 0 " of electronegative potential.And after the 3rd PMOS P3 conducting, the current potential at Node B place is driven high, data become " 1 "; And then allowing the 4th PMOS P4 turn off, node Qb is in high-impedance state, and data remain " 1 ".But it is still " 0 " and " 1 " that the data due to Q and Qb point can not change, and makes the second PMOS P2 and the 3rd NMOS tube N3 conducting, i.e. Bb and B point charging and discharging gradually.Finally, Bb, B have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Internal node B when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd NMOS tube N3 is subject to high-energy particle bombardment, internal node B place current potential is driven high, and roll data occurs and becomes " 1 ".Make the second NMOS tube N2 conducting, the 4th PMOS P4 turns off simultaneously; After second NMOS tube N2 conducting, internal node Bb voltage is dragged down, and data variation is " 0 ".After this rejuvenation after circuit reaction overturns by ionizing radiation when occuring as " 1 " with potential change and internal node Bb is identical.
Internal node B when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd PMOS P3 is subject to high-energy particle bombardment, internal node B place current potential is dragged down, and roll data occurs and becomes " 0 ".Make the second NMOS tube N2 turn off, the 4th PMOS P4 conducting simultaneously; Second NMOS tube N2 closes and has no progeny, and internal node Bb is in high-impedance state, and keep current potential constant, data are still " 0 ".After 4th PMOS P4 conducting, the voltage at internal node Qb place is dragged down, and data become " 1 ".Namely B, Qb point overturns the state of maintenance " 0 " and " 1 " simultaneously.But it is still " 1 " and " 0 " that the data due to Q and Bb point can not change, and makes the 4th NMOS tube N4 and the 3rd PMOS P3 conducting, i.e. B and Qb point charging and discharging gradually.Finally, B, Qb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
Internal node Qb when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 4th PMOS P4 is subject to high-energy particle bombardment, internal node Qb place current potential is driven high, and roll data occurs and becomes " 0 ".Make the 3rd NMOS tube N3 turn off, the first PMOS P1 conducting simultaneously; 3rd NMOS tube N3 closes and has no progeny, and internal node B is in high-impedance state, and current potential remains unchanged, and data remain " 1 ".After first PMOS P1 conducting, Q point voltage is driven high, and Data flipping is " 1 ".After this rejuvenation after circuit reaction overturns by ionizing radiation when occuring as " 0 " with potential change and internal node Q is identical.
Internal node Qb when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 4th NMOS tube N4 is subject to high-energy particle bombardment, internal node Qb place current potential is dragged down, and roll data occurs and becomes " 1 ".Make the 3rd NMOS tube N3 conducting, the first PMOS P1 turns off simultaneously; After 3rd NMOS tube N3 conducting, internal node B current potential is dragged down, and data variation is " 0 ".First PMOS P1 closes and has no progeny, and internal node Q is in high-impedance state, and current potential remains unchanged.After this rejuvenation after circuit reaction overturns by ionizing radiation when occuring as " 1 " with potential change and internal node B is identical.
The present invention and traditional sense amplifier have carried out circuit transmission characteristic Simulation, and in circuit, by at key node (Q, Bb, B, Qb) inject transient pulse, reach and make the current potential of key node in the upset that very short time occurs instantaneously, monitor change in voltage and the contrast of anti-ion rollover characteristics of other key nodes, comparing result is as table 1.
The contrast of table 1 the present invention and traditional sense amplifier
| Preliminary filling and sense amplifier | The present invention | |
| Postpone | 0.19ns | 0.13ns |
| Critical charge | 0.052pC | 13.6pC |
| LET th | ＜5MeV·cm 2·mg -1 | ＞500MeV·cm 2·mg -1 |
Compared with traditional sense amplifier, critical charge value of the present invention is larger, and anti-single particle overturn reinforce stabilization is better; The basis having above-mentioned performance does not significantly increase delay, and basic and former amplifier is consistent; And larger LET
thindicate the energy absorption capability that device is larger.
Claims (9)
1. a primary particle inversion resistant sense amplifier, is characterized in that, comprises pre-charge circuit (1), input control structure (2) and latch cicuit (3);
The input port of pre-charge circuit connects precharging signal line (EN) and two complementary data input lines (BL, BL#) respectively, two complementary data input lines are connected with power supply by pre-charge circuit respectively, and two complementary data input lines are connected, make complementary data input line precharge balance;
The input end of input control structure connects working control signal line (SE), and the output terminal of the complementary data input line of pre-charge circuit; The output terminal of input control structure connects internal node and the earth point of latch cicuit;
Latch cicuit comprises the latch structure of multiple cross-linked phase inverter composition and the phase inverter of multiple two-way feedback inverter composition, latch structure and phase inverter arranged in a crossed manner, internal node is arranged in the inside of latch structure, phase inverter; The output terminal of latch cicuit connects two complementary data output lines (OUT, OUT#) respectively;
Described input control structure (2) comprises the 5th PMOS (P5), the 6th PMOS (P6), the 7th PMOS (P7), the 8th PMOS (P8) and the 5th NMOS tube (N5);
The grid of the 5th PMOS (P5) connects working control signal line (SE), and drain electrode connects the first complementary data output line (OUT), and source electrode connects the first complementary data input line (BL), and substrate connects power supply;
The grid of the 6th PMOS (P6) connects working control signal line (SE), and drain electrode meets internal node Bb, and source electrode connects the second complementary data input line (BL#), and substrate connects power supply;
The grid of the 7th PMOS (P7) connects working control signal line (SE), and drain electrode meets internal node B, and source electrode connects the first complementary data input line (BL), and substrate connects power supply;
The grid of the 8th PMOS (P8) connects working control signal line (SE), and drain electrode connects the second complementary data output line (OUT#), and source electrode connects the second complementary data input line (BL#), and substrate connects power supply;
5th NMOS tube (N5) grid connects working control signal line (SE), and drain electrode meets internal node N, source electrode and Substrate ground;
Latch cicuit (3) is made up of the first PMOS (P1), the first NMOS tube (N1), the second PMOS (P2), the second NMOS tube (N2), the 3rd PMOS (P3), the 3rd NMOS tube (N3), the 4th PMOS (P4) and the 4th NMOS tube (N4);
The grid of the first PMOS (P1) connects the second complementary data output line (OUT#), and drain electrode connects the first complementary data output line (OUT), and source electrode and substrate connect power supply;
The grid of the first NMOS tube (N1) meets internal node Bb, and drain electrode connects the first complementary data output line (OUT), and source electrode meets internal node N, Substrate ground;
The grid of the second PMOS (P2) connects the first complementary data output line (OUT), and drain electrode meets internal node Bb, and source electrode and substrate connect power supply;
The grid of the second NMOS tube (N2) meets internal node B, and drain electrode meets internal node Bb, and source electrode meets internal node N, Substrate ground;
The grid of the 3rd PMOS (P3) meets internal node Bb, and drain electrode meets internal node B, and source electrode and substrate connect power supply;
The grid of the 3rd NMOS tube (N3) connects the second complementary data output line (OUT#), and drain electrode meets internal node B, and source electrode meets internal node N, Substrate ground;
The grid of the 4th PMOS (P4) meets internal node B, and drain electrode connects the second complementary data output line (OUT#), and source electrode and substrate connect power supply;
The grid of the 4th NMOS tube (N4) connects the first complementary data output line (OUT), and drain electrode connects the second complementary data output line (OUT#), and source electrode meets internal node N, Substrate ground.
2. primary particle inversion resistant sense amplifier as claimed in claim 1, it is characterized in that, described pre-charge circuit (1) comprises three PMOS, wherein two complementary data input lines are connected with power supply by two PMOS respectively, and two articles of complementary data input lines are connected by the 3rd PMOS.
3. primary particle inversion resistant sense amplifier as claimed in claim 1, it is characterized in that, described input control structure (2) is managed by multiple POMS and a NMOS tube forms, and POMS pipe is all connected with working control signal line (SE) with the grid of NMOS tube; The drain electrode of each PMOS is connected with one of latch cicuit internal node respectively, and source electrode is connected with one of two complementary data output lines; NMOS tube source ground, drain electrode connects latch cicuit internal node.
4. primary particle inversion resistant sense amplifier as claimed in claim 1, is characterized in that, described pre-charge circuit (1) comprises three PMOS, consists of:
The grid of the 9th PMOS (P9) connects precharging signal line (EN), and drain electrode connects the first complementary data input line (BL), and source electrode connects the second complementary data input line (BL#), and substrate connects power supply;
The grid of the tenth PMOS (P10) connects precharging signal line (EN), and drain electrode connects the first complementary data input line (BL), and source electrode and substrate connect power supply;
The grid of the 11 PMOS (P11) connects precharging signal line (EN), and drain electrode connects the second complementary data input line (BL#), and source electrode and substrate connect power supply.
5. primary particle inversion resistant sense amplifier as claimed in claim 1, it is characterized in that, in the course of the work, 5th NMOS tube (N5) conducting, the 5th PMOS (P5), the 6th PMOS (P6), the 7th PMOS (P7) and the 8th PMOS (P8) turn off; If internal node Q and B voltage are " 1 ", internal node Bb and Qb voltage are " 0 ", then the drain electrode of the first NMOS tube (N1), the 3rd NMOS tube (N3), the second PMOS (P2) and the 4th PMOS (P4) is reverse-biased; Internal node Q, B, Qb and Bb are sensitive nodes.
6. primary particle inversion resistant sense amplifier as claimed in claim 5, is characterized in that, when internal node Q occurs as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the first NMOS tube (N1) is subject to high-energy particle bombardment, the voltage at internal node Q place is driven high, and make the data variation of storage for " 1 ", cause the 4th NMOS tube (N4) conducting, the second PMOS (P2) turns off; After 4th NMOS tube (N4) conducting, internal node Qb place voltage is also drop-down, makes it overturn; Internal node Q, Qb place overturns the state of maintenance " 1 " and " 0 " simultaneously; And internal node B and Bb place can not change still for " 0 " and " 1 ", make the 4th PMOS (P4) and the first NMOS tube (N1) conducting, namely discharge gradually and charge in internal node Q and Qb place, final Q, Qb have returned to original current potential, and Data flipping returns " 0 " and " 1 ";
Internal node Q when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the first PMOS (P1) is subject to high-energy particle bombardment, the voltage at internal node Q place is dragged down, and makes the data variation of storage for " 0 ", causes the 4th NMOS tube (N4) to turn off, the second PMOS (P2) conducting; 4th NMOS tube (N4) is closed and is had no progeny, and internal node Qb is in high-impedance state, makes data keep " 0 "; After second PMOS (P2) conducting, the current potential at internal node Bb place is driven high, and overturns, and data become " 1 "; The noble potential at internal node Bb place makes the 3rd PMOS (P3) turn off, and internal node B point is equally in high-impedance state with internal node Qb point, keeps one state; And the noble potential of internal node B point makes the conducting of the second NMOS tube (N2) pipe simultaneously, absorb the electric charge at Bb point place; The electronegative potential of internal node Qb point makes the first PMOS (P1) conducting, and absorb the electric charge at internal node Q point place, final internal node Q, Bb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
7. primary particle inversion resistant sense amplifier as claimed in claim 5, is characterized in that: when internal node Bb occurs as " 0 " by the rejuvenation after ionizing radiation upset be:
When the drain terminal of the second NMOS tube (N2) is subject to high-energy particle bombardment, internal node Bb place current potential is driven high, and roll data occurs and becomes " 1 ", make the first NMOS tube (N1) conducting simultaneously, the 3rd PMOS (P3) turns off; After first NMOS tube (N1) conducting, internal node Q point voltage is dragged down, and data become " 0 ", causes the 4th NMOS tube (N4) to turn off, the second PMOS (P2) conducting; 4th NMOS tube (N4) is closed and is had no progeny, and internal node Qb is in high-impedance state, makes data keep " 0 "; After second PMOS (P2) conducting, the current potential at internal node Bb place is driven high, and overturns, and data become " 1 "; The noble potential at internal node Bb place makes the 3rd PMOS (P3) turn off, and internal node B point is equally in high-impedance state with internal node Qb point, keeps one state; And the noble potential of internal node B point makes the conducting of the second NMOS tube (N2) pipe simultaneously, absorb the electric charge at Bb point place; The electronegative potential of internal node Qb point makes the first PMOS (P1) conducting, and absorb the electric charge at internal node Q point place, final internal node Q, Bb have returned to original current potential, and Data flipping returns " 1 " and " 0 ";
Internal node Bb when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the second PMOS (P2) is subject to high-energy particle bombardment, internal node Bb place current potential is dragged down, and roll data occurs and becomes " 0 ", make the first NMOS tube (N1) turn off, the 3rd PMOS (P3) conducting simultaneously; After first NMOS tube (N1) conducting, internal node Q point is in high-impedance state, keeps the data " 0 " of electronegative potential; And after the 3rd PMOS (P3) conducting, the current potential at internal node B place is driven high, data become " 1 "; And then allowing the 4th PMOS (P4) turn off, internal node Qb is in high-impedance state, and data remain " 1 "; It is still " 0 " and " 1 " that the data of internal node Q and Qb point can not change, make the second PMOS (P2) and the 3rd NMOS tube (N3) conducting, internal node Bb and B point charging and discharging gradually, final internal node Bb, B have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
8. primary particle inversion resistant sense amplifier as claimed in claim 5, is characterized in that, when internal node B occurs as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd NMOS tube (N3) is subject to high-energy particle bombardment, internal node B place current potential is driven high, and roll data occurs and becomes " 1 ", make the second NMOS tube (N2) conducting simultaneously, the 4th PMOS (P4) turns off; After second NMOS tube (N2) conducting, internal node Bb voltage is dragged down, and data variation is " 0 "; Make the first NMOS tube (N1) turn off, the 3rd PMOS (P3) conducting simultaneously; After first NMOS tube (N1) conducting, internal node Q point is in high-impedance state, keeps the data " 0 " of electronegative potential; And after the 3rd PMOS (P3) conducting, the current potential at internal node B place is driven high, data become " 1 "; And then allowing the 4th PMOS (P4) turn off, internal node Qb is in high-impedance state, and data remain " 1 "; It is still " 0 " and " 1 " that the data of internal node Q and Qb point can not change, make the second PMOS (P2) and the 3rd NMOS tube (N3) conducting, internal node Bb and B point charging and discharging gradually, final internal node Bb, B have returned to original current potential, and Data flipping returns " 1 " and " 0 ";
Internal node B when occuring as " 1 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 3rd PMOS (P3) is subject to high-energy particle bombardment, internal node B place current potential is dragged down, and roll data occurs and becomes " 0 ", make the second NMOS tube (N2) turn off, the 4th PMOS (P4) conducting simultaneously; Second NMOS tube (N2) is closed and is had no progeny, and internal node Bb is in high-impedance state, and keep current potential constant, data are still " 0 "; After 4th PMOS (P4) conducting, the voltage at internal node Qb place is dragged down, and data become " 1 ", and internal node B, Qb point overturns the state of maintenance " 0 " and " 1 " simultaneously; And the data of internal node Q and Bb point can not change still for " 1 " and " 0 ", make the 4th NMOS tube (N4) and the 3rd PMOS (P3) conducting, i.e. internal node B and Qb point charging and discharging gradually, final B, Qb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
9. primary particle inversion resistant sense amplifier as claimed in claim 5, is characterized in that: when internal node Qb occurs as " 1 " by the rejuvenation after ionizing radiation upset be:
When the drain terminal of the 4th PMOS (P4) is subject to high-energy particle bombardment, internal node Qb place current potential is driven high, and roll data occurs and becomes " 0 ", makes the 3rd NMOS tube (N3) turn off, the first PMOS (P1) conducting simultaneously; 3rd NMOS tube (N3) is closed and is had no progeny, and internal node B is in high-impedance state, and current potential remains unchanged, and data remain " 1 "; After first PMOS (P1) conducting, Q point voltage is driven high, and Data flipping is " 1 ", causes the 4th NMOS tube (N4) conducting, and the second PMOS (P2) turns off; After 4th NMOS tube (N4) conducting, internal node Qb place voltage is also drop-down, makes it overturn; Internal node Q, Qb place overturns the state of maintenance " 1 " and " 0 " simultaneously; And internal node B and Bb place can not change still for " 0 " and " 1 ", make the 4th PMOS (P4) and the first NMOS tube (N1) conducting, namely discharge gradually and charge in internal node Q and Qb place, final Q, Qb have returned to original current potential, and Data flipping returns " 0 " and " 1 ";
Internal node Qb when occuring as " 0 " by the rejuvenation after ionizing radiation upset is:
When the drain terminal of the 4th NMOS tube (N4) is subject to high-energy particle bombardment, internal node Qb place current potential is dragged down, and roll data occurs and becomes " 1 ", make the 3rd NMOS tube (N3) conducting simultaneously, the first PMOS (P1) turns off; After 3rd NMOS tube (N3) conducting, internal node B current potential is dragged down, and data variation is " 0 "; First PMOS (P1) is closed and is had no progeny, and internal node Q is in high-impedance state, and current potential remains unchanged, and the second NMOS tube (N2) turns off, the 4th PMOS (P4) conducting; Second NMOS tube (N2) is closed and is had no progeny, and internal node Bb is in high-impedance state, and keep current potential constant, data are still " 0 "; After 4th PMOS (P4) conducting, the voltage at internal node Qb place is dragged down, and data become " 1 ", and internal node B, Qb point overturns the state of maintenance " 0 " and " 1 " simultaneously; And the data of internal node Q and Bb point can not change still for " 1 " and " 0 ", make the 4th NMOS tube (N4) and the 3rd PMOS (P3) conducting, i.e. internal node B and Qb point charging and discharging gradually, final B, Qb have returned to original current potential, and Data flipping returns " 1 " and " 0 ".
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| CN110995236B (en) * | 2019-12-26 | 2022-04-26 | 中北大学 | High-frequency circuit application-oriented charge sharing resistant D latch |
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| CN102025351A (en) * | 2010-12-08 | 2011-04-20 | 西安交通大学 | SEU (single event upset)/SET (single event transient)-resistant dynamic comparator |
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