CN203673380U - Multi-power-source power supply selection circuit - Google Patents
Multi-power-source power supply selection circuit Download PDFInfo
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- CN203673380U CN203673380U CN201320747341.6U CN201320747341U CN203673380U CN 203673380 U CN203673380 U CN 203673380U CN 201320747341 U CN201320747341 U CN 201320747341U CN 203673380 U CN203673380 U CN 203673380U
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Abstract
The utility model discloses a multi-power-source power supply selection circuit. The multi-power-source power supply selection circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor. According to the multi-power-source power supply selection circuit, just one transistor needs to be arranged on an access between a programming power source and a programming node, the number of the transistor on the access between the programming power source and the programming node can be greatly reduced, and therefore the area of the transistor can be greatly reduced. Under the condition of the same conduction resistance, the area can be reduced by four times, and therefore the area of the whole circuit can be reduced.
Description
Technical field
The utility model relates to programming device field, particularly relates to the multiple feed selection circuit that a kind of SOC (system on a chip) need to be used in the time that programming device carries out burning.
Background technology
Programming device generally can carry out burning, so that programming device is carried out corresponding function according to the content of burning.When SOC (system on a chip) is in the time carrying out burning to programming device, need to utilize selection circuit, circuit, FPGA (Field Programmable Gate Array) programming feed circuit, Flash programming feed circuit or OTP programming feed circuit etc. are selected in for example multiple feed, thereby to introduce high voltage to programming device, programming device are carried out to burning.
Fig. 1 is the circuit diagram that circuit is selected in a kind of existing multiple feed.As shown in Figure 1, multiple feed selects circuit 10 to comprise PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, nmos pass transistor MN1, nmos pass transistor MN2, resistance 11, resistance 12, resistance 13, resistance 14, load capacitance 15, low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) 16, phase inverter 17, electric capacity 18, programming power supply Vprog, power vd D, power supply selection signal Power_Sel.
Wherein, the drain electrode of PMOS transistor MP1 is electrically connected programming power supply Vprog, and node a between programming power supply Vprog and the drain electrode of PMOS transistor MP1 passes through resistance 11 ground connection.The source electrode of the source electrode of PMOS transistor MP1 and PMOS transistor MP2 is electrically connected, and the grid of the grid of PMOS transistor MP1 and PMOS transistor MP2 is electrically connected, and node b between the source electrode of PMOS transistor MP1 and the source electrode of PMOS transistor MP2 is electrically connected to the node c between the grid of PMOS transistor MP1 and the grid of PMOS transistor MP2 by resistance 12.Node c is electrically connected to the drain electrode of nmos pass transistor MN1 by resistance 13, the source ground of nmos pass transistor MN1, and the grid of nmos pass transistor MN1 is electrically connected power supply selection signal Power_Sel.The grid of nmos pass transistor MN2 is electrically connected to power supply by phase inverter 17 and selects signal Power_Sel, its source ground, and its drain electrode is electrically connected to the drain electrode of PMOS transistor MP2 by resistance 14.The source electrode of PMOS transistor MP3 is electrically connected to the drain electrode of PMOS transistor MP2, its source electrode is electrically connected to the output terminal of low pressure difference linear voltage regulator 16, and its source electrode further passes through electric capacity 18 and ground connection, and its grid is electrically connected to the drain electrode of nmos pass transistor MN2.The input end of low pressure difference linear voltage regulator 16 is electrically connected power vd D.And the drain electrode of PMOS transistor MP2 is further used as programming node flash, it passes through load capacitance 15 and ground connection.
In the time that programming power supply Vprop does not load, the voltage on node a is pulled low to ground level by resistance 11.Now, power supply selects signal Power_Sel in low level, and therefore nmos pass transistor MN1 is correspondingly in cut-off state, and due to the effect of phase inverter 17, nmos pass transistor MN2 is in conducting state.Because nmos pass transistor MN1 is in cut-off state, and the source electrode of PMOS transistor MP1 and PMOS transistor MP2 and grid pass through resistance 12 and short circuit, and therefore PMOS transistor MP1 and PMOS transistor MP2 are in cut-off state.Because PMOS transistor MP1 and PMOS transistor MP2 are in cut-off state, therefore it has cut off programming power supply Vprop to the path between programming node flash.Simultaneously, because nmos pass transistor MN2 is in conducting state, therefore the grid of PMOS transistor MP3 by the nmos pass transistor MN2 of conducting ground connection, be that voltage on the grid of PMOS transistor MP3 is pulled low to ground level, PMOS transistor MP3 is in conducting state, and the voltage that low pressure difference linear voltage regulator 16 produces transfers to programming node flash by the PMOS transistor MP3 of conducting.
In the time that programming power supply Vprop is loaded, the voltage of the power of voltage ratio VDD of programming power supply Vprop wants high conventionally, therefore in the time of design, need to avoid especially the feedthrough from programming power supply Vprop to power vd D and between low pressure difference linear voltage regulator 16.Now, power supply selects signal Power_Sel in high level, and nmos pass transistor MN1 is in conducting state, and due to the effect of phase inverter 17, nmos pass transistor MN2 is in cut-off state.Because nmos pass transistor MN1 is in conducting state, and the effect of the bleeder circuit that PMOS transistor MP1 and PMOS transistor MP2 form due to resistance 12 and resistance 13 and in conducting state, the voltage that therefore programming power supply Vprop loads transfers to programming node flash by PMOS transistor MP1 and the PMOS transistor MP2 of conducting.In addition, due to, because nmos pass transistor MN2 is in cut-off state, and the grid of PMOS transistor MP3 and source electrode are shorted together by resistance 14, therefore PMOS transistor MP3 is in cut-off state, and therefore the output voltage of low pressure difference linear voltage regulator 16 can't transfer to programming node flash.Voltage on programming node flash is the voltage that programming power supply Vprop loads, and the voltage of the power of voltage ratio VDD loading due to programming power supply Vprop wants high, be that the voltage that programming power supply Vprop loads equals the voltage on programming node flash, and it is greater than the voltage of power vd D, and the voltage of power vd D is greater than the output voltage of low pressure difference linear voltage regulator 16 certainly, therefore PMOS transistor MP3 is in cut-off state completely, programming power supply Vprop does not have feedthrough between low pressure difference linearity stabilizator 16, and programming power supply Vprop does not have feedthrough between power vd D yet.
But, when SOC (system on a chip) is during in programming/programming state, during to programme/programming of programming device, larger electric current need to be provided, therefore select to have on circuit the restriction of maximum access resistance in multiple feed, limit programming power supply Vprop to the path between programming node flash the resistance when the conducting, at this, the resistance while being mainly back-to-back PMOS transistor MP1 and PMOS transistor MP2 conducting.Because electric current can produce voltage drop when by back-to-back PMOS transistor MP1 and PMOS transistor MP2, it can affect the effective voltage of programming node flash, thus the effect of impact programming/programming.Suppose that the maximum access resistance that multiple feed selects circuit to allow is R0, and a transistorized area of PMOS of corresponding maximum access resistance R 0 is a, because PMOS transistor MP1 and PMOS transistor MP2 are cascaded, therefore each the transistorized area in PMOS transistor MP1 and PMOS transistor MP2 must be more than or equal to 2a, PMOS transistor MP1 and two transistorized total areas of PMOS transistor MP2 are more than or equal to 4a, and PMOS transistor MP1 and the resistance sum of PMOS transistor MP2 under conducting state of guarantee series connection are less than or equal to R0.That is to say, need to, with the PMOS transistor MP1 of 4 times of areas and two transistors of PMOS transistor MP2, could obtain satisfactory conducting resistance at this, it can increase the area of whole circuit undoubtedly, and has additionally increased cost.
Utility model content
The technical matters that the utility model mainly solves is to provide a kind of multiple feed and selects circuit, and it can reduce the transistorized quantity on programming power supply and programming node path, thereby can greatly reduce transistorized area.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: provide a kind of multiple feed to select circuit, it comprises the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor.The drain electrode of described the first transistor is electrically connected to programming power supply, and wherein, the node definition between the drain electrode of described the first transistor and described programming power supply is first node.The drain electrode of described transistor seconds is electrically connected to internal electric source, its grid and source electrode are electrically connected, and be further electrically connected to the source electrode of described the first transistor, wherein, the node definition between the source electrode of the grid of described transistor seconds and source electrode and described the first transistor is Section Point.Described the 3rd transistorized source electrode is electrically connected to described first node, and its back grid is electrically connected to described Section Point, and its grid is electrically connected to described Section Point by the first resistance, and it drains as programming node.Described the 4th transistorized source electrode is electrically connected to described programming node, and its grid is electrically connected to its source electrode by the second resistance, and its drain electrode is electrically connected to described internal electric source by low pressure difference linear voltage regulator.Described the 5th transistorized grid receives power supply and selects signal, its source ground, and its drain electrode is electrically connected to the source electrode of described the first transistor by bleeder circuit, wherein, the grid of described the first transistor is electrically connected at the dividing potential drop node in described bleeder circuit.Described the 6th transistorized grid receives described power supply and selects signal, its source ground, and its drain electrode is electrically connected the 3rd transistorized grid.Described the 7th transistorized grid is electrically connected described power supply by phase inverter and selects signal, its source ground, and its drain electrode is electrically connected described the 4th transistorized grid.Wherein, described the first transistor, described transistor seconds, described the 3rd transistor and described the 4th transistor are respectively first kind transistor, and described the 5th transistor, described the 6th transistor and described the 7th transistor are respectively the Second Type transistor contrary with described first kind transistor.
Wherein, described first kind transistor is PMOS transistor, and described Second Type transistor is nmos pass transistor.
Wherein, described bleeder circuit comprises the 3rd resistance and the 4th resistance.Wherein, described the 3rd resistance and described the 4th resistance are cascaded, and node between described the 3rd resistance and the 4th resistance is as described dividing potential drop node.
Wherein, the grid of described the first transistor is electrically connected the source electrode of described the first transistor by described the 3rd resistance.
Wherein, described multiple feed selects circuit further to comprise the 6th resistance, and it is electrically connected between described first node and ground.
Wherein, described multiple feed selects circuit further to comprise load capacitance, and it is electrically connected between described programming node and ground.
Wherein, described multiple feed selects circuit further to comprise electric capacity, and it is electrically connected between described the 4th transistorized drain electrode and ground.
The beneficial effects of the utility model are: the situation that is different from prior art, multiple feed of the present utility model selects circuit can reduce the transistorized quantity on programming power supply Vprop and programming node Flash path, thereby can greatly reduce transistorized area, the in the situation that of equal conduction impedance, can realize the area reduction of 4 times, thereby reduce the area of whole circuit.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that circuit is selected in a kind of existing multiple feed; And
Fig. 2 is the circuit diagram that circuit is selected in the multiple feed of the utility model embodiment.
Embodiment
Fig. 2 is the circuit diagram that circuit is selected in the multiple feed of the utility model embodiment.As shown in Figure 2, the multiple feed of the utility model embodiment selects circuit 200 to comprise transistor 210, transistor 220, transistor 230, transistor 240, transistor 250, transistor 260 and transistor 270.Wherein, transistor 210, transistor 220, transistor 230 and transistor 240 are respectively first kind transistor, and in the present embodiment, it can be respectively PMOS transistor; And transistor 250, transistor 260 and transistor 270 are respectively the Second Type transistor contrary with first kind transistor, in the present embodiment, it can be respectively nmos pass transistor.
Particularly, the drain electrode of transistor 210 is electrically connected to programming power supply Vprop, and node A between the drain electrode of transistor 210 and programming power supply Vprop can be further by resistance 211 and ground connection.And the source electrode of transistor 210 can be electrically connected to by bleeder circuit 280 drain electrode of transistor 250, and the grid of transistor 210 is electrically connected at the dividing potential drop Node B in bleeder circuit 280.
Wherein, bleeder circuit 280 can be made up of resistance 281 and resistance 282, and resistance 281 and resistance 282 are cascaded, and Node B between resistance 281 and resistance 282 is as the dividing potential drop node in bleeder circuit 280.That is to say, the grid of transistor 210 is electrically connected its source electrode by resistance 281.
The drain electrode of transistor 220 is electrically connected to internal electric source VDD, its grid and source electrode are electrically connected, and be further electrically connected to the source electrode of transistor 210, at this, the tie point that can define between the grid of transistor 220 and the source electrode of source electrode and transistor 210 is node C.
The source electrode of transistor 230 is electrically connected to node A, and its back grid is electrically connected to node C, and its grid is electrically connected to node C by resistance 231, and its drain electrode is as programming node Flash.Preferably, programming node Flash can further pass through load capacitance 235 and ground connection.
The source electrode of transistor 240 is electrically connected to programming node Flash, and its grid is electrically connected to its source electrode by resistance 241, and its drain electrode is electrically connected to internal electric source VDD by low pressure difference linear voltage regulator 290.In other words, the input end of low pressure difference linear voltage regulator 290 is electrically connected internal electric source VDD, and the output terminal of low pressure difference linear voltage regulator 290 is electrically connected the drain electrode of transistor 240, so that the drain electrode of transistor 240 can receive the output voltage V LDO of low pressure difference linear voltage regulator 290.Wherein, the output voltage V LDO that compresses difference linear constant voltage regulator 290 is less than the magnitude of voltage of internal electric source VDD.In addition, the drain electrode of transistor 240 can further be passed through electric capacity 245 and ground connection.
The grid of transistor 250 is electrically connected power supply and selects signal Power_Sel, its source ground, and its drain electrode is the source electrode that is electrically connected transistor 210 by bleeder circuit 280.
The grid of transistor 260 is electrically connected power supply and selects signal Power_Sel, its source ground, and its drain electrode is electrically connected to the grid of transistor 230.
The grid of transistor 270 is electrically connected power supply by phase inverter 271 and selects signal Power_Sel, its source ground, and its drain electrode is electrically connected the grid of transistor 240.
Below the multiple feed of introducing particularly the utility model embodiment is selected to the principle of work of circuit.
In the time that programming power supply Vprop does not load, the voltage on node A can be pulled low to ground level by resistance 211.Now, power supply selects signal Power_Sel in low level, and because transistor 250, transistor 260 and transistor 270 are nmos pass transistor, transistor 250 and transistor 260 are in complete cut-off state; Meanwhile, due to the effect of phase inverter 271, transistor 270 is in complete conducting state.
Because transistor 250 is in complete cut-off state, and because grid and the source electrode of transistor 210 are PMOS transistor by 281 short circuits of resistance and transistor 210, therefore transistor 210 is in cut-off state.Because the voltage of node C (being the voltage on the back grid of transistor 230) depends on relatively high voltage in node A (being programming power supply Vprop loading place) and internal electric source VDD completely, and at this moment, because programming power supply Vprop does not load, internal electric source VDD is higher than the voltage on node A, and the grid of transistor 220 and source electrode are electrically connected, therefore the voltage of node C approximates greatly internal electric source VDD and deducts the voltage drop of the body diode of transistor 220, and the voltage of node C approximates greatly internal electric source VDD.
Because transistor 260 is in complete cut-off state, and the grid of transistor 230 is electrically connected to node C by resistance 231, and therefore the voltage on the grid of transistor 230 equals the voltage of node C.Because transistor 270 is in complete conducting state, and the grid of transistor 240 by the transistor 270 of conducting ground connection, and transistor 240 is PMOS transistor, therefore transistor 240 is in conducting state.Now, the source ground of transistor 230, and its drain electrode connects the output terminal of low pressure difference linear voltage regulator 290 by the transistor 240 of conducting, therefore the voltage in the drain electrode of transistor 230 equals the output voltage V LDO of low pressure difference linear voltage regulator 290.Because the output voltage V LDO of low pressure difference linear voltage regulator 290 generally can be than more than the little 1V of the magnitude of voltage of internal electric source VDD, therefore the voltage in the drain electrode of transistor 230 is lower than the voltage on the grid of the voltage on node C and transistor 230, and transistor 230 is PMOS transistor, it can guarantee that transistor 230 is in cut-off state.
And in the time that programming power supply Vprop loads, the voltage on node A is higher than the voltage of internal electric source VDD, therefore in the time that power supply selects signal Power_Sel to become high level, because transistor 250, transistor 260 and transistor 270 are nmos pass transistor, transistor 250 and transistor 260 are in complete conducting state; Meanwhile, due to the effect of phase inverter 271, transistor 270 is in complete cut-off state.
Because transistor 250 is in complete conducting state, and transistor 210 is due to the effect of bleeder circuit 280, and therefore it is in conducting state.
Now, node C is because the conducting of transistor 210 equals the voltage of the programming power supply Vprop that node A loads.The source electrode of transistor 230 is electrically connected node A, and therefore the voltage on it also equals the voltage of the programming power supply Vprop that node A loads; And the grid of transistor 230 by the transistor 260 of complete conducting ground connection, and transistor 230 is PMOS transistor, therefore transistor 230 is in complete conducting state.Voltage on programming node Flash equals node A and loads the voltage of programming power supply Vprop.
Now, voltage on the source electrode of transistor 220 is because transistor 210 conductings equal the voltage of the programming power supply Vprop that node A loads, and its drain electrode on voltage equal the voltage that internal electric source VDD provides, and because the voltage of the programming power supply Vprop loading generally all can be greater than the voltage that internal electric source VDD provides, therefore the body diode of transistor 220 is in reverse-bias state, therefore, in the time that programming power supply Vprop loads, between programming power supply Vprop and internal electric source VDD, there is not any path.
And, because the voltage on programming node Flash is because the transistor 230 of completely conducting equals the voltage of the programming power supply Vprop that node A loads, the source electrode of transistor 240 is electrically connected programming node Flash, its grid is because transistor 270 passes through resistance 241 shorted source in complete cut-off state, its drain electrode receives the output voltage V LDO of low pressure difference linear voltage regulator 290, it is less than the voltage of programming power supply Vprop, therefore the body diode of transistor 240 is also in reverse-bias state, therefore, in the time that programming power supply Vprop loads, between the output voltage V LDO of programming power supply Vprop and low pressure difference linear voltage regulator 290, there is not any path yet.
In the time loading programming power supply Vprop, to the large current path between programming node Flash, only there is a PMOS transistor in programming power supply Vprop, it is the transistor 230 of conducting, and not as prior art, there are two PMOS transistors, therefore in the utility model, can reduce the transistorized quantity on programming power supply Vprop and programming node Flash path, thereby can greatly reduce transistorized area, the in the situation that of equal conduction impedance, can realize the area reduction of 4 times, thereby reduce the area of whole circuit.
Although, in the utility model embodiment, the transistorized switch drive mode of each first kind is to realize by the mode of electric resistance partial pressure, but, it will be understood by those skilled in the art that, the transistorized switch drive mode of each first kind also can adopt other switch driving circuit to replace, for example logic gate, push-pull output stage etc. mode.In addition, those skilled in the art are passable, and at programming power supply Vprop, to the path of internal electric source VDD, transistor 220 also can be operated on off state, just add a way switch control circuit to control the switch of transistor 220.
The foregoing is only embodiment of the present utility model; not thereby limit the scope of the claims of the present utility model; every equivalent structure or conversion of equivalent flow process that utilizes the utility model instructions and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.
Claims (7)
1. a circuit is selected in multiple feed, it is characterized in that, comprising:
The first transistor, its drain electrode is electrically connected to programming power supply, and wherein, the node definition between the drain electrode of described the first transistor and described programming power supply is first node;
Transistor seconds, its drain electrode is electrically connected to internal electric source, its grid and source electrode are electrically connected, and be further electrically connected to the source electrode of described the first transistor, wherein, the node definition between the source electrode of the grid of described transistor seconds and source electrode and described the first transistor is Section Point;
The 3rd transistor, its source electrode is electrically connected to described first node, and its back grid is electrically connected to described Section Point, and its grid is electrically connected to described Section Point by the first resistance, and it drains as programming node;
The 4th transistor, its source electrode is electrically connected to described programming node, and its grid is electrically connected to its source electrode by the second resistance, and its drain electrode is electrically connected to described internal electric source by low pressure difference linear voltage regulator;
The 5th transistor, its grid receives power supply and selects signal, its source ground, and its drain electrode is electrically connected to the source electrode of described the first transistor by bleeder circuit, wherein, the grid of described the first transistor is electrically connected at the dividing potential drop node in described bleeder circuit;
The 6th transistor, its grid receives described power supply and selects signal, its source ground, and its drain electrode is electrically connected the 3rd transistorized grid;
The 7th transistor, its grid is electrically connected described power supply by phase inverter and selects signal, its source ground, and its drain electrode is electrically connected described the 4th transistorized grid;
Wherein, described the first transistor, described transistor seconds, described the 3rd transistor and described the 4th transistor are respectively first kind transistor, and described the 5th transistor, described the 6th transistor and described the 7th transistor are respectively the Second Type transistor contrary with described first kind transistor.
2. circuit is selected in multiple feed according to claim 1, it is characterized in that, described first kind transistor is PMOS transistor, and described Second Type transistor is nmos pass transistor.
3. circuit is selected in multiple feed according to claim 2, it is characterized in that, described bleeder circuit comprises:
The 3rd resistance,
The 4th resistance, wherein, described the 3rd resistance and described the 4th resistance are cascaded, and node between described the 3rd resistance and the 4th resistance is as described dividing potential drop node.
4. circuit is selected in multiple feed according to claim 3, it is characterized in that, the grid of described the first transistor is electrically connected the source electrode of described the first transistor by described the 3rd resistance.
5. circuit is selected in multiple feed according to claim 2, it is characterized in that, further comprises:
The 6th resistance, it is electrically connected between described first node and ground.
6. circuit is selected in multiple feed according to claim 2, it is characterized in that, further comprises:
Load capacitance, it is electrically connected between described programming node and ground.
7. circuit is selected in multiple feed according to claim 2, it is characterized in that, further comprises:
Electric capacity, it is electrically connected between described the 4th transistorized drain electrode and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320747341.6U CN203673380U (en) | 2013-02-28 | 2013-11-21 | Multi-power-source power supply selection circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310065210.4 | 2013-02-28 | ||
| CN201310065210 | 2013-02-28 | ||
| CN201320747341.6U CN203673380U (en) | 2013-02-28 | 2013-11-21 | Multi-power-source power supply selection circuit |
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| CN203673380U true CN203673380U (en) | 2014-06-25 |
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|---|---|---|---|
| CN201320747341.6U Withdrawn - After Issue CN203673380U (en) | 2013-02-28 | 2013-11-21 | Multi-power-source power supply selection circuit |
| CN201310594751.6A Active CN104020809B (en) | 2013-02-28 | 2013-11-21 | Multiple feed selection circuit |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310594751.6A Active CN104020809B (en) | 2013-02-28 | 2013-11-21 | Multiple feed selection circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104020809A (en) * | 2013-02-28 | 2014-09-03 | 东莞赛微微电子有限公司 | Selection circuit powered by multiple power sources |
| CN104935034A (en) * | 2015-05-21 | 2015-09-23 | 深圳天珑无线科技有限公司 | Switching pulse type charging device, switching pulse type charging method and terminal |
| CN114895612A (en) * | 2022-07-11 | 2022-08-12 | 深圳市杰美康机电有限公司 | Simulation system and simulation control method for DSP chip |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005116048A (en) * | 2003-10-07 | 2005-04-28 | Elpida Memory Inc | Anti-fuse programming circuit |
| CN101047166A (en) * | 2006-03-29 | 2007-10-03 | 富晶半导体股份有限公司 | Fuse memory bit with double voltage source and its power supplying method |
| JP2009152325A (en) * | 2007-12-19 | 2009-07-09 | Sharp Corp | Semiconductor apparatus |
| JP2011119018A (en) * | 2011-01-13 | 2011-06-16 | Renesas Electronics Corp | Semiconductor device |
| CN102623065A (en) * | 2012-01-12 | 2012-08-01 | 苏州华芯微电子股份有限公司 | Write-in and read-out circuit for OTP storage data |
| CN203673380U (en) * | 2013-02-28 | 2014-06-25 | 东莞赛微微电子有限公司 | Multi-power-source power supply selection circuit |
-
2013
- 2013-11-21 CN CN201320747341.6U patent/CN203673380U/en not_active Withdrawn - After Issue
- 2013-11-21 CN CN201310594751.6A patent/CN104020809B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104020809A (en) * | 2013-02-28 | 2014-09-03 | 东莞赛微微电子有限公司 | Selection circuit powered by multiple power sources |
| CN104020809B (en) * | 2013-02-28 | 2016-01-13 | 东莞赛微微电子有限公司 | Multiple feed selection circuit |
| CN104935034A (en) * | 2015-05-21 | 2015-09-23 | 深圳天珑无线科技有限公司 | Switching pulse type charging device, switching pulse type charging method and terminal |
| CN114895612A (en) * | 2022-07-11 | 2022-08-12 | 深圳市杰美康机电有限公司 | Simulation system and simulation control method for DSP chip |
| CN114895612B (en) * | 2022-07-11 | 2022-09-27 | 深圳市杰美康机电有限公司 | Simulation system for DSP chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104020809B (en) | 2016-01-13 |
| CN104020809A (en) | 2014-09-03 |
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20140625 Effective date of abandoning: 20160113 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |