CN109164863A

CN109164863A - SONOS grid end controls voltage generation circuit

Info

Publication number: CN109164863A
Application number: CN201810984642.8A
Authority: CN
Inventors: 赵艳丽
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-08-28
Filing date: 2018-08-28
Publication date: 2019-01-08
Anticipated expiration: 2038-08-28
Also published as: CN109164863B

Abstract

The invention discloses a kind of SONOS grid ends to control voltage generation circuit, and charge pump outputs export negative high voltage signal, and multiple resistance are connected in series between reference voltage terminal and negative high voltage VNEG signal, are divided；Multiple switch one end is corresponding in turn on the node for being connected to and being connected in series between resistance R (K+1) and R0, and the other end links together, as branch pressure voltage input terminal；The reverse input end of amplifier is grounded, and positive input is connected to resistance R (n) and R (K+1) series connection node, and output end is connected with charge pump；One PMOS transistor and two NMOS transistors are sequentially connected in series；The grid of first NMOS transistor inputs branch pressure voltage, and the connecting pin output SONOS grid end of the drain electrode of source electrode and the second NMOS transistor controls voltage signal VNEG_P, which is above the negative high voltage signal of VNEG.The present invention can effectively shorten SONOS grid end control voltage settling time.

Description

SONOS grid end controls voltage generation circuit

Technical field

The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of SONOS (Semiconductor- Oxide-Nitride-Oxide-Semiconductor flash memory) grid end control voltage generation circuit.

Background technique

NVM (nonvolatile memory) FLASH (flash memory) can have a kind of erasing to row is not operated in high pressure programming operation The interference of type, this interference phenomenon will affect the reliability of FLASH.

It needs to hold the WLS (grid end) of not selected line unit in high pressure programming operation for the reliability for promoting FLASH Current potential is increased to VNEG_P by VNEG (negative high voltage), which is above the negative high voltage of VNEG, to reduce not selected cell (cell) voltage difference of grid end and drain terminal, to mitigate interference.

Existing generation VNEG_P potential circuit (i.e. existing SONOS grid end controls voltage generation circuit), such as Fig. 1 institute Show, by multiple resistance, a PMOS transistor PM1, a NMOS transistor NM1, an operational amplifier YF, charge pump DHB composition. VREF is benchmark voltage, charge pump DHB output VNEG.

The multiple resistance R (n), R (K+1), R1, R0 are connected in series between VREF and VNEG R (K) ..., and R (n) is N-th of resistance, R (k) are k-th of resistance, and n and k are the integer more than or equal to zero, and k is less than n.

The normal phase input end of the operational amplifier YF is connected on the series connection node DIV of resistance R (n) and R (k+1).It should The reverse inter-input-ing ending grounding of operational amplifier YF, output end are connected with charge pump DHB.Charge pump DHB output as previously described VNEG。

The source electrode of PMOS transistor PM1 is grounded GND, and drain electrode is connected with the drain electrode of NMOS transistor NM1, and grid is defeated Enter SONOS grid end control voltage and generates signal CTRL1.

The one end of S1, S0 multiple switch S (K) ... are connected to the node being connected in series between resistance R (K+1) and R0 On, the other end is connected as branch pressure voltage VNEG_PP input terminal with the gate terminal of NMOS transistor NM1.In this way, in charge Between the VNEG and reference voltage VREF of pump DHB output by the way of electric resistance partial pressure tap, branch pressure voltage VNEG_PP is inputted To the gate terminal of NMOS transistor NM1.Branch pressure voltage VNEG_PP passes through Vt (grid end and the source threshold value of NMOS transistor NM1 Voltage) after, VNEG_P, the VNEG_P multi-gear adjustable are generated in the source terminal of NMOS transistor NM1.

Foregoing circuit has problems in that, when the load capacitance of VNEG_P signal is excessive, the settling time of VNEG_P Can be too long, and then the time of high pressure programming is eaten up, influence SONOS element characteristics.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of SONOS grid ends to control voltage generation circuit, can effectively contract The settling time of short SONOS grid end control voltage.

In order to solve the above technical problems, SONOS grid end of the invention controls voltage generation circuit, by an operational amplifier, One charge pump, a PMOS transistor, two NMOS transistors, multiple switch and multiple resistance composition；

The multiple switch is denoted as S (K) respectively ..., and S1, S0, the multiple resistance are denoted as R (n), R (K+1), R respectively (K) ... R1, R0, wherein R (n) is n-th of resistance, and R (K) is the K resistance, and S (K) is k-th of switch, n and k for greater than etc. In zero integer, and k is less than n；

The charge pump outputs export negative high voltage signal VNEG, the multiple resistance R (n), R (K+1), R (K) ... R1, R0 is connected in series between the end reference voltage VREF and negative high voltage signal VNEG, to reference voltage VREF and negative high voltage signal VNEG Between voltage divided；

The multiple switch S (K) ... S1, S0, one end, which is corresponding in turn to, is connected to the company of series connection between resistance R (K+1) and R0 On the node connect, the other end links together, as branch pressure voltage VNEG_PP input terminal；

The reverse input end of the operational amplifier is grounded, and positive input is connected to resistance R (n) and R (K+1) goes here and there Interlink point DIV, output end are connected with charge pump；

First PMOS transistor and the first NMOS transistor, the second NMOS transistor are sequentially connected in series, and the first PMOS is brilliant The source electrode of body pipe is grounded GND, and the source electrode of the second NMOS transistor is connected with the end negative high voltage signal VNEG；

The grid of the grid of first PMOS transistor and the second NMOS transistor inputs SONOS grid end control voltage and generates letter The grid of number CTRL, the first NMOS transistor input branch pressure voltage VNEG_PP, the source electrode of the first NMOS transistor and the 2nd NMOS The connecting pin of the drain electrode of transistor controls voltage signal VNEG_P as output end output SONOS grid end, which is above The negative high voltage signal of VNEG.

VNEG_P is followed by that charge pump establishes can be slow, and really need VNEG_P voltage when is that VNEG is established After good, so the present invention then allows VNEG_P=VNEG before VNEG is not established also, established to VNEG and then will VNEG_P is switched to another branch, generates the negative high voltage of the ratio VNEG high of needs.

When being able to solve excessive because of VNEG_P signal load capacitor using method of the invention, settling time is too long to be asked Topic, the SONOS grid end that effectively shortens controls the settling time of voltage, and then shortens high pressure programming time, reduces time cost.

Detailed description of the invention

Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

Fig. 1 is existing SONOS grid end control voltage generation circuit schematic diagram；

Fig. 2 is improved SONOS grid end control voltage generation circuit schematic diagram；

Fig. 3 is simulation result diagram.

Specific embodiment

As shown in connection with fig. 2, improved SONOS grid end control voltage generation circuit in the following embodiments, is transported by one Calculate amplifier YF, a charge pump DHB, a PMOS transistor PM1, two NMOS transistor NM1, NM2, multiple switch S (K) ... S1, S0, multiple resistance R (n), R (K+1), R (K) ... R1, R0 composition.Wherein, R (n) is n-th of resistance, and R (K) is k-th electricity Resistance, S (K) are k-th of switch, and n and k are the integer more than or equal to zero, and k is less than n.

The charge pump DHB output end exports negative high voltage VNEG voltage signal, the multiple resistance R (n), R (K+1), R (K) ... R1, R0 are connected in series between the end reference voltage VREF and charge pump DHB output end, to reference voltage VREF and negative height Voltage between pressure VNEG is divided.

The multiple switch S (K) ... S1, S0, one end are corresponding in turn to be connected between resistance R (K+1) and R0 and be connected in series Node on, the other end links together, as branch pressure voltage VNEG_PP input terminal.

The reverse input end of the operational amplifier YF is grounded, and positive input is connected to resistance R (n) and R (K+1) Series connection node DIV, output end are connected with charge pump DHB.

PMOS transistor PM1 and NMOS transistor NM1, NM2 are sequentially connected in series, the source electrode ground connection of PMOS transistor PM1 The source electrode of GND, NMOS transistor NM2 are connected with the end VNEG.

The grid of PMOS transistor PM1 and the grid input SONOS grid end control voltage of NMOS transistor NM2 generate signal The grid of CTRL, NMOS transistor NM1 input branch pressure voltage VNEG_PP, the source electrode and NMOS transistor of NMOS transistor NM1 The connecting pin of the drain electrode of NM2 controls voltage signal VNEG_P as output end output SONOS grid end.

CTRL signal=the PUMP&PE&PRG, wherein PUMP is that the characterization VNEG of operational amplifier YF output is established Signal exported after VNEG Voltage Establishment is good by operational amplifier YF, PE is the enable signal of charge pump DHB, and PRG is High pressure programming operation signal, " & " is indicated and operation.That is PUMP and PE, PRG signal co- controlling NMOS transistor NM2 And PMOS transistor PM1.

Before VNEG voltage is not set up, PUMP signal is " 0 ", and CTRL signal is " 1 ", and NMOS transistor NM2 is beaten It opens, PMOS transistor PM1 shutdown, VNEG_P=VNEG.

After VNEG Voltage Establishment is good, PUMP signal set, CTRL signal is VNEG current potential, NMOS transistor NM2 Shutdown, PMOS transistor PM1 are opened, and VNEG_P current potential is the Vt value that VNEG_PP subtracts a NMOS transistor NM1.

Fig. 3 is the result schematic diagram of emulation, in which: from top to bottom,

First column simulation result is ideal situation, and VNEG_P voltage is established with VNEG.

Second column simulation result is abnormal conditions, and VNEG_P settling time is too long, after VNEG is established also not just Often establish.

Third column simulation result is simulation result of the invention, before VNEG is established, PUMP signal reset, and VNEG_P After=VNEG, PUMP set, VNEG_P=VNEG_PP-Vt.VNEG_P is the negative high voltage of the ratio VNEG high needed.

Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims

1. a kind of SONOS grid end controls voltage generation circuit, it is characterised in that: by an operational amplifier, a charge pump, a PMOS Transistor, two NMOS transistors, multiple switch and multiple resistance composition；

The multiple switch is denoted as S (K) respectively ... S1, S0, the multiple resistance be denoted as respectively R (n), R (K+1), R (K) ... R1, R0, wherein R (n) is n-th of resistance, and R (K) is k-th resistance, and S (K) is k-th of switch, and n and k are whole more than or equal to zero Number, and k is less than n；

The charge pump outputs export negative high voltage signal VNEG, the multiple resistance R (n), R (K+1), R (K) ... R1, R0 string Connection is connected between the end reference voltage VREF and negative high voltage signal VNEG, between reference voltage VREF and negative high voltage signal VNEG Voltage divided；

The multiple switch S (K) ... S1, S0, one end are corresponding in turn to be connected to and be connected in series between resistance R (K+1) and R0 On node, the other end links together, as branch pressure voltage VNEG_PP input terminal；

The reverse input end of the operational amplifier is grounded, and positive input is connected to resistance R (n) and R (K+1) series connection node DIV, output end are connected with charge pump；

First PMOS transistor and the first NMOS transistor, the second NMOS transistor are sequentially connected in series, the first PMOS transistor Source electrode be grounded GND, the source electrode of the second NMOS transistor is connected with the end negative high voltage signal VNEG；

The grid of the grid of first PMOS transistor and the second NMOS transistor inputs SONOS grid end control voltage and generates signal CTRL, the grid of the first NMOS transistor input branch pressure voltage VNEG_PP, and the source electrode of the first NMOS transistor and the 2nd NMOS are brilliant The connecting pin of the drain electrode of body pipe controls voltage signal VNEG_P as output end output SONOS grid end, which is above The negative high voltage signal of VNEG.

2. circuit as described in claim 1, it is characterised in that: the CTRL signal=PUMP&PE&PRG, wherein PUMP is The characterization VNEG of operational amplifier output establishes signal, and PE is the enable signal of charge pump, and PRG is high pressure programming operation letter Number, " & " is indicated and operation.

3. circuit as claimed in claim 1 or 2, it is characterised in that: before VNEG voltage is not set up, characterization VNEG is established Good signal PUMP signal is " 0 ", and CTRL signal is " 1 ", and the second NMOS transistor is opened, the shutdown of the first PMOS transistor, VNEG_ P=VNEG.

4. circuit as claimed in claim 1 or 2, it is characterised in that: after VNEG Voltage Establishment is good, characterization VNEG is established Signal PUMP signal set, CTRL signal are VNEG current potential, and the second NMOS transistor turns off, and the first PMOS transistor is opened, VNEG_P current potential is the threshold voltage vt value that VNEG_PP subtracts first NMOS transistor.