CN105468075A - Feedback circuit of negative voltage charge pump - Google Patents
Feedback circuit of negative voltage charge pump Download PDFInfo
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- CN105468075A CN105468075A CN201510977066.0A CN201510977066A CN105468075A CN 105468075 A CN105468075 A CN 105468075A CN 201510977066 A CN201510977066 A CN 201510977066A CN 105468075 A CN105468075 A CN 105468075A
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- Prior art keywords
- charge pump
- circuit
- negative pressure
- reference voltage
- operational amplifier
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/562—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices with a threshold detection shunting the control path of the final control device
Abstract
The invention discloses a feedback circuit of a negative voltage charge pump. The circuit comprises a bleeder circuit which is formed by connecting a plurality of MOS transistors in series, the drain electrodes and the grid electrodes of the MOS transistors being in short circuit. The bleeder circuit is connected between the negative voltage output by the charge pump and first reference voltage, and outputs branch voltage as feedback voltage. The feedback voltage is connected with a first input end of a first operational amplifier. The second input end of the first operational amplifier is connected with ground. An amplification signal output by the first operational amplifier is used as a clock control signal. The clock signal inputs to the input end of the charge pump through a clock control circuit. The clock control signal inputs to the clock control circuit to adjust amplitude of the clock signal input to the charge pump, and values of the negative voltage are controlled through adjusting the amplitude of the clock signal. The circuit area is reduced.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of negative pressure charge pump feedback circuit.
Background technology
As shown in Figure 1, be the schematic diagram of existing negative pressure charge pump feedback circuit; Clock signal C lock is connected to and door 102 input end, the input end of negative pressure charge pump 101 is connected to the output terminal of door 102, the output terminal of negative pressure charge pump 101 exports negative pressure Vneg, feedback circuit be connected to negative pressure charge pump 101 output terminal and and another input end of door 102 between, feedback circuit comprises comparer 103, resistor voltage divider circuit 104 and positive-negative voltage conversion circuit 105.Resistor voltage divider circuit 104 in Fig. 1 is formed by multiple resistant series, can the annexation of regulating resistance thus the dividing ratios of controlling resistance bleeder circuit 104 to the control of switch by digital signal Dac.What export due to resistor voltage divider circuit 104 is the dividing potential drop of negative pressure Vneg, therefore also needs, by positive-negative voltage conversion circuit 105, dividing potential drop is converted to malleation.The positive partial pressure value that positive-negative voltage conversion circuit 105 exports and reference voltage V ref compare output feedack voltage and clock enable signal Clock_en, clock enable signal Clock_en controls clock signal C lock and whether is supplied to charge pump 101 circuit, thus regulates the output voltage Vneg of charge pump 101 to desired value.
Find out as shown in Figure 1, the resistor voltage divider circuit 104 in existing feedback circuit, by multiple resistant series, can take larger area.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of negative pressure charge pump feedback circuit, can reduction circuit area.
For solving the problems of the technologies described above, negative pressure charge pump feedback circuit provided by the invention comprises:
Bleeder circuit, connected by multiple MOS transistor and formed, the drain and gate of each described MOS transistor links together, between the negative pressure that described bleeder circuit is connected to charge pump output and the first reference voltage, described bleeder circuit exports the dividing potential drop of described negative pressure and described first reference voltage as feedback voltage.
First operational amplifier, described feedback voltage is connected to the first input end of described first operational amplifier, second input end grounding of described first operational amplifier, the output terminal of described first operational amplifier export described feedback voltage and earthy difference amplifying signal and using this amplifying signal as clock control signal.
Clock signal is input to the input end of described charge pump by clock control circuit, described clock control signal is input to described clock control circuit, described clock control signal regulates described clock signal to be input to the amplitude of described charge pump, is regulated the size of described negative pressure by the adjustment of the amplitude to described clock signal.
Further improvement is, described bleeder circuit is connected by multiple nmos pass transistor and formed.
Further improvement is, each described NMOS tube of described bleeder circuit measure-alike.
Further improvement is, described bleeder circuit is connected by multiple PMOS transistor and formed.
Further improvement is, each described PMOS of described bleeder circuit measure-alike.
Further improvement is, described bleeder circuit is connected by multiple PMOS transistor and multiple nmos pass transistor and formed.
Further improvement is, described first reference voltage is exported by reference voltage regulating circuit, is regulated the size of described first reference voltage by described reference voltage regulating circuit.
Further improvement is, described reference voltage regulating circuit comprises the second operational amplifier and resistance string; The output terminal of described second operational amplifier as described reference voltage regulating circuit output terminal and export described first reference voltage; Described resistance series winding is connected between described first reference voltage and ground; Described resistance string is in series by the first resistance and adjustable resistance; The first input end of described second operational amplifier connects the second reference voltage, second input end of described second operational amplifier is connected to the connected node of described first resistance and described adjustable resistance, by the size of the first reference voltage described in the size adjustment that regulates described adjustable resistance.
Further improvement is, described clock control circuit comprises the first phase inverter, the second phase inverter and the 3rd phase inverter.
The input end of described first phase inverter connects described clock signal, and the output terminal of described first phase inverter is connected to described charge pump, and the control end of described first phase inverter connects described clock control signal.
The input end of described second phase inverter connects described clock signal, the output terminal of described second phase inverter connects the input end of described 3rd phase inverter, the output terminal of described 3rd phase inverter connects described charge pump, and the control end of described 3rd phase inverter connects described clock control signal.
Further improvement is, the output terminal of described first operational amplifier is connected to the grid of the first NMOS tube, the source ground of described first NMOS tube, and the drain electrode of described first NMOS tube exports described clock control signal.
Further improvement is, between the output terminal that the first electric capacity is connected to described first operational amplifier and described negative pressure.
The present invention has following Advantageous Effects:
1, bleeder circuit of the present invention is in series by MOS transistor, and relative to the bleeder circuit structure that resistant series is formed, the present invention can reduce the area of bleeder circuit.
2, bleeder circuit of the present invention by regulating the ratio of size of MOS transistor and the quantity of MOS transistor just can obtain required dividing potential drop, in addition, the present invention does not need the control realizing clock signal to bleeder circuit adjustment, but the amplifying signal exported by operational amplifier realizes the control to clock signal to the adjustment of the amplitude of clock signal, and then the size adjustment realized the negative pressure exported, so the present invention controls relative to the size adjustment needed in existing feedback circuit by the resistance to bleeder circuit, bleeder circuit of the present invention can keep less electric current always, so the present invention can reduce the electric current of bleeder circuit, thus the current loading of charge pump can be reduced, and then the area of charge pump can be reduced.
3, the present invention can regulate the size of the first reference voltage by reference voltage regulating circuit, and the negative pressure exported really and being in proportion of the first reference voltage, so the present invention can carry out the size of the negative pressure of regulation output by the adjustment of the size to the first reference voltage, thus the present invention can realize export adjustable.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram of existing negative pressure charge pump feedback circuit;
Fig. 2 is the schematic diagram of embodiment of the present invention negative pressure charge pump feedback circuit.
Embodiment
As shown in Figure 2, be the schematic diagram of embodiment of the present invention negative pressure VNEG charge pump 202 feedback circuit, embodiment of the present invention negative pressure VNEG charge pump 202 feedback circuit comprises:
Bleeder circuit 201, connected by multiple MOS transistor and formed, the drain and gate of each described MOS transistor links together, between the negative pressure VNEG that described bleeder circuit 201 is connected to charge pump 202 output and the first reference voltage V refo, described bleeder circuit 201 exports the dividing potential drop of described negative pressure VNEG and described first reference voltage V refo as feedback voltage FDBK.
First operational amplifier 205, described feedback voltage FDBK is connected to the first input end of described first operational amplifier 205, second input end grounding of described first operational amplifier 205, the output terminal of described first operational amplifier 205 export described feedback voltage FDBK and earthy difference amplifying signal and using this amplifying signal as clock control signal.
Clock signal C lock is input to the input end of described charge pump 202 by clock control circuit 203, described clock control signal is input to described clock control circuit 203, described clock control signal regulates described clock signal C lock to be input to the amplitude of described charge pump 202, is regulated the size of described negative pressure VNEG by the adjustment of the amplitude to described clock signal C lock.
In the embodiment of the present invention, described bleeder circuit 201 is connected by multiple nmos pass transistor and is formed, each described NMOS tube of described bleeder circuit 201 measure-alike.In other embodiments, also can be that described bleeder circuit 201 is connected by multiple nmos pass transistor and formed, and the size of each described NMOS tube of described bleeder circuit 201 is not identical; Or described bleeder circuit 201 is connected by multiple PMOS transistor and is formed, each described PMOS of described bleeder circuit 201 measure-alike or; Described bleeder circuit 201 is formed by multiple PMOS transistor and multiple nmos pass transistor combined serial.
In embodiments of the present invention, described first reference voltage V refo is exported by reference voltage regulating circuit 204, is regulated the size of described first reference voltage V refo by described reference voltage regulating circuit 204.
Described reference voltage regulating circuit 204 comprises the second operational amplifier 206 and resistance string; The output terminal of described second operational amplifier 206 as described reference voltage regulating circuit 204 output terminal and export described first reference voltage V refo; Described resistance series winding is connected between described first reference voltage V refo and ground; Described resistance string is in series by the first resistance R1 and adjustable resistance Rd, and adjustable resistance Rd controls by control signal CTRL; The first input end of described second operational amplifier 206 connects the second reference voltage V ref, second input end of described second operational amplifier 206 is connected to the connected node of described first resistance R1 and described adjustable resistance Rd, by the size of the first reference voltage V refo described in the size adjustment that regulates described adjustable resistance Rd.
In embodiments of the present invention, described clock control circuit 203 comprises the first phase inverter 207a, the second phase inverter 207b and the 3rd phase inverter 207c.
The input end of described first phase inverter 207a connects described clock signal C lock, and the output terminal of described first phase inverter 207a is connected to described charge pump 202, and the control end of described first phase inverter 207a connects described clock control signal.
The input end of described second phase inverter 207b connects described clock signal C lock, the output terminal of described second phase inverter 207b connects the input end of described 3rd phase inverter 207c, the output terminal of described 3rd phase inverter 207c connects described charge pump 202, and the control end of described 3rd phase inverter 207c connects described clock control signal.
In the embodiment of the present invention, the output terminal of described first operational amplifier 205 is connected to the grid of the first NMOS tube MN1, the source ground of described first NMOS tube MN1, and the drain electrode of described first NMOS tube MN1 exports described clock control signal.Also namely described in the embodiment of the present invention, the first operational amplifier 205 does not directly export described clock control signal, but is exporting as described clock control signal after the output signal of described first operational amplifier 205 is amplified by described first NMOS tube MN1.
Between the output terminal that first electric capacity C1 is connected to described first operational amplifier 205 and described negative pressure VNEG.
Below in conjunction with formula, the embodiment of the present invention is described further:
The formula that described reference voltage regulating circuit 204 produces adjustable first reference voltage V refo is:
Vrefo＝Vref×(Rd+R1)/R1；
Wherein, R1 represents described first resistance, and Rd represents described adjustable resistance, and Vrefo represents the first reference voltage, and Vref represents the second reference voltage.When the location swap of the first resistance R1 and described adjustable resistance Rd described in Fig. 2, also can realize the adjustable of the first reference voltage V refo, the value of Rd and R1 at this moment in formula is exchanged.
The formula that described bleeder circuit 201 forms described feedback voltage FDBK is:
FDBK＝Vrefo*n/(n+1)+VNEG*1/(n+1)；
Wherein, FDBK represents feedback voltage, VNEG represents negative pressure, the number of wherein 1 nmos pass transistor represented in Fig. 2 between the first reference voltage V refo and feedback voltage FDBK is 1, n represents that the number of the nmos pass transistor in Fig. 2 between negative pressure VNEG and feedback voltage FDBK is n, and each nmos pass transistor is measure-alike.When the size of MOS transistor and type and number change, the formula of feedback voltage FDBK can do corresponding adjustment.As from the foregoing, in the embodiment of the present invention shown in Fig. 2, feedback voltage FDBK is only relevant with the number of nmos pass transistor.
In the embodiment of the present invention, feedback voltage FDBK, after described first operational amplifier 205 and described clock control circuit 203 realize the adjustment to described charge pump 202, can make feedback voltage FDBK=0; And the formula being updated to above-mentioned feedback voltage by 0 can obtain:
VNEG＝-Vrefo×n＝-vref×n*(Rd+R1)/R1。
It can thus be appreciated that, negative pressure VNEG only with the first reference voltage V refo of the embodiment of the present invention is relevant with the number of the MOS transistor of described bleeder circuit 201, do not need to adopt resistance string to carry out dividing potential drop, relative to resistance string, in SIC (semiconductor integrated circuit) manufacture field, the size of MOS transistor reduces greatly, so the embodiment of the present invention can reduce the area of bleeder circuit.
Simultaneously, the ratio of size by adjustment MOS transistor and the quantity of MOS transistor of embodiment of the present invention bleeder circuit 201 just can obtain required dividing potential drop, the present invention does not need to adjust to bleeder circuit 201 control realized clock signal C lock, but the amplifying signal exported by operational amplifier 205 realizes the control to clock signal C lock to the adjustment of the amplitude of clock signal C lock, and then the size adjustment realized the negative pressure VNEG exported, so the embodiment of the present invention controls relative to the size adjustment needed in existing feedback circuit by the resistance to bleeder circuit, the bleeder circuit 201 of the embodiment of the present invention can keep less electric current always, so the embodiment of the present invention can reduce the electric current of bleeder circuit 201, thus the current loading of charge pump can be reduced, and then the area of charge pump can be reduced.
Known, the embodiment of the present invention achieves the minimizing of the area of bleeder circuit 201 and charge pump 202 simultaneously, and whole circuit area obtains minimizing.
In addition, the embodiment of the present invention can regulate the size of the first reference voltage V refo by reference voltage regulating circuit 204, and the negative pressure VNEG exported and being in proportion of the first reference voltage V refo, so the embodiment of the present invention can regulate the size of negative pressure VNEG by the adjustment of the size to the first reference voltage V refo, thus the present invention can realize export adjustable.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (11)
1. a negative pressure charge pump feedback circuit, is characterized in that, comprising:
Bleeder circuit, connected by multiple MOS transistor and formed, the drain and gate of each described MOS transistor links together, between the negative pressure that described bleeder circuit is connected to charge pump output and the first reference voltage, described bleeder circuit exports the dividing potential drop of described negative pressure and described first reference voltage as feedback voltage;
First operational amplifier, described feedback voltage is connected to the first input end of described first operational amplifier, second input end grounding of described first operational amplifier, the output terminal of described first operational amplifier export described feedback voltage and earthy difference amplifying signal and using this amplifying signal as clock control signal;
Clock signal is input to the input end of described charge pump by clock control circuit, described clock control signal is input to described clock control circuit, described clock control signal regulates described clock signal to be input to the amplitude of described charge pump, is regulated the size of described negative pressure by the adjustment of the amplitude to described clock signal.
2. negative pressure charge pump feedback circuit as claimed in claim 1, is characterized in that: described bleeder circuit is connected by multiple nmos pass transistor and formed.
3. negative pressure charge pump feedback circuit as claimed in claim 2, is characterized in that: each described NMOS tube of described bleeder circuit measure-alike.
4. negative pressure charge pump feedback circuit as claimed in claim 1, is characterized in that: described bleeder circuit is connected by multiple PMOS transistor and formed.
5. negative pressure charge pump feedback circuit as claimed in claim 4, is characterized in that: each described PMOS of described bleeder circuit measure-alike.
6. negative pressure charge pump feedback circuit as claimed in claim 1, is characterized in that: described bleeder circuit is connected by multiple PMOS transistor and multiple nmos pass transistor and formed.
7. negative pressure charge pump feedback circuit as claimed in claim 1, is characterized in that: described first reference voltage is exported by reference voltage regulating circuit, is regulated the size of described first reference voltage by described reference voltage regulating circuit.
8. negative pressure charge pump feedback circuit as claimed in claim 7, is characterized in that: described reference voltage regulating circuit comprises the second operational amplifier and resistance string;
The output terminal of described second operational amplifier as described reference voltage regulating circuit output terminal and export described first reference voltage;
Described resistance series winding is connected between described first reference voltage and ground; Described resistance string is in series by the first resistance and adjustable resistance;
The first input end of described second operational amplifier connects the second reference voltage, second input end of described second operational amplifier is connected to the connected node of described first resistance and described adjustable resistance, by the size of the first reference voltage described in the size adjustment that regulates described adjustable resistance.
9. negative pressure charge pump feedback circuit as claimed in claim 1, is characterized in that: described clock control circuit comprises the first phase inverter, the second phase inverter and the 3rd phase inverter;
The input end of described first phase inverter connects described clock signal, and the output terminal of described first phase inverter is connected to described charge pump, and the control end of described first phase inverter connects described clock control signal;
The input end of described second phase inverter connects described clock signal, the output terminal of described second phase inverter connects the input end of described 3rd phase inverter, the output terminal of described 3rd phase inverter connects described charge pump, and the control end of described 3rd phase inverter connects described clock control signal.
10. the negative pressure charge pump feedback circuit as described in claim 1 or 9, it is characterized in that: the output terminal of described first operational amplifier is connected to the grid of the first NMOS tube, the source ground of described first NMOS tube, the drain electrode of described first NMOS tube exports described clock control signal.
11. negative pressure charge pump feedback circuits as claimed in claim 10, is characterized in that: between the output terminal that the first electric capacity is connected to described first operational amplifier and described negative pressure.
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| CN201510977066.0A CN105468075B (en) | 2015-12-22 | 2015-12-22 | Negative pressure charge pump feedback circuit |
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| CN201510977066.0A CN105468075B (en) | 2015-12-22 | 2015-12-22 | Negative pressure charge pump feedback circuit |
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| CN105468075B CN105468075B (en) | 2017-10-24 |
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Cited By (13)
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| CN105843316A (en) * | 2016-05-31 | 2016-08-10 | 上海华虹宏力半导体制造有限公司 | Charge pump reference voltage adjusting circuit |
| CN106774600A (en) * | 2016-12-23 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of low power consumption power supply circuit |
| CN107276396A (en) * | 2017-05-27 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN107453599A (en) * | 2017-07-17 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | The malleation charge pump of multivoltage output |
| CN107493012A (en) * | 2017-07-17 | 2017-12-19 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN109164866A (en) * | 2018-08-31 | 2019-01-08 | 南方科技大学 | Low pressure difference linear voltage regulator and power management chip based on negative charge pump enhancing |
| CN109164863A (en) * | 2018-08-28 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | SONOS grid end controls voltage generation circuit |
| CN109274261A (en) * | 2018-11-30 | 2019-01-25 | 中国电子科技集团公司第四十三研究所 | A kind of non-isolated negative pressure output control circuit and control method |
| CN109327133A (en) * | 2017-08-01 | 2019-02-12 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit |
| CN113315369A (en) * | 2021-07-09 | 2021-08-27 | 北京紫光青藤微系统有限公司 | Charge pump circuit |
| CN114362528A (en) * | 2021-12-31 | 2022-04-15 | 广州赛隆增材制造有限责任公司 | Suspension power supply |
| US11489443B2 (en) | 2020-03-12 | 2022-11-01 | Changxin Memory Technologies, Inc. | Charge pump circuit |
| CN115425844A (en) * | 2022-11-02 | 2022-12-02 | 无锡中感微电子股份有限公司 | Charge pump capable of modulating output voltage and battery protection circuit adopting same |
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| CN107276396B (en) * | 2017-05-27 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN107276396A (en) * | 2017-05-27 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN107453599B (en) * | 2017-07-17 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | Multi-voltage output positive-voltage charge pump |
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| CN107453599A (en) * | 2017-07-17 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | The malleation charge pump of multivoltage output |
| CN109327133A (en) * | 2017-08-01 | 2019-02-12 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit |
| CN109164863A (en) * | 2018-08-28 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | SONOS grid end controls voltage generation circuit |
| CN109164866A (en) * | 2018-08-31 | 2019-01-08 | 南方科技大学 | Low pressure difference linear voltage regulator and power management chip based on negative charge pump enhancing |
| CN109274261A (en) * | 2018-11-30 | 2019-01-25 | 中国电子科技集团公司第四十三研究所 | A kind of non-isolated negative pressure output control circuit and control method |
| US11489443B2 (en) | 2020-03-12 | 2022-11-01 | Changxin Memory Technologies, Inc. | Charge pump circuit |
| CN113315369A (en) * | 2021-07-09 | 2021-08-27 | 北京紫光青藤微系统有限公司 | Charge pump circuit |
| CN114362528A (en) * | 2021-12-31 | 2022-04-15 | 广州赛隆增材制造有限责任公司 | Suspension power supply |
| CN115425844A (en) * | 2022-11-02 | 2022-12-02 | 无锡中感微电子股份有限公司 | Charge pump capable of modulating output voltage and battery protection circuit adopting same |
| CN115425844B (en) * | 2022-11-02 | 2023-02-28 | 无锡中感微电子股份有限公司 | Charge pump capable of modulating output voltage and battery protection circuit adopting same |
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