CN107066024A - A kind of low power consumption high-precision non-bandgap reference voltage source - Google Patents
A kind of low power consumption high-precision non-bandgap reference voltage source Download PDFInfo
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- CN107066024A CN107066024A CN201710173120.5A CN201710173120A CN107066024A CN 107066024 A CN107066024 A CN 107066024A CN 201710173120 A CN201710173120 A CN 201710173120A CN 107066024 A CN107066024 A CN 107066024A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
A negative threshold value pipe threshold voltage is subtracted using a high threshold pipe threshold voltage the invention discloses one kind, a temperature independent low-power consumption, high accuracy, non-bandgap reference voltage source is realized.The reference voltage source is made up of three partial circuits：Start-up circuit, bias current generating circuit and reference voltage generating circuit.Start-up circuit provides startup voltage after it connects dc source for bias current generating circuit, voltage generation circuit provides necessary electric current on the basis of bias current generating circuit, reference voltage generating circuit is then made the difference by the threshold voltage of the threshold voltage and a negative threshold value pipe of a high threshold pipe, and after being corrected by reference voltage control code, produce a temperature independent reference voltage source.The completely compatible common CMOS process of the present invention, with precision is high, low in energy consumption, flexibility and reliability the characteristics of.
Description
Technical field
The present invention is used for IC design field, and in particular to a kind of low power consumption high-precision non-bandgap reference voltage source.
Background technology
In recent years, with various portable type electronic product broad developments and application, such as mobile phone, digital camera, mobile sound/regard
How frequency equipment etc., reduce one of the problem of power consumption, the use time of extension battery have turned into product design overriding concern.Cause
This, reference voltage source is as one of key modules in Analogous Integrated Electronic Circuits, to its low pressure, low-power consumption, accuracy and stability
Requirement more and more higher.
Band-gap reference is to be widely used in the industry because of its higher accuracy, and its operation principle is to utilize pn-junction forward voltage
With negative temperature coefficient, and the base-emitter voltage difference for two bipolar transistors being operated under different current densities has
Positive temperature coefficient, the two is mutually compensated for, and realizes the reference voltage of zero-temperature coefficient, and output voltage is general constant in 1.25V or so.
However, with the fast development of integrated circuit deep submicron process, requirement of many application systems to reference voltage value has been less than
1V, this not only needs to reduce output reference voltage value by increasing voltage conversion circuit to increase the design hardly possible of circuit
Degree, use of the bipolar transistor in CMOS technology can also bring the problems such as power consumption is higher, area is larger.
The content of the invention
The problem to be solved in the present invention is：For conventional bandgap voltage reference in deep-submicron CMOS process application
Present in above-mentioned drawback, it is proposed that a kind of low power consumption high-precision non-bandgap reference voltage source, the present invention is characterized in：
Described circuit structure includes start-up circuit, bias current generating circuit, reference voltage generating circuit.Start-up circuit, partially
Current generating circuit is put, reference voltage generating circuit meets supply voltage VDD respectively, and start-up circuit is used for circuit in power up
The circuit Deadlock being likely to occur, it exports the input of termination bias current generating circuit, and bias current generating circuit is used
In producing one not with the reference current of mains voltage variations, the output end of bias current generating circuit is proportional to be mirrored to benchmark
The input of voltage generation circuit, the output termination Vref of reference voltage generating circuit, reference voltage generating circuit is also by base
Quasi- voltage corrective control code A1、A2……AX, B1、B2……BXControl, for correction reference voltage Vref, specific annexation
It is as follows：
PMOS P1 grounded-grid, PMOS P1 source electrode meets power vd D, and PMOS P1 drain electrode connects PMOS P2 grid
Pole, while connecing the first electric capacity C1 anode, the first electric capacity C1 negativing ending grounding, PMOS P2 source class meets power vd D, PMOS
P2 drain electrode connects as the output end of start-up circuit with NMOS tube N1 grid with drain electrode, and with PMOS P3 drain electrode phase
Connect, NMOS tube N1 source ground, PMOS P3 source electrode meets power vd D, and PMOS P3 grid connects PMOS P4 grid
And drain electrode, and the output end connected with NMOS tube N2 drain electrode as bias current generating circuit, PMOS P4 source electrode connects electricity
Source VDD, NMOS tube N2 grid connects NMOS tube N1 grid, and NMOS tube N2 source electrode connects first resistor R1 anode, the first electricity
R1 negativing ending grounding is hindered, PMOS P5 grid connects the output end of bias current generating circuit, and PMOS P5 source electrode connects power supply
VDD, PMOS P5 drain electrode connect negative threshold value NMOS tube LA0, LA1, LA2 ... LAX grid, while being also coupled to high threshold NMOS
Pipe H0 drain and gate and high threshold NMOS tube HB0, HB1, HB2 ... HBX grid, negative threshold value NMOS tube LA0, LA1,
LA2 ... LAX source electrode connects and is connected to output port Vref, high threshold NMOS pipe HB0, HB1, HB2 ... HBX drain electrode
Connect and be connected to output port Vref, negative threshold value NMOS tube LA0 drain electrode meets power vd D, and high threshold NMOS tube HB0 source electrode connects
Ground, the drain electrode of high threshold NMOS tube LA1, LA2 ... LAX drain electrode successively with PMOS PA1, PA2 ... PAX connects, PMOS
Pipe PA1, PA2 ... PAX grid meet input port A successively1、A2……AX, PMOS PA1, PA2 ... PAX source electrode connects electricity
Drain electrode of source VDD, high threshold NMOS tube HB1, HB2 ... the HBX source electrode successively with NMOS tube NB1, NB2 ... NBX connects,
NMOS tube NB1, NB2 ... NBX grid connects input port B successively1、B2……BX, NMOS tube NB1, NB2 ... NBX source electrode
Ground connection.
The main characteristic of the invention lies in that：
1. it is simple in construction：The present invention is using CMOS technology and not comprising bipolar transistor, not using amplifier, it is not necessary to use benefit
Electric capacity is repaid, this not only greatly reduces chip area expense but also power consumption is controllable extremely low；
2. function admirable：The introducing of perfect Corrective control code, can flexibly have by the size of the bias current for controlling mirror image
The output of the correction reference voltage of effect, its performance fully achieves the performance of band-gap reference circuit under same technique；
It 3. is widely used：The present invention, which breaches band-gap reference circuit, can only export the constraint of the single reference voltages of 1.25V, a side
Reference voltage of the face less than 1V more meets the growth requirement of analogue layout, and the another aspect present invention can also be sacrificial
In the case of the certain precision of domestic animal, realize that VREF outputs are adjustable, use is more flexible.
Brief description of the drawings
A kind of Fig. 1 low power consumption high-precision non-bandgap reference voltage source circuit structured flowcharts proposed by the present invention；
A kind of Fig. 2 low power consumption high-precision non-bandgap reference voltage source circuit figures proposed by the present invention；
Fig. 3 reference voltages output VREF varies with temperature curve map.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
Its circuit structure block diagram of a kind of low power consumption high-precision non-bandgap reference voltage source proposed by the present invention as shown in figure 1, including
Start-up circuit, bias current generating circuit, reference voltage generating circuit.Start-up circuit, bias current generating circuit, reference voltage
Generation circuit meets supply voltage VDD respectively, and start-up circuit is used for the circuit Deadlock that circuit is likely to occur in power up,
It exports the input of termination bias current generating circuit, and bias current generating circuit is used for generation one and do not become with supply voltage
The reference current of change, the proportional input for being mirrored to reference voltage generating circuit of the output end of bias current generating circuit, its
The size of image current is by reference voltage Corrective control port A1, A2 ... AX, B1, B2 ... BX control, for correcting height
Threshold value pipe threshold voltage and negative threshold value pipe threshold voltage make the difference after temperature deviation, so as to produce a temperature independent benchmark
Voltage Vref.
Example is embodied as shown in Fig. 2 PMOS P1 grounded-grid, PMOS P1 source electrode meets power vd D, PMOS in it
P1 drain electrode connects PMOS P2 grid, while the first electric capacity C1 anode is connect, the first electric capacity C1 negativing ending grounding, PMOS P2
Source electrode meet power vd D, PMOS P2 drain electrode connects as the output end of start-up circuit with NMOS tube N1 grid with drain electrode,
And connect with PMOS P3 drain electrode, NMOS tube N1 source ground, PMOS P3 source electrode meets power vd D, PMOS P3's
Grid connects PMOS P4 grid and drain electrode, and the output connected with NMOS tube N2 drain electrode as bias current generating circuit
End, PMOS P4 source electrode meets power vd D, and NMOS tube N2 grid connects NMOS tube N1 grid, and NMOS tube N2 source electrode connects the
One resistance R1 anode, first resistor R1 negativing ending grounding, PMOS P5 grid connects the output end of bias current generating circuit,
PMOS P5 source electrode meets power vd D, and PMOS P5 drain electrode connects negative threshold value NMOS tube LA0, LA1, LA2 ... LAX grid,
High threshold NMOS tube H0 drain and gate and high threshold NMOS tube HB0, HB1, HB2 ... HBX grid are also coupled to simultaneously,
Negative threshold value NMOS tube LA0, LA1, LA2 ... LAX source electrode connect and are connected to output port Vref, high threshold NMOS tube HB0,
HB1, HB2 ... HBX drain electrode connect and are connected to output port Vref, and negative threshold value NMOS tube LA0 drain electrode meets power vd D, high
Threshold value NMOS tube HB0 source ground, high threshold NMOS tube LA1, LA2 ... LAX drain electrode successively with PMOS PA1,
PA2 ... PAX drain electrode connects, and PMOS PA1, PA2 ... PAX grid meets input port A1, A2 ... AX, PMOS successively
Pipe PA1, PA2 ... PAX source electrode meet power vd D, high threshold NMOS tube HB1, HB2 ... HBX source electrode successively with NMOS tube
NB1, NB2 ... NBX drain electrode connect, and NMOS tube NB1, NB2 ... NBX grid meets input port B 1, B2 ... BX successively,
NMOS tube NB1, NB2 ... NBX source ground.
Wherein, PMOS P1, P2 and the first electric capacity C1 composition start-up circuits.When power vd D is opened, due to PMOS P2's
Grid voltage is relatively low, and PMOS P2 can make it not enter " degeneracy " state to bias current generating circuit Injection Current.With
PMOS P1 constantly gives the first electric capacity C1 chargings, and PMOS P2 grid voltage gradually steps up most at last PMOS P2 closings, opened
Dynamic circuit end-of-job, circuit enters normal operating conditions.
PMOS P3, P4, NMOS tube N1, N2 and first resistor R1 constitute bias current generating circuit, produce one not with electricity
The reference current of source voltage change and it is proportional be mirrored to reference voltage generating circuit be used for correction reference voltage Vref.
The agent structure of reference voltage generating circuit is by PMOS P5, high threshold NMOS tube H0, HB0 and Low threshold NMOS tube
LA0 is constituted, and Vref is mainly produced by these pipes, control port A1、A2……AX, B1、B2……BXThe path at place is then led
If for correcting Vref outputs, the quantity of footmark " X " expression port here, can be according to actual electricity not to concrete values
Flexibly select, compromised between precision and expense the need for road.
The derivation of the present invention is described below：
First, four metal-oxide-semiconductors of reference voltage generating circuit agent structure are described, are PMOS P5, high threshold NMOS respectively
Pipe H0, HB0 and Low threshold NMOS tube LA0, it is assumed that VGSH0Represent high threshold NMOS tube H0 gate source voltage, VGSLA0Represent low threshold
It is worth NMOS tube LA0 gate source voltage, Vref represents that reference voltage is exported, VTHH0High threshold NMOS tube H0 threshold voltage is represented,
VTHLA0Represent negative threshold value NMOS tube LA0 threshold voltage, WH0/LH0Represent high threshold NMOS tube H0 breadth length ratio, WLA0/LLA0Table
Show negative threshold value NMOS tube LA0 breadth length ratio, in order that deriving more directly perceived, it is further assumed that the electric current I of bias current generating circuit
Represent, and equal proportion is mirrored to current path where PMOS P5, and electric current I equal proportions are mirrored to by high threshold NMOS tube H0
Path where high threshold NMOS tube HB0, expression is as follows：
VGSLA0=VGSH0-Vref (3)
It can be obtained by formula (1), (2), (3),
Because being hypothesized that electric current I equal proportions are mirrored to high threshold NMOS tube HB0 places path by high threshold NMOS tube H0 before,
Therefore, expression formula (4) is also denoted as,
Because high threshold NMOS tube threshold voltage VTHH0It is inversely proportional with temperature, negative threshold value NMOS tube threshold voltage VTHLA0Also with temperature
It is inversely proportional, but-VTHLA0It is directly proportional to temperature, the threshold voltage and the threshold voltage of negative threshold value NMOS tube of high threshold NMOS tube make the difference
There is the V of negative temperature coefficient equivalent to oneTHH0With-a V with positive temperature coefficientTHLA0Summation, is realized to a certain extent
The complementation of temperature coefficient, but in CMOS technology, hardly there is the V with equal temperature coefficientTHH0And VTHLA0, because
This, from expression formula (5) as can be seen that can be by adjusting electric current I temperatures coefficient and high threshold NMOS tube HB0 and negative threshold value
NMOS tube LA0 breadth length ratio adjusts VTHH0With VTHLA0Temperature deviation after making the difference, it is assumed that VTHH0-VTHLA0With negative temperature system
Number, then, bias current generating circuit can be made to produce an electric current being directly proportional to temperature, and appropriate adjustment high threshold NMOS
Pipe HB0 and negative threshold value NMOS tube LA0 breadth length ratio causeSo ensure thatV is offset with positive temperature coefficientTHH0-VTHLA0Negative temperature coefficient so that obtain one with
The unrelated Vref outputs of temperature；Even bias current generating circuit generates an electric current being inversely proportional with temperature, can also
Appropriate adjustment high threshold NMOS tube HB0 and negative threshold value NMOS tube LA0 breadth length ratio causesSo also may be used
To ensureV is offset with positive temperature coefficientTHH0-VTHLA0Negative temperature coefficient, can also obtain
To a temperature independent Vref outputs.
However, due to the deviation of technique, the influence of the factor such as mismatch of metal-oxide-semiconductor, actual chips can't be as model emulation so
Accurately, the size of image current, the size of metal-oxide-semiconductor can all have deviation, therefore, introduce Corrective control port A1、A2……
AX, B1、B2……BX, the introducing of these correction paths is actually in correctionSize.First, threshold is born
The channel length for being worth pipe LA0, LA1, LA2 ... LAX is equal, and high threshold pipe HB0, HB1, HB2 ... HBX channel length
Also it is equal, it is assumed that control code A1To be low, then, PMOS PA1 conductings, negative threshold value pipe LA1 equivalent to negative threshold value pipe LA0 simultaneously
Connection；Assuming that control code B1 is height, then, NMOS tube NB1 conductings, high threshold pipe HB1 is equivalent in parallel with high threshold pipe HB0；Such as
Fruit control port A1、A2……AXIt is low, while control port B1、B2……BXIt is height, then, expression formula (5) can be with table
It is shown as：
From expression formula (6) as can be seen that Corrective control port A1、A2……AX, B1、B2……BXIntroducing cause the circuit school
Positive way is very flexible, is on the one hand that control port quantity and opening ways can be selected flexibly, is on the other hand negative threshold value
Pipe LA0, LA1, LA2 ... LAX and high threshold pipe HB0, HB1, HB2 ... HBX raceway grooves are wide flexibly to set, purpose only has
One, obtain a temperature independent reference voltage V ref.Certainly, in the case where practical application allows, it can also pass through
Adjust these Corrective controls code and realize that Vref outputs are adjustable in the case where sacrificing certain precision.
Vref temperature characteristics that this embodiment is obtained under CMOS technology is as shown in figure 3, under normal temperature, reference voltage V ref
715.08mV is output as, within the temperature range of -40 DEG C~85 DEG C, voltage change is only 0.76mV, i.e. the temperature of output voltage
Coefficient is 8.5ppm/ DEG C.
Claims (4)
1. a kind of low power consumption high-precision non-bandgap reference voltage source, it is characterised in that：Including start-up circuit, bias current produces electricity
Road, reference voltage generating circuit；Start-up circuit, bias current generating circuit, reference voltage generating circuit connects supply voltage respectively
VDD, start-up circuit is used for the circuit Deadlock that circuit is likely to occur in power up, and it exports termination bias current and produced
The input of circuit, bias current generating circuit is used to produce one not with the reference current of mains voltage variations, bias current
The proportional input for being mirrored to reference voltage generating circuit of the output end of generation circuit, the output end of reference voltage generating circuit
Vref is met, reference voltage generating circuit is also by reference voltage Corrective control code A1、A2……AX, B1、B2……BXControl, use
In correction reference voltage Vref.
2. a kind of low power consumption high-precision non-bandgap reference voltage source according to claim 1, it is characterised in that：Described opens
Dynamic circuit is made up of PMOS P1, PMOS P2, the first electric capacity C1, and PMOS P1 grounded-grid, PMOS P1 source electrode connects
Power vd D, PMOS P1 drain electrode connect PMOS P2 grid, while connecing the first electric capacity C1 anode, the first electric capacity C1's is negative
End ground connection, PMOS P2 source electrode meets power vd D, PMOS P2 drain electrode as start-up circuit output end.
3. a kind of low power consumption high-precision non-bandgap reference voltage source according to claim 1, it is characterised in that：Described is inclined
Put current generating circuit to be made up of two PMOSs, two NMOS tubes and a resistance, NMOS tube N1 grid connects with drain electrode,
And connect with PMOS P3 drain electrode, while PMOS P2 drain electrode is also coupled to, NMOS tube N1 source ground, PMOS P3's
Source electrode meets power vd D, and PMOS P3 grid connects PMOS P4 grid and drain electrode, and the conduct that connects with NMOS tube N2 drain electrode
The output end of bias current generating circuit, PMOS P4 source electrode meets power vd D, and NMOS tube N2 grid connects NMOS tube N1 grid
Pole, NMOS tube N2 source electrode connects first resistor R1 anode, first resistor R1 negativing ending grounding.
4. a kind of low power consumption high-precision non-bandgap reference voltage source according to claim 1, it is characterised in that：Described base
Quasi- voltage generation circuit PMOS P5 grid connects the output end of bias current generating circuit, and PMOS P5 source electrode connects power supply
VDD, PMOS P5 drain electrode connect negative threshold value NMOS tube LA0, LA1, LA2 ... LAX grid, while being also coupled to high threshold NMOS
Pipe H0 drain and gate and high threshold NMOS tube HB0, HB1, HB2 ... HBX grid, negative threshold value NMOS tube LA0, LA1,
LA2 ... LAX source electrode connects and is connected to output port Vref, high threshold NMOS tube HB0, HB1, HB2 ... HBX drain electrode phase
Connect and be connected to output port Vref, negative threshold value NMOS tube LA0 drain electrode meets power vd D, and high threshold NMOS tube HB0 source electrode connects
Ground, the drain electrode of high threshold NMOS tube LA1, LA2 ... LAX drain electrode successively with PMOS PA1, PA2 ... PAX connects, PMOS
Pipe PA1, PA2 ... PAX grid meet input port A successively1、A2……AX, PMOS PA1, PA2 ... PAX source electrode connects electricity
Drain electrode of source VDD, high threshold NMOS tube HB1, HB2 ... the HBX source electrode successively with NMOS tube NB1, NB2 ... NBX connects,
NMOS tube NB1, NB2 ... NBX grid connects input port B successively1、B2……BX, NMOS tube NB1, NB2 ... NBX source electrode
Ground connection.
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| CN107943183A (en) * | 2017-12-06 | 2018-04-20 | 电子科技大学 | A kind of voltage reference circuit of super low-power consumption |
| CN107992145A (en) * | 2017-12-06 | 2018-05-04 | 电子科技大学 | A kind of voltage reference circuit with super low-power consumption characteristic |
| CN108469864A (en) * | 2018-03-30 | 2018-08-31 | 李启同 | A kind of low-temperature coefficient generating circuit from reference voltage and electronic device |
| CN116301166A (en) * | 2023-05-10 | 2023-06-23 | 深圳市安科讯电子制造有限公司 | Non-band gap reference voltage source circuit |
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