CN104102266A - Reference voltage generating circuit - Google Patents

Abstract

The invention discloses a reference voltage generating circuit and belongs to the technical field of integrated circuits. The reference voltage generating circuit comprises a presetting circuit converting input voltage to presetting voltage and a core circuit generating reference voltage under the action of the presetting voltage. The presetting circuit comprises a first depletion mode N-channel metal oxide semiconductor transistor and a second depletion mode N-channel metal oxide semiconductor transistor, and the core circuit comprises a third depletion mode N-channel metal oxide semiconductor transistor, a fourth depletion mode N-channel metal oxide semiconductor transistor, an enhanced N-channel metal oxide semiconductor transistor and a first resistor. The circuit is simplified, the layout area is reduced, output of the reference voltage with an arbitrary value is realized, and the reference voltage generating circuit has the advantages of low power consumption, low noise, low temperature coefficient and high PSRR (power supply rejection ratio).

Description

Reference voltage generating circuit

Technical field

The invention discloses reference voltage generating circuit, especially a kind of reference voltage generating circuit being comprised of depletion type MOS tube and enhancement mode metal-oxide-semiconductor, belongs to the technical field of integrated circuit.

Background technology

Reference voltage source, as important unit module circuit in IC design, is widely used in various Analogous Integrated Electronic Circuits, digital integrated circuit and hybrid digital-analog integrated circuit.Along with the development of integrated circuit technique, more and more higher to the requirement of reference voltage source now, require reference voltage source low in energy consumption, noise is low, temperature coefficient is low, PSRR is high, chip area is little etc.

Traditional reference voltage source generally adopts band-gap reference structure, utilizes the BE knot pressure drop V of the negative temperature coefficient of triode BJT _bEthe positive temperature coefficient (PTC) current flowing resistance producing with BJT thermal voltage VT produce the stack of positive temperature coefficient (PTC) voltage, generate the reference voltage of zero-temperature coefficient.Traditional band-gap reference structure comprises amplifier, triode BJT, resistance and building-out capacitor etc., and the components and parts of using are many, and chip area is large, and the electric current of consumption is large; And higher being not easy of the output noise of band-gap reference lowers; If obtain higher PSRR, the gain of amplifier used, bandwidth etc. are all had higher requirements, these factors have all limited the performance of band gap reference.

For these reasons, find a kind of simple in structure, excellent performance, the electric current simultaneously consuming again extremely low reference voltage generating circuit is necessary.

Summary of the invention

Technical matters to be solved by this invention is for the deficiency of above-mentioned background technology, and reference voltage generating circuit is provided.

The present invention adopts following technical scheme for achieving the above object:

Reference voltage generating circuit, comprise: the pre-adjusting circuit that is converted to preconditioning voltage by input voltage, under the effect of preconditioning voltage, produce the core circuit of reference voltage, described pre-adjusting circuit comprises: the first depletion type NMOS pipe, the second depletion type NMOS pipe, core circuit comprises: the 3rd depletion type NMOS pipe, the 4th depletion type NMOS pipe, enhancement mode NMOS pipe, the first resistance

Described first, the drain electrode of the second depletion type NMOS pipe all connects input voltage, first, the equal ground connection of substrate of the second depletion type NMOS pipe, the first depletion type MOS tube source electrode, the second depletion type NMOS tube grid is all connected with the 3rd depletion type NMOS pipe drain electrode, the second depletion type NMOS pipe source electrode, the first depletion type NMOS tube grid is all connected with the 4th depletion type NMOS pipe drain electrode, the grid of the 3rd depletion type NMOS pipe, source shorted, the 3rd depletion type NMOS tube grid is connected with the 4th depletion type NMOS tube grid, the drain electrode of enhancement mode NMOS pipe connects the 3rd depletion type NMOS pipe source electrode, enhancement mode NMOS manages source ground, enhancement mode NMOS tube grid, the 4th depletion type NMOS pipe source electrode first resistance one end is joined together to form reference voltage output point, the first resistance other end ground connection.

Further, reference voltage generating circuit also comprises the dividing potential drop branch road being connected between the described first resistance other end and the earth, chooses some dividing potential drop output points of dividing potential drop branch road as remaining reference voltage output point.

As the further prioritization scheme of described reference voltage generating circuit, the circuit elements device that dividing potential drop branch road is chosen has different temperatures coefficient, and dividing potential drop branch road is equivalent to the reference current generating circuit of zero-temperature coefficient.

As the further prioritization scheme of described reference voltage generating circuit, described dividing potential drop branch road is the second resistance, and second resistance one end is connected as another reference voltage output point with the first resistance other end, the second resistance other end ground connection.

As the further prioritization scheme of described reference voltage generating circuit, described the first resistance, the second resistance adopt Trimming design, by laser or burning aluminium, trim the first resistance with the size of the second resistance.

The present invention adopts technique scheme, has following beneficial effect: simplify circuit and reduced chip area, having realized the output of arbitrary value reference voltage, having advantages of low-power consumption, low noise, low-temperature coefficient, high PSRR.

Accompanying drawing explanation

Fig. 1 is the novel pipe reference voltage generating circuit schematic diagram that exhausts of the present invention.

Fig. 2 is that reference voltage generating circuit schematic diagram is managed in basic exhausting.

Fig. 3 is the improved pipe reference voltage generating circuit schematic diagram that exhausts.

Number in the figure explanation: DN11, DN22, DN33, DN44, DN1, DN2, DN3, DN4 are depletion type NMOS pipe, and MN1, MN3, MN4 are enhancement mode NMOS pipe, and R1, R2 are resistance.

Embodiment

Below in conjunction with accompanying drawing, the technical scheme of invention is elaborated.

Exhausting pipe reference voltage is to be obtained with the threshold voltage stack of depletion type NMOS by enhancement mode NMOS, by offsetting enhancement mode NMOS, follows depletion type NMOS V separately _tHnegative temperature coefficient, obtain the reference voltage of zero-temperature coefficient.Basic exhausts pipe reference voltage generating circuit as shown in Figure 2, the drain electrode of depletion type NMOS pipe DN0 connects VIN, the drain electrode that the grid source short circuit of depletion type NMOS pipe DN0 is connected to enhancement mode NMOS pipe MN0 connects with grid, the source ground of enhancement mode NMOS pipe MN0, the gate source voltage of enhancement mode NMOS pipe MN0 is reference voltage V _rEF:

$V_{\mathrm{REF}}=V_{\mathrm{TN}}-\sqrt{\frac{k_{\mathrm{DN}0}}{k_{\mathrm{MN}0}}}{V}_{\mathrm{TD}}---(1,)$

V in formula (1) _tNwith V _tDrepresent respectively the threshold voltage of enhancement mode NMOS pipe MN0 and depletion type NMOS pipe DN0, k _dN0=μ _nc _oX(W/L) _dN0, k _mN0=μ _nc _oX(W/L) _mN0, (W/L) _dN0, (W/L) _mN0for the breadth length ratio of DN0, MN0, the threshold value of depletion type NMOS is negative, and the threshold value V of depletion type NMOS pipe DN0 _tDthreshold value V with enhancement mode NMOS pipe MN0 _tNall be negative temperature coefficient, by choose reasonable MN0, follow the W/L of DN0, can obtain the reference voltage V of zero-temperature coefficient _rEF.

Circuit shown in Fig. 3 is that modified exhausts pipe reference voltage generating circuit, wherein the drain electrode of depletion type NMOS pipe DN33 meets VIN, its substrate ground connection, the grid of depletion type NMOS pipe DN33 connects the source electrode of depletion type NMOS pipe DN44, the source electrode of depletion type NMOS pipe DN33 connects the drain electrode of depletion type NMOS pipe DN3, the drain electrode of the grid source short circuit link enhancement type NMOS pipe MN3 of depletion type NMOS pipe DN3 is with grid, the source ground of enhancement mode NMOS pipe MN3, the gate source voltage of enhancement mode NMOS pipe MN3 is reference voltage V _rEF3; The drain electrode of depletion type NMOS pipe DN44 meets VIN, its substrate ground connection, the grid of depletion type NMOS pipe DN44 connects the source electrode of depletion type NMOS pipe DN33, the source electrode of depletion type NMOS pipe DN44 connects the drain electrode of depletion type NMOS pipe DN4, the drain electrode of the grid source short circuit link enhancement type NMOS pipe MN4 of depletion type NMOS pipe DN4 is with grid, the source ground of enhancement mode NMOS pipe MN4, the gate source voltage of enhancement mode NMOS pipe MN4 is reference voltage V _rEF4.

Modified exhausts pipe reference circuit has increased depletion type NMOS pipe DN33 on reference circuit with DN44 substantially exhausting pipe, and DN33 plays pre-adjustment effect with the introducing of DN44 to VIN voltage, can further improve reference voltage V _rEF3with V _rEF4pSRR performance and greatly reduce its line regulation.In circuit shown in Fig. 3 (W/L) _dN33=(W/L) _dN44, (W/L) _dN3=(W/L) _dN4, (W/L) _mN3=(W/L) _mN4,

$V_{\mathrm{REF}3}=V_{\mathrm{REF}4}=V_{\mathrm{TN}}-\sqrt{\frac{k_{\mathrm{DN}3}}{k_{\mathrm{MN}3}}}{V}_{\mathrm{TD}}=V_{\mathrm{TN}}-\sqrt{\frac{k_{\mathrm{DN}4}}{k_{\mathrm{MN}4}}}{V}_{\mathrm{TD}}---\left(2\right),$

In formula (2), V _tNwith V _tDrepresent respectively the threshold voltage of enhancement mode NMOS pipe MN4 (or MN3) and depletion type NMOS pipe DN4 (or DN3), k _dN3= _{μ n}c _oX(W/L) _dN3, k _mN3=μ _ncO _x(W/L) _mN3, k _dN4=μ _nc _oX(W/L) _dN4, k _mN4=μ _nc _oX(W/L) _mN4, (W/L) _dN3, (W/L) _mN3, (W/L) _dN4, (W/L) _mN4be respectively the breadth length ratio of DN3, MN3, DN4, MN4.

In view of the reference voltage generating circuit shown in Fig. 3 can only produce fixing reference voltage V _rEF3or V _rEF4, in low pressure applications, there is limitation, if DN4 grid in Fig. 3 is connected with the gate-source tie point of DN3, the grid of MN3 is connected to DN4 source electrode, MN4 is changed to resistance R 1 and can obtains the core circuit shown in Fig. 1.

Specific embodiment one

Reference voltage generating circuit as shown in Figure 1, comprising: by input voltage, be converted to the pre-adjusting circuit of preconditioning voltage, produce the core circuit of reference voltage under the effect of preconditioning voltage.Pre-adjusting circuit comprises: depletion type NMOS pipe DN11, depletion type NMOS pipe DN22.Core circuit comprises: depletion type NMOS pipe DN1, depletion type NMOS pipe DN2, enhancement mode NMOS pipe MN1, resistance R 1.Depletion type NMOS manages DN11, the drain electrode of DN22 all connects input voltage VIN, depletion type NMOS manages DN11, the equal ground connection of substrate of DN22, depletion type MOS tube DN11 source electrode, depletion type NMOS pipe DN22 grid is all connected (the A point in Fig. 1) with depletion type NMOS pipe DN1 drain electrode, depletion type NMOS pipe DN22 source electrode, depletion type NMOS pipe DN11 grid is all connected (the B point in Fig. 1) with depletion type NMOS pipe DN2 drain electrode, the grid of depletion type NMOS pipe DN1, source shorted (the C point in Fig. 1), depletion type NMOS pipe DN1 grid is connected with depletion type NMOS pipe DN2 grid, enhancement mode NMOS pipe MN1 drain electrode connects depletion type NMOS pipe DN1 source electrode, enhancement mode NMOS pipe MN1 source ground, enhancement mode NMOS pipe MN1 grid, depletion type NMOS pipe DN2 source resistance R1 one end is joined together to form reference voltage output point, this reference voltage output point output VREF1, resistance R 1 other end ground connection.

Depletion type NMOS pipe DN1 forms the basic pipe reference generating circuit that exhausts with enhancement mode NMOS pipe MN1,

$V_{\mathrm{REF}1}=V_{\mathrm{TN}}-\sqrt{\frac{k_{\mathrm{DN}1}}{k_{\mathrm{MN}1}}}{V}_{\mathrm{TD}}---\left(3\right),$

In formula (3), V _tNwith V _tDrepresent respectively the threshold voltage of enhancement mode NMOS pipe MN1 and depletion type NMOS pipe DN1.

The source electrode that the grid of enhancement mode NMOS pipe MN1 are connected to depletion type NMOS pipe DN2 is during with resistance R 1, V _rEF1value is still identical while following the grid of enhancement mode NMOS pipe MN1 to connect its drain electrode: if V _rEF1higher than enhancement mode NMOS manages the V of MN1 _gSincrease the gate voltage V of depletion type NMOS pipe DN1, DN2 _ccertainly will reduce V _creduction will make V _rEF1reduce; If V _rEF1lower than enhancement mode NMOS manages the V of MN1 _gSreduce the gate voltage V of depletion type NMOS pipe DN1, DN2 _cto raise, V _crising will make V _rEF1this circuit raises, so finally must be stabilized in in this example, core circuit improves by the reference circuit to traditional, has reduced the number of pipe, manages molecular close-loop feedback and is controlled under the not outside prerequisite regulating and has realized the stable output of reference voltage, has reduced loss and noise.

In addition, depletion type NMOS DN11, the DN22 shown in Fig. 1 forms pre-adjusting circuit, can further improve PSRR performance and the anti-linear performance of adjusting of reference voltage.

Specific embodiment two

On the basis of specific embodiment one, introduce dividing potential drop branch road, dividing potential drop branch road can be the resistance R 2 shown in Fig. 1, resistance R 1 composes in series bleeder circuit with resistance R 2, to V _rEF1carry out dividing potential drop, can obtain lower than V _rEF1any reference voltage value V of value _rEF2, V _rEF2=V _rEF1* R2/ (R1+R2).Dividing potential drop branch road can be selected numerous embodiments according to the demand of reference voltage, usings each dividing potential drop output point of bleeder circuit as the output point of any reference voltage.This example has realized the output of arbitrary value reference voltage.

Specific embodiment three

Fig. 2 is with the V of the reference voltage generating circuit shown in 3 _rEFvalue is a fixed value, and other slightly low arbitrary value reference voltages cannot be provided, and is difficult to carry out Trimming raising V _rEFprecision.If increase resistance Trimming function on resistance R 1 or R2 resistance, by laser or burning aluminium, trim resistance R 1 and follow the size of resistance R 2 can improve V _rEF2precision, eliminate the V that flow technological fluctuation causes _rEF1the deviation of value.

Specific embodiment four

If V in Fig. 1 _rEF1the resistance of lower series connection selects zero-temperature coefficient resistance (as adopted positive temperature coefficient (PTC) with the resistance stack of two types of negative temperature coefficients) can obtain the electric current of zero-temperature coefficient, and the present invention can easily realize the reference current of zero-temperature coefficient.

Above-described embodiment has only been enumerated the enforceable several examples of the present invention, but is not limitation of the present invention, and all the other meet the embodiment of inventive concept of the present invention or the replacement form that is equal to of the embodiment of the present invention all falls into protection scope of the present invention.

In sum, the present invention has the following advantages:

(1) pre-adjusting circuit, core circuit simplicity of design, reduced chip area;

(2) core circuit improves on existing reference circuit basis, not only reduced device count, and by the FEEDBACK CONTROL in closed loop, under the not outside prerequisite regulating, realized reference voltage and stablized output, low-power consumption, low noise, low-temperature coefficient, high PSRR;

(3) design of dividing potential drop branch road has realized the output of arbitrary value reference voltage.

Claims (5)

1. reference voltage generating circuit, comprise: the pre-adjusting circuit that is converted to preconditioning voltage by input voltage, under the effect of preconditioning voltage, produce the core circuit of reference voltage, it is characterized in that, described pre-adjusting circuit comprises: the first depletion type NMOS pipe (DN11), the second depletion type NMOS pipe (DN22), core circuit comprises: the 3rd depletion type NMOS pipe (DN1), the 4th depletion type NMOS pipe (DN2), enhancement mode NMOS manage (MN1), the first resistance (R1)

Described first, the second depletion type NMOS pipe (DN11, DN22) drain electrode all connects input voltage, first, the second depletion type NMOS pipe (DN11, DN22) the equal ground connection of substrate, the first depletion type MOS tube (DN11) source electrode, second depletion type NMOS pipe (DN22) grid is all connected with the 3rd depletion type NMOS pipe (DN1) drain electrode, second depletion type NMOS pipe (DN22) source electrode, first depletion type NMOS pipe (DN11) grid is all connected with the 4th depletion type NMOS pipe (DN2) drain electrode, the grid of the 3rd depletion type NMOS pipe (DN1), source shorted, the 3rd depletion type NMOS pipe (DN1) grid is managed (DN2) grid with the 4th depletion type NMOS and is connected, enhancement mode NMOS pipe (MN1) drain electrode connects the 3rd depletion type NMOS pipe (DN1) source electrode, enhancement mode NMOS manages (MN1) source ground, enhancement mode NMOS manages (MN1) grid, the 4th depletion type NMOS pipe (DN2) source electrode the first resistance (R1) one end is joined together to form reference voltage output point, the first resistance (R1) other end ground connection.

2. reference voltage generating circuit according to claim 1, characterized by further comprising the dividing potential drop branch road being connected between described the first resistance (R1) other end and the earth, chooses some dividing potential drop output points of dividing potential drop branch road as remaining reference voltage output point.

3. reference voltage generating circuit according to claim 2, is characterized in that, the circuit elements device that described dividing potential drop branch road is chosen has different temperatures coefficient, and dividing potential drop branch road is equivalent to the reference current generating circuit of zero-temperature coefficient.

4. according to the reference voltage generating circuit described in claim 2 or 3, it is characterized in that, described dividing potential drop branch road is the second resistance (R2), and the second resistance (R2) one end is connected as another reference voltage output point with the first resistance (R1) other end, the second resistance (R2) other end ground connection.

5. reference voltage generating circuit according to claim 4, is characterized in that, described the first resistance (R1), the second resistance (R2) adopt Trimming design, by laser or burning aluminium, trims the first resistance (R1) with the size of the second resistance (R2).