CN102176185B - Sub-threshold CMOS (complementary metal-oxide-semiconductor transistor) reference source - Google Patents

Abstract

The invention discloses a sub-threshold CMOS (complementary metal-oxide-semiconductor transistor) reference source, which comprises a starting circuit, a positive temperature coefficient circuit, a negative temperature coefficient circuit and an output circuit, and a body bias compensation circuit connected with the positive temperature coefficient circuit and the negative temperature coefficient circuit for producing a body bias voltage, the bias voltage is used for controlling the threshold voltage of the NMOS (N-channel metal oxide semiconductor) tube working in a sub-threshold value region in the positive temperature coefficient circuit and the negative temperature coefficient circuit so as to compensate the bias of an output reference voltage caused by the changes of the power voltage; and finally, a reference voltage with a temperature coefficient approximate to zero is produced in the output circuit. The output reference voltage value of the sub-threshold CMOS reference source nearly keeps the consistency when the power voltage is changed, and the power rejection ratio and the linearity are effectively improved without obviously adding the complexity of the circuit.

Description

Subthreshold value CMOS reference source

Technical field

The invention belongs to integrated circuit fields, be specifically related to a kind of subthreshold value CMOS reference source.

Background technology

Reference source is one of composition module the most basic in the analogy and digital circuit system.In design, require the indices of reference source lower to temperature and mains voltage variations susceptibility.Because traditional band gap reference can satisfy above-mentioned condition, so usually used by circuit designers.But band gap reference need to use large-area diode or parasitic triode, and its cut-in voltage generally about 0.6V, is not suitable for some low pressure applications occasion, and power consumption is relatively high, is difficult to satisfy the demand of portable electric appts.Therefore, subthreshold value CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) reference source is proposed and broad research by circuit designers.For example, G.Giustolisi, G.Palumbo, M.Criscione, and F.Cutr ì, " A low-voltage low-power voltage reference based on subthreshold MOSFETs; " IEEE J.Solid-State Circuits, vol.38, no.1, pp.151-154, Jan.2003.

In the prior art, subthreshold value CMOS reference source circuit figure as shown in Figure 1, it is comprised of start-up circuit 11, PTC circuit 12, negative temperature parameter circuit 13 and output circuit 14.

Start-up circuit 11 is by PMOS (P-Channel Metal Oxide Semiconductor, P-channel metal-oxide-semiconductor) pipe MP11, MP12 and NMOS (N-Channel Metal Oxide Semiconductor, the N NMOS N-channel MOS N) pipe MN11 forms, and the rear whole reference source that is used for guaranteeing to power on switches to duty.

PTC circuit 12 is by PMOS pipe MP13, MP14, and NMOS pipe MN12, MN13 and resistance R 11 form, and wherein MP13, MP14 consist of current-mirror structure, and MN12, MN13 are operated in sub-threshold region, and its transport property satisfies formula (1):

$I_D=I_{\mathrm{DO}}\mathrm{Sexp}\left(\frac{V_{\mathrm{GS}}-\left|V_{\mathrm{TH}}\right|}{n{V}_T}\right)---\left(1\right)$

V wherein _GSAnd V _THBe respectively gate source voltage and the threshold voltage of MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS) comprises: PMOS and NMOS) pipe, S=W/L is breadth length ratio, V _T=kT/q is thermal voltage, and n is slope factor, I _D0Be V _GS=V _TH, the leakage current during S=1.Can derive the positive temperature coefficient (PTC) electric current I according to formula (1) _PTAT(be the upper current flowing I of biasing resistor R11 _R11) be:

$I_{\mathrm{PTAT}}=I_{R11}=\frac{V_{\mathrm{GSN}12}-V_{\mathrm{GSN}13}}{{\mathrm{<figure-callout\; id="11"\; label="R"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_{11}}\&cong;n\frac{\mathrm{<figure-callout\; id="11"\; label="kT\; q\; R"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">kT</figure-callout>}}{q{R}_{}}\ln \left(\frac{S_{P13}{S}_{N13}}{S_{P14}{S}_{N12}}\right)---\left(2\right)$

Negative temperature parameter circuit 13 is by PMOS pipe MP15, MP16, and NMOS pipe MN14, MN15 and biasing resistor R12 form.Wherein MP15 and MP13, MP14 consist of one group of current mirror, and MP16, MP17 consist of another group current mirror, and MN14 is biased in sub-threshold region, and its transport property also satisfies formula (1), can derive negative temperature parameter current I thus _CTAT(be the upper electric current I of biasing resistor R12 _R12) be:

$I_{\mathrm{CTAT}}=\frac{V_{\mathrm{GSN}14}}{{\mathrm{<figure-callout\; id="12"\; label="R"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_{12}}=\frac{V_{\mathrm{THN}14}}{{\mathrm{<figure-callout\; id="12"\; label="R"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_{12}}+\mathrm{<figure-callout\; id="12"\; label="n\; kT\; qR"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">n</figure-callout>}\frac{\mathrm{kT}}{{\mathrm{qR}}_{}}\frac{{}_{12}}{}\ln \left(\frac{I_{\mathrm{DN}14}}{I_{D0}{S}_{N14}}\right)---\left(3\right)$

Because metal-oxide-semiconductor I when sub-threshold region _DBe generally less than I _D0S _N14So, negative temperature parameter current I _CTATBe inversely proportional to temperature.

Output circuit 14 is by PMOS pipe MP17, MP18, and resistance R 13 and capacitor C 11 form.The positive temperature coefficient (PTC) electric current I _PTATWith negative temperature parameter current I _CTATBe mirrored in the output circuit 14 by MP17 and MP18 respectively, the impact of the temperature of cancelling out each other, and by the final reference voltage V of resistance R 13 generations _REF, see formula (4):

$V_{\mathrm{REF}}=\frac{S_{P18}{R}_{13}}{S_{P14}}{I}_{\mathrm{PTAT}}+\frac{S_{P17}{R}_{13}}{S_{P16}}{I}_{\mathrm{CTAT}}=\mathrm{\&alpha;}{V}_T+\mathrm{\&beta;}[{\mathrm{<figure-callout\; id="14"\; label="V\; THN"\; filenames="HDA0000045017470000011.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{THN}}+n{V}_T\ln \left(\frac{I_{\mathrm{DN}14}}{I_{D0}{S}_{N14}}\right)]---\left(4\right)$

Wherein

By formula (4) as can be known, by ratio and the resistance ratio of reasonable adjustment metal-oxide-semiconductor breadth length ratio, can obtain one close to the reference voltage V of zero-temperature coefficient _REFCapacitor C 11 is used for filter away high frequency noise to reference voltage V _REFImpact.

Subthreshold value CMOS reference source circuit can reduce chip area and power consumption, and is applicable to the application scenario of low-voltage.But, because the restriction of low supply voltage, subthreshold value CMOS reference source generally adopts the single-stage metal-oxide-semiconductor to do current mirror (rather than traditional cascade structure), the output terminal of reference source is lower to the equivalent output resistance of power voltage terminal or ground end like this, the long mudulation effect of ditch is obvious, cause Power Supply Rejection Ratio and the linearity of subthreshold value CMOS reference source relatively poor, be difficult to be applicable to the circuit occasion of a lot of high precision high linearities.In fact, Power Supply Rejection Ratio and linearity problems have become one of Main Bottleneck of subthreshold value CMOS reference source.

Summary of the invention

The invention provides a kind of subthreshold value CMOS reference source based on the body bias compensation, affected by mains voltage variations with the reference voltage of the subthreshold value CMOS reference source output that overcomes prior art larger, Power Supply Rejection Ratio and the linearity are relatively poor, are difficult to be applicable to the deficiency of a lot of high precision high linearity circuit occasions.

A kind of subthreshold value CMOS reference source comprises start-up circuit, PTC circuit, negative temperature parameter circuit and output circuit;

Described start-up circuit is used for powering on the described subthreshold value CMOS reference source of rear startup;

Described PTC circuit and negative temperature parameter circuit are respectively applied to produce the electric current that is directly proportional with absolute temperature and the electric current that is inversely proportional to absolute temperature;

Simultaneously, the electric current of described PTC circuit and negative temperature parameter circuit converges in described output circuit, and the impact of the temperature of cancelling out each other, and produces a temperature coefficient and is approximately zero reference voltage;

Wherein, also be provided with the body bias compensating circuit, link to each other with negative temperature parameter circuit with described PTC circuit, for generation of bias voltage, control the threshold voltage of the NMOS pipe that is operated in the subthreshold value zone in described PTC circuit and the negative temperature parameter circuit, to compensate the deviation of the output reference voltage that causes owing to mains voltage variations.

In the above-mentioned subthreshold value CMOS reference source, described start-up circuit by a PMOS manage, the 2nd PMOS pipe and a NMOS pipe form, wherein, PMOS pipe and NMOS pipe form an inverter module, are used for the assurance rear whole reference source that powers on and switch to duty.

The source of described start-up circuit the one PMOS pipe links to each other with reference power source, the source of the one NMOS pipe links to each other with reference ground, the drain terminal of the one PMOS pipe links to each other with the drain terminal of a NMOS pipe, and the grid end of the grid end of a PMOS pipe and a NMOS pipe links to each other and accesses in the PTC circuit; The source of the 2nd PMOS pipe connects reference power source, and the drain terminal of grid termination the one PMOS pipe of the 2nd PMOS pipe and the drain terminal of a NMOS pipe are in the drain terminal access PTC circuit of the 2nd PMOS pipe;

In the above-mentioned subthreshold value CMOS reference source, described body bias compensating circuit comprises:

Two divider resistances, electric resistance partial pressure produces bias voltage, and the body end that described bias voltage exports the NMOS pipe that is operated in the subthreshold value zone in described PTC circuit and the negative temperature parameter circuit to carries out the control of threshold voltage parameter;

And operational amplifier, be the unity gain feedback arrangement, be used for the bias voltage buffering, strengthen the load capacity of body bias compensating circuit, avoid metal-oxide-semiconductor body electric current to the adverse effect of bias voltage.

In the described body bias compensating circuit, one termination reference power source of the first divider resistance, the other end of the first divider resistance links to each other with an end of the second divider resistance and the positive input terminal of operational amplifier, another termination of the second divider resistance is with reference to ground, self output terminal of the negative input end of operational amplifier and operational amplifier links to each other, simultaneously, in the output terminal of operational amplifier access PTC circuit and the negative temperature parameter circuit;

In the above-mentioned subthreshold value CMOS reference source, described PTC circuit comprises:

Two NMOS pipes (the 2nd NMOS pipe and the 3rd NMOS pipe) that are operated in the subthreshold value zone, bulk potential is all adjustable, for generation of positive temperature coefficient (PTC) voltage;

A biasing resistor (the first biasing resistor), between the grid end of described two the NMOS pipes that are operated in the subthreshold value zone, the positive temperature coefficient (PTC) voltage transitions that is used for producing becomes the positive temperature coefficient (PTC) electric current;

And current mirror, formed by two PMOS pipes (the 3rd PMOS pipe and the 4th PMOS pipe), be positioned at an end of described the first biasing resistor, for generation of image current.

In the described PTC circuit, the body end of the body end of the 2nd NMOS pipe and the 3rd NMOS pipe is independent from substrate, links to each other with the output terminal of operational amplifier in the body bias compensating circuit; The source of the source of the 2nd NMOS pipe and the 3rd NMOS pipe all connects with reference to ground; The grid end of the 2nd NMOS pipe connects respectively an end of the first biasing resistor and the drain terminal of the 3rd PMOS pipe; The drain terminal of the 2nd NMOS pipe links to each other with the drain terminal of the 2nd PMOS pipe in the grid end of the other end of the first biasing resistor, the 3rd NMOS pipe, the start-up circuit respectively, and the drain terminal of the 3rd NMOS pipe links to each other with the drain terminal of the 4th PMOS pipe; The drain terminal of the 4th PMOS pipe links to each other with the grid end of the 4th PMOS pipe, simultaneously, the grid end of the 4th PMOS pipe links to each other with the grid end of the 3rd PMOS pipe, and links to each other with the grid end, the grid end of a NMOS pipe of a PMOS pipe in the start-up circuit, also is linked into simultaneously in negative temperature parameter circuit and the output circuit; The source of the source of the 3rd PMOS pipe and the 4th PMOS pipe all connects reference power source;

In the above-mentioned subthreshold value CMOS reference source, described negative temperature parameter circuit comprises:

A NMOS pipe (the 4th NMOS pipe) that is operated in the subthreshold value zone, bulk potential is adjustable, for generation of negative temperature coefficient voltage;

A biasing resistor (the second biasing resistor), at the grid end of the described NMOS pipe that is operated in the subthreshold value zone with between with reference to ground, being used for the negative temperature coefficient voltage transitions is negative temperature parameter current;

A feedback NMOS pipe (the 5th NMOS pipe), its grid end links to each other with the described drain terminal that is operated in the NMOS pipe in subthreshold value zone, its source links to each other with the described grid end that is operated in the NMOS pipe in subthreshold value zone, be used to form negative feedback, stablize voltage and current on described the second biasing resistor by negative feedback;

With two current mirrors, the first current mirror is positioned at more than the drain terminal of the described NMOS pipe that is operated in the subthreshold value zone, for subthreshold value NMOS pipe provides image current, the second current mirror is positioned at more than the drain terminal of described feedback NMOS pipe, provides image current for feeding back NMOS pipe and biasing resistor.

In the described negative temperature parameter circuit, the body end of the 4th NMOS pipe is independent from substrate, links to each other with the output terminal of operational amplifier in the body bias compensating circuit; The source of the 4th NMOS pipe connects with reference to ground, and the drain terminal of the 4th NMOS pipe links to each other with the drain terminal of the 5th PMOS pipe, the grid end of the 5th NMOS pipe, and the grid end of the 4th NMOS pipe links to each other with the source of an end of the second biasing resistor, the 5th NMOS pipe; The other end of the second biasing resistor links to each other with reference ground; The drain terminal of the 5th NMOS pipe links to each other with the drain terminal of the 6th PMOS pipe; Self grid end of the drain terminal of the 6th PMOS pipe and the 6th PMOS pipe links to each other, and in the access output circuit, the source of the 6th PMOS pipe connects reference power source; The source of the 5th PMOS pipe connects reference power source, and the grid end of the 3rd PMOS pipe, the grid end of the 4th PMOS pipe link to each other in the grid end of the 5th PMOS pipe and the PTC circuit, and in the access output circuit;

In the above-mentioned subthreshold value CMOS reference source, described output circuit comprises:

Two PMOS pipes (the 7th PMOS pipe and the 8th PMOS pipe), be used for being connected with PTC circuit with described negative temperature parameter circuit respectively, negative temperature parameter current and positive temperature coefficient (PTC) current mirror converged in the output circuit and the impact of the temperature of cancelling out each other;

A biasing resistor (the 3rd biasing resistor) is approximately zero reference voltage for generation of final temperature coefficient;

And electric capacity, be used for filter away high frequency noise to the impact of reference voltage.

In the described output circuit, the source of the source of the 7th PMOS pipe and the 8th PMOS pipe all connects reference power source, the drain terminal of the drain terminal of the 7th PMOS pipe and the 8th PMOS pipe all connects the reference source output terminal, the grid end of the 6th PMOS pipe links to each other with drain terminal in the grid end of the 7th PMOS pipe and the negative temperature parameter circuit, in the grid end of the 8th PMOS pipe and the PTC circuit in the grid end of the grid end of the 3rd PMOS pipe, the 4th PMOS pipe and the negative temperature parameter circuit grid end of the 5th PMOS pipe link to each other; One end of the 3rd biasing resistor and an end of electric capacity all connect the reference source output terminal, and the other end of the 3rd biasing resistor and the other end of electric capacity all connect with reference to ground.

In the subthreshold value CMOS reference source of prior art, because the long mudulation effect of the ditch of metal-oxide-semiconductor in the practical application, the positive temperature coefficient (PTC) curent change is directly proportional with mains voltage variations, so the reference voltage of reference source output is directly proportional with mains voltage variations, this characteristic degradation Power Supply Rejection Ratio and the linearity of subthreshold value CMOS reference source.

In the subthreshold value CMOS reference source of the present invention, behind the introducing body bias compensating circuit, bias voltage (being electric resistance partial pressure) variation also is directly proportional with mains voltage variations; Bias voltage is delivered to the body end of the NMOS pipe that is operated in the subthreshold value zone in PTC circuit and the negative temperature parameter circuit, the threshold voltage variation and the bias voltage that are operated in the NMOS pipe in subthreshold value zone after the bulk potential modulation are varied to inverse ratio, namely are inversely proportional to mains voltage variations.Because being operated in the threshold voltage variation of the NMOS pipe in subthreshold value zone itself is directly proportional with the reference voltage of reference source output, so the body bias compensating circuit is operated in the threshold voltage of the NMOS pipe in subthreshold value zone by adjustment, can effectively compensate output reference voltage owing to the deviation that the long mudulation effect of ditch causes, improve Power Supply Rejection Ratio and the linearity of subthreshold value CMOS reference source.And, owing to the body end of the NMOS pipe that is operated in the subthreshold value zone in PTC circuit and the negative temperature parameter circuit is all independent from substrate, link to each other with the output terminal of body bias compensating circuit, like this, the threshold voltage that is operated in the NMOS pipe in subthreshold value zone in PTC circuit and the negative temperature parameter circuit is consistent, the working point of NMOS pipe that is operated in the subthreshold value zone when reference source is worked in PTC circuit and the negative temperature parameter circuit is similar, is conducive to like this to reduce circuit non-linear.In addition, the change position of the biasing resistor in the PTC circuit is placed between two NMOS tube grids that are operated in the subthreshold value zone, and the source bulk voltage of such two NMOS pipes that are operated in the subthreshold value zone is identical, and the bulk effect effect is consistent.

Further, can arrange on the second divider resistance in the described body bias compensating circuit on several sheets that can be shorted to separately ground and trim (on-chip trimming) input end, can trim to change by resistance on the sheet resistance value and the bias voltage of the second divider resistance when testing like this, thereby adjust the threshold voltage of the NMOS pipe that is operated in the subthreshold value zone.

Compared with prior art, the present invention has following useful technique effect:

By the bulk potential modulating action of body bias compensating circuit to the NMOS pipe that is operated in the subthreshold value zone in the reference source, final so that the output reference voltage value of subthreshold value CMOS reference source is consistent when mains voltage variations substantially, effectively improve Power Supply Rejection Ratio and the linearity of subthreshold value CMOS reference source in the situation of not obvious increase circuit complexity.

Description of drawings

Fig. 1 is the subthreshold value CMOS reference source circuit figure of prior art;

Fig. 2 is subthreshold value CMOS reference source circuit figure of the present invention;

Fig. 3 is Power Supply Rejection Ratio (the be not with filter capacitor) curve map of subthreshold value CMOS reference source under 27 ℃ of temperature and 1.2V supply voltage of subthreshold value CMOS reference source of the present invention and prior art;

Fig. 4 be the subthreshold value CMOS reference source of subthreshold value CMOS reference source of the present invention and prior art under 27 ℃ of temperature reference voltage and the graph of relation of supply voltage;

Fig. 5 is the reference voltage of subthreshold value CMOS reference source under the 1.2V supply voltage and the graph of relation of temperature of subthreshold value CMOS reference source of the present invention and prior art.

Embodiment

Describe the present invention in detail below in conjunction with embodiment and accompanying drawing, but the present invention is not limited to this.

A kind of subthreshold value CMOS reference source, its circuit diagram are comprised of start-up circuit 21, body bias compensating circuit 22, PTC circuit 23, negative temperature parameter circuit 24 and output circuit 25 as shown in Figure 2.

Start-up circuit 21 is comprised of PMOS pipe MP1, the 2nd PMOS pipe MP2 and NMOS pipe MN1.Wherein, the one PMOS pipe MP1 and NMOS pipe MN1 form a basic inverter module, the source of the one PMOS pipe MP1 links to each other with reference power source, the source of the one NMOS pipe MN1 links to each other with reference ground, the drain terminal of the one PMOS pipe MP1 links to each other with the drain terminal of NMOS pipe MN1, and the grid end of the grid end of PMOS pipe MP1 and NMOS pipe MN1 links to each other and accesses in the PTC circuit 23; The source of the 2nd PMOS pipe MP2 connects reference power source, and the drain terminal of grid termination the one PMOS pipe MP1 of the 2nd PMOS pipe MP2 and the drain terminal of NMOS pipe MN1 are in the drain terminal access PTC circuit 23 of the 2nd PMOS pipe MP2;

Body bias compensating circuit 22 is by two divider resistance R4, R5 and operational amplifier A 1 form, operational amplifier A 1 is the both-end input, Single-end output, wherein, the termination reference power source of the first divider resistance R4, the end of the other end of the first divider resistance R4 and the second divider resistance R5, and the positive input terminal of operational amplifier A 1 links to each other, another termination of the second divider resistance R5 is with reference to ground, self output terminal of the negative input end of operational amplifier A 1 and operational amplifier A 1 links to each other, form the unity gain feedback arrangement, simultaneously, in the output terminal of operational amplifier A 1 access PTC circuit 23 and the negative temperature parameter circuit 24;

PTC circuit 23 is managed MP4 by the 3rd PMOS pipe MP3, the 4th PMOS, and the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the first biasing resistor R1 form, and wherein the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 are operated in the subthreshold value zone; The body end of the body end of the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 is independent from substrate, links to each other with the output terminal of operational amplifier A 1 in the body bias compensating circuit 22; The source of the source of the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 all connects with reference to ground; The grid end of the 2nd NMOS pipe MN2 connects respectively the end of the first biasing resistor R1 and the drain terminal of the 3rd PMOS pipe MP3; The drain terminal of the 2nd NMOS pipe MN2 links to each other with the drain terminal of the 2nd PMOS pipe MP2 in the grid end of the other end of the first biasing resistor R1, the 3rd NMOS pipe MN3, the start-up circuit 21 respectively, and the drain terminal of the 3rd NMOS pipe MN3 links to each other with the drain terminal that the 4th PMOS manages MP4; The drain terminal of the 4th PMOS pipe MP4 links to each other with the grid end of the 4th PMOS pipe MP4, simultaneously, the grid end of the 4th PMOS pipe MP4 links to each other with the grid end of the 3rd PMOS pipe MP3, and link to each other with the grid end, the grid end of NMOS pipe MN1 of PMOS pipe MP1 in the start-up circuit 21, also be linked into simultaneously in negative temperature parameter circuit 24 and the output circuit 25; The source of the source of the 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 all connects reference power source;

Negative temperature parameter circuit 24 is managed MP6 by the 5th PMOS pipe MP5, the 6th PMOS, and the 4th NMOS pipe MN4, the 5th NMOS pipe MN5 and the second biasing resistor R2 form; Wherein, the 4th NMOS pipe MN4 is operated in the subthreshold value zone, and the output terminal of the operational amplifier A 1 in the body end of the 4th NMOS pipe MN4 and the body bias compensating circuit 22 links to each other; The source of the 4th NMOS pipe MN4 connects with reference to ground, the drain terminal of the 4th NMOS pipe MN4 links to each other with the grid end of the drain terminal of the 5th PMOS pipe MP5, the 5th NMOS pipe MN5, and the grid end of the 4th NMOS pipe MN4 links to each other with the source of the end of the second biasing resistor R2, the 5th NMOS pipe MN5; The other end of the second biasing resistor R2 links to each other with reference ground; The drain terminal of the 5th NMOS pipe MN5 links to each other with the drain terminal of the 6th PMOS pipe MP6; Self grid end of the drain terminal of the 6th PMOS pipe MP6 and the 6th PMOS pipe MP6 links to each other, and in the access output circuit 25, the source that the 6th PMOS manages MP6 connects reference power source; The source of the 5th PMOS pipe MP5 connects reference power source, and the grid end of the 3rd PMOS pipe MP3, the grid end of the 4th PMOS pipe MP4 link to each other, and access in the output circuit 25 in the grid end of the 5th PMOS pipe MP5 and the PTC circuit 23;

Output circuit 25 is managed MP8 by the 7th PMOS pipe MP7, the 8th PMOS, the 3rd biasing resistor R3 and capacitor C 1 form, wherein, the source of the source of the 7th PMOS pipe MP7 and the 8th PMOS pipe MP8 all connects reference power source, and the drain terminal of the drain terminal of the 7th PMOS pipe MP7 and the 8th PMOS pipe MP8 all meets reference source output terminal (V _REFEnd), the grid end of the 6th PMOS pipe MP6 links to each other with drain terminal in the grid end of the 7th PMOS pipe MP7 and the negative temperature parameter circuit 24, and the grid end that the 5th PMOS manages MP5 in the grid end of the grid end of the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4 and the negative temperature parameter circuit 24 in the grid end of the 8th PMOS pipe MP8 and the PTC circuit 23 links to each other; The end of the 3rd biasing resistor R3 and an end of capacitor C 1 all meet reference source output terminal (V _REFEnd), the other end of the other end of the 3rd biasing resistor R3 and capacitor C 1 all connects with reference to ground.

In the above-mentioned subthreshold value CMOS reference source, start-up circuit 21 is used for powering on the described subthreshold value CMOS reference source of rear startup; PTC circuit 23 and negative temperature parameter circuit 24 are respectively applied to produce the electric current that is directly proportional with absolute temperature and the electric current that is inversely proportional to absolute temperature; Simultaneously, the electric current of PTC circuit 23 and negative temperature parameter circuit 24 converges in output circuit 25, and the impact of the temperature of cancelling out each other, and produces a temperature coefficient and is approximately zero reference voltage; Body bias compensating circuit 22, link to each other with negative temperature parameter circuit 24 with PTC circuit 23, for generation of bias voltage, control the threshold voltage that is operated in the NMOS pipe in subthreshold value zone in PTC circuit 23 and the negative temperature parameter circuit 24, to compensate the deviation of the output reference voltage that causes owing to mains voltage variations.Specific as follows:

The start-up circuit 21 rear whole reference source that is used for guaranteeing to power on switches to duty, if circuit enters zero current condition, the one PMOS pipe MP1, the 2nd PMOS pipe MP2 and NMOS pipe MN1 all are in high level, the phase inverter that this moment, the one PMOS pipe MP1 and NMOS pipe MN1 formed is pulled down to low level by force with the drain terminal (i.e. the grid end of the 2nd PMOS pipe MP2) of PMOS pipe MP1, the 2nd PMOS manages the MP2 conducting and electric current is injected positive temperature coefficient (PTC) current generating circuit 23, and whole band gap reference is opened immediately.After the unlatching, the grid terminal potential of the 3rd PMOS pipe MP3 in the positive temperature coefficient (PTC) current generating circuit 23 descends, PMOS pipe MP1 conducting, and the 2nd PMOS pipe MP2 cut-off, start-up circuit 21 quits work.

Body bias compensating circuit 22 produces body bias current potential V by the electric resistance partial pressure of two divider resistances _BB, body bias current potential V _BBManage the body end of MN3 and the 4th NMOS pipe MN4 through entering the 2nd NMOS pipe MN2, the 3rd NMOS that are operated in the subthreshold value zone in PTC circuit 23 and the negative temperature parameter circuit 24 after the operational amplifier A 1, be used for the bulk potential modulation.And the operational amplifier A 1 of unity gain feedback arrangement can strengthen the load capacity of body bias compensating circuit 22, is used for the bias voltage buffering, avoids the body electric current of metal-oxide-semiconductor to bias voltage V _BBAdverse effect.

The threshold voltage V of metal-oxide-semiconductor _THWith body bias current potential V _BBRelations Among is as shown in the formula shown in (5):

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\&gamma;}(\sqrt{2\left|{\mathrm{\&phi;}}_F\right|-v_{\mathrm{BB}}}-\sqrt{2\left|{\mathrm{\&phi;}}_F\right|})---\left(5\right)$

V wherein _TH0V _SB=0 o'clock threshold voltage, γ are body-effect coefficient, φ _FIt is Fermi potential.

By formula (5) as can be known, by adjusting body bias current potential V _BBCan change the threshold voltage V of metal-oxide-semiconductor _TH, that is: can modulate to adjust the threshold voltage that the 2nd NMOS pipe MN2, the 3rd NMOS manage MN3 and the 4th NMOS pipe MN4 by bulk potential.

Further, can several sheets that can be shorted to separately ground be set at the second divider resistance R5 and trim (on-chip trimming) input end, can trim to change by resistance on the sheet resistance value and the bias voltage V of the second divider resistance R5 when testing like this _BBThereby, adjust the threshold voltage that the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the 4th NMOS manage MN4.

In the PTC circuit 23, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 are operated in the subthreshold value zone, and bulk potential is all adjustable, for generation of positive temperature coefficient (PTC) voltage; The first biasing resistor R1 is between the grid end of the second NMOS pipe MN2 and the 3rd NMOS pipe MN3, and the positive temperature coefficient (PTC) voltage transitions that is used for producing becomes the positive temperature coefficient (PTC) electric current I _PTAT(that is the electric current that, is directly proportional with absolute temperature); The 3rd PMOS pipe MP3 and the 4th PMOS pipe MP4 form current-mirror structure, are positioned at the end of the first biasing resistor R1, for generation of image current.The threshold voltage of the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 is modulated to adjust by bulk potential.

In the negative temperature parameter circuit 24, the 4th NMOS pipe MN4 is operated in the subthreshold value zone, and bulk potential is adjustable, for generation of negative temperature coefficient voltage; The second biasing resistor R2 at the grid end of the 4th NMOS pipe MN4 with reference to ground between, being used for the negative temperature coefficient voltage transitions is negative temperature parameter current I _CTAT(that is the electric current that, is inversely proportional to absolute temperature); The 5th NMOS pipe MN5 forms feedback loop with the 4th NMOS pipe MN4, stablizes voltage and current on the second biasing resistor R2 by negative feedback; The 5th PMOS pipe MP5 is used for the source-drain current on the 4th PMOS pipe MP4 is mirrored to the 4th NMOS pipe MN4; The 6th PMOS pipe MP6 then manages MN5 for the 5th NMOS and the second biasing resistor R2 provides image current.The threshold voltage of the 4th NMOS pipe MN4 is modulated to adjust by bulk potential.

Owing to being operated in the body end of the 4th NMOS pipe MN4 in subthreshold value zone in the negative temperature parameter circuit 24, body end with the 2nd NMOS pipe MN2 that is operated in the subthreshold value zone in the PTC circuit 23 and the 3rd NMOS pipe MN3, all the output terminal with operational amplifier A 1 links to each other, so the threshold voltage of the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the 4th NMOS pipe MN4 is consistent.The 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 is similar with the working point of the 4th NMOS pipe MN4 when reference source is worked, and is conducive to like this to reduce circuit non-linear.In addition, the change position of the first biasing resistor R1 is put between the 2nd NMOS pipe MN2 grid and the 3rd NMOS pipe MN3 grid, and such the 2nd NMOS pipe MN2 is identical with the 3rd NMOS pipe MN3 source bulk voltage, and the bulk effect effect is consistent.According to formula (4), the threshold voltage that changes the 4th NMOS pipe MN4 can change the reference voltage V of reference source output effectively _REFTherefore, body bias compensating circuit 22 produces bias voltage, can control the threshold voltage of the subthreshold value NMOS pipe in the reference source, thereby compensation is because the deviation of the output reference voltage that mains voltage variations causes.

Output circuit 25 is used for above-mentioned positive temperature coefficient (PTC) electric current I _PTATWith negative temperature parameter current I _CTATConverge and the impact of the temperature of cancelling out each other, finally produce a temperature coefficient and be approximately zero reference voltage.The 7th PMOS pipe MP7 is used for that negative temperature parameter current is mirrored to output circuit 25, the eight PMOS pipe MP8 and is used for the positive temperature coefficient (PTC) current mirror to output circuit 25; The 3rd biasing resistor R3 is used for converging negative temperature parameter current and positive temperature coefficient (PTC) electric current, and produces final reference voltage V _REF, and capacitor C 1 is used for filter away high frequency noise to reference voltage V _REFImpact.

In the subthreshold value CMOS reference source, Power Supply Rejection Ratio can through type (4) to supply voltage V _DDDifferentiate obtains:

$\frac{{\&PartialD;V}_{\mathrm{REF}}}{\&PartialD;V_{\mathrm{DD}}}=(\frac{S_{P8}{R}_3}{S_{P4}}+n\frac{{\mathrm{kTS}}_{P7}{R}_3}{{\mathrm{qS}}_{P6}{R}_2}\frac{I_{D0}{S}_{N4}}{I_{\mathrm{DN}4}})\frac{\&PartialD;I_{\mathrm{PTAT}}}{\&PartialD;V_{\mathrm{DD}}}+\frac{S_{P7}{R}_3}{S_{P6}{R}_2}\frac{\&PartialD;V_{\mathrm{THN}4}}{\&PartialD;V_{\mathrm{DD}}}---\left(6\right)$

Because the long mudulation effect of ditch of the 3rd PMOS pipe MP3 is as supply voltage V _DDDuring increase, the positive temperature coefficient (PTC) electric current I _PTATAlso increase, so

Introduced body bias compensating circuit 22, bias voltage V in the subthreshold value CMOS reference source of the present embodiment _BBWith supply voltage V _DDIncrease and increase, cause the threshold voltage of the 4th NMOS pipe MN4 to reduce, namely

Therefore, can utilize the positive temperature coefficient (PTC) electric current I _PTATMake with this opposite trend of threshold voltage of the 4th NMOS pipe MN4 Level off to zero, thereby improve the Power Supply Rejection Ratio of the subthreshold value CMOS reference source of the present embodiment.

Further, trim on the sheet by the second divider resistance R5 during test, can obtain the optimal value of Power Supply Rejection Ratio.

Under 0.13 μ m CMOS mixed signal technique, under 27 ℃ of temperature and 1.2V supply voltage, the Power Supply Rejection Ratio (not being with filter capacitor) of the subthreshold value CMOS reference source of the present embodiment and the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) contrasts as shown in Figure 3.As shown in Figure 3, the Power Supply Rejection Ratio of the subthreshold value CMOS reference source of the present embodiment under 0.2V bias voltage and 100Hz frequency is-51dB, as a comparison, the Power Supply Rejection Ratio of the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) is-26.5dB.This shows that the increase of body bias compensating circuit 22 can significantly improve the Power Supply Rejection Ratio of the subthreshold value CMOS reference source of the present embodiment.

The subthreshold value CMOS reference source of the present embodiment and the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) under 27 ℃ of temperature reference voltage and the contrast of the relation curve of supply voltage as shown in Figure 4.As shown in Figure 4, the subthreshold value CMOS reference source of the present embodiment (V in 1.1V to 2.2V supply voltage scope _DDDuring=1.2V, V _BB=0.1V) the linearity

Be 0.28%/V, and the linearity of the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) is 3%/V.This shows that the increase of body bias compensating circuit 22 can significantly improve the linearity of the subthreshold value CMOS reference source of the present embodiment.

In addition, the introducing of body bias compensating circuit 22 can't worsen the temperature coefficient of subthreshold value CMOS reference source When working temperature is T ₀The time, the 4th NMOS that is operated in sub-threshold region manages the gate source voltage V of MN4 _GSN4Be approximately with the relation of temperature:

$V_{\mathrm{GSN}4}\left(T\right)=V_{\mathrm{GSN}4}\left(T_0\right)+[V_{\mathrm{GSN}4}\left(T_0\right)-V_{\mathrm{THN}4}\left(T_0\right)+K_{\mathrm{TN}4}](\frac{T}{T_0}-1)$

$=V_{\mathrm{GSN}4}\left(T_0\right)+[n{V}_T\left(T_0\right)\ln \frac{I_D\left(T_0\right)}{I_{D0}{S}_{N4}}+K_{\mathrm{TN}4}](\frac{T}{T_0}-1)---\left(7\right)$

K wherein _TN4Be the 4th NMOS pipe MN4 threshold voltage V _THN4Temperature coefficient, with formula (7) substitution formula (4), and with formula (4) to the temperature differentiate, can obtain formula (8):

$\&PartialD;V_{\mathrm{REF}}/\&PartialD;T=\frac{S_{P9}{R}_3}{S_{P3}}\frac{\&PartialD;I_{\mathrm{PTAT}}}{\&PartialD;T}+\frac{S_{P8}{R}_3}{S_{P6}}\frac{\&PartialD;I_{\mathrm{CTAT}}}{\&PartialD;T}$

$=\frac{\mathrm{\&alpha;k}}{q}+\frac{\mathrm{\&beta;}}{T_0}[n{V}_T\left(T_0\right)\ln \frac{I_D\left(T_0\right)}{I_{D0}{S}_{N4}}+K_{\mathrm{TN}4}]---\left(8\right)$

At different bias voltage V _BBLower, the K in the formula (8) _TN4Remain unchanged.The drain terminal electric current I of the 4th NMOS pipe MN4 _D(T ₀) will change, but since the temperature coefficient of reference source only with I _D(T ₀) logarithmic form relevant, so I _D(T ₀) variation in the certain limit is very little on the impact of the temperature coefficient of reference source.Fig. 5 is the subthreshold value CMOS reference source of the present embodiment and the reference voltage of the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) under the 1.2V supply voltage and the graph of relation of temperature.As shown in Figure 5, as bias voltage V _BBWhen in-0.2V to 0.2V scope, changing, the temperature coefficient of the subthreshold value CMOS reference source of the present embodiment changes between 49ppm/ ℃ to 65ppm/ ℃, amplitude of variation is less, and the poorest 65ppm/ ℃ temperature coefficient also can be applicable to most of high-precision applications occasions.And the subthreshold value CMOS reference source of prior art (circuit diagram as shown in Figure 1) temperature coefficient is 58ppm/ ℃.

Claims (3)

1. a subthreshold value CMOS reference source comprises start-up circuit (21), PTC circuit (23), negative temperature parameter circuit (24) and output circuit (25), wherein,

Described start-up circuit (21) is used for powering on the described subthreshold value CMOS reference source of rear startup;

Described PTC circuit (23) and negative temperature parameter circuit (24) are respectively applied to produce the electric current that is directly proportional with absolute temperature and the electric current that is inversely proportional to absolute temperature;

Simultaneously, the electric current of described PTC circuit (23) and negative temperature parameter circuit (24) converges in described output circuit (25), and the impact of the temperature of cancelling out each other, and produces a temperature coefficient and is approximately zero reference voltage;

It is characterized in that:

Also be provided with body bias compensating circuit (22), link to each other with negative temperature parameter circuit (24) with described PTC circuit (23), for generation of bias voltage, control the threshold voltage that is operated in the NMOS pipe in subthreshold value zone in described PTC circuit (23) and the negative temperature parameter circuit (24), to compensate the deviation of the output reference voltage that causes owing to mains voltage variations;

Described body bias compensating circuit (22) comprising:

Two divider resistances, electric resistance partial pressure produces bias voltage, described bias voltage exports the body end that is operated in the NMOS pipe in subthreshold value zone in described PTC circuit (23) and the negative temperature parameter circuit (24) to, carries out the control of threshold voltage parameter;

And operational amplifier, be the unity gain feedback arrangement, be used for the bias voltage buffering.

2. subthreshold value CMOS reference source as claimed in claim 1 is characterized in that,

Described start-up circuit (21) is comprised of PMOS pipe (MP1), the 2nd PMOS pipe (MP2) and NMOS pipe (MN1), wherein, the source of the one PMOS pipe (MP1) links to each other with reference power source, the source of the one NMOS pipe (MN1) links to each other with reference ground, the drain terminal of the one PMOS pipe (MP1) links to each other with the drain terminal that a NMOS manage (MN1), and the grid end that the grid end that a PMOS manages (MP1) and a NMOS manage (MN1) links to each other and accesses in the PTC circuit (23); The source of the 2nd PMOS pipe (MP2) connects reference power source, and the drain terminal of grid termination the one PMOS pipe (MP1) of the 2nd PMOS pipe (MP2) and the drain terminal of NMOS pipe (MN1) are in the drain terminal access PTC circuit (23) of the 2nd PMOS pipe (MP2);

Described body bias compensating circuit (22) is by two divider resistance (R4, R5) and operational amplifier (A1) form, wherein, one termination reference power source of the first divider resistance (R4), one end of the other end of the first divider resistance (R4) and the second divider resistance (R5), and the positive input terminal of operational amplifier (A1) links to each other, another termination of the second divider resistance (R5) is with reference to ground, self output terminal of the negative input end of operational amplifier (A1) and operational amplifier (A1) links to each other, simultaneously, in the output terminal of operational amplifier (A1) access PTC circuit (23) and the negative temperature parameter circuit (24);

Described PTC circuit (23) is managed (MP4) by the 3rd PMOS pipe (MP3), the 4th PMOS, the 2nd NMOS pipe (MN2), the 3rd NMOS pipe (MN3) and the first biasing resistor (R1) form, and wherein the 2nd NMOS pipe (MN2) and the 3rd NMOS pipe (MN3) is operated in the subthreshold value zone; The body end of the body end of the 2nd NMOS pipe (MN2) and the 3rd NMOS pipe (MN3) is independent from substrate, links to each other with the output terminal of operational amplifier (A1) in the body bias compensating circuit (22); The source of the source of the 2nd NMOS pipe (MN2) and the 3rd NMOS pipe (MN3) all connects with reference to ground; The grid end of the 2nd NMOS pipe (MN2) connects respectively an end of the first biasing resistor (R1) and the drain terminal of the 3rd PMOS pipe (MP3); The drain terminal of the 2nd NMOS pipe (MN2) links to each other with the drain terminal of the 2nd PMOS pipe (MP2) in the grid end of the other end of the first biasing resistor (R1), the 3rd NMOS pipe (MN3), the start-up circuit (21) respectively, and the drain terminal that the 3rd NMOS manages (MN3) links to each other with the drain terminal that the 4th PMOS manages (MP4); The drain terminal of the 4th PMOS pipe (MP4) links to each other with the grid end that the 4th PMOS manages (MP4), simultaneously, the grid end of the 4th PMOS pipe (MP4) links to each other with the grid end that the 3rd PMOS manages (MP3), and link to each other with the grid end, the grid end of NMOS pipe (MN1) of PMOS pipe (MP1) in the start-up circuit (21), also be linked into simultaneously in negative temperature parameter circuit (24) and the output circuit (25); The source of the source of the 3rd PMOS pipe (MP3) and the 4th PMOS pipe (MP4) all connects reference power source;

Described negative temperature parameter circuit (24) is managed (MP6) by the 5th PMOS pipe (MP5), the 6th PMOS, and the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5) and the second biasing resistor (R2) form; Wherein, the 4th NMOS pipe (MN4) is operated in the subthreshold value zone, and the output terminal of the operational amplifier (A1) in the body end of the 4th NMOS pipe (MN4) and the body bias compensating circuit (22) links to each other; The source of the 4th NMOS pipe (MN4) connects with reference to ground, the drain terminal of the 4th NMOS pipe (MN4) is managed the drain terminal of (MP5) with the 5th PMOS, the grid end of the 5th NMOS pipe (MN5) links to each other, and the grid end of the 4th NMOS pipe (MN4) links to each other with the source of an end of the second biasing resistor (R2), the 5th NMOS pipe (MN5); The other end of the second biasing resistor (R2) links to each other with reference ground; The drain terminal of the 5th NMOS pipe (MN5) links to each other with the drain terminal that the 6th PMOS manages (MP6); Self grid end that the drain terminal of the 6th PMOS pipe (MP6) and the 6th PMOS manages (MP6) links to each other, and accesses in the output circuit (25), and the source that the 6th PMOS manages (MP6) connects reference power source; The source of the 5th PMOS pipe (MP5) connects reference power source, and the grid end of the 3rd PMOS pipe (MP3), the grid end of the 4th PMOS pipe (MP4) link to each other, and access in the output circuit (25) in the grid end of the 5th PMOS pipe (MP5) and the PTC circuit (23);

Described output circuit (25) is by the 7th PMOS pipe (MP7), the 8th PMOS manages (MP8), the 3rd biasing resistor (R3) and electric capacity (C1) form, wherein, the source of the source of the 7th PMOS pipe (MP7) and the 8th PMOS pipe (MP8) all connects reference power source, the drain terminal of the drain terminal of the 7th PMOS pipe (MP7) and the 8th PMOS pipe (MP8) all connects the reference source output terminal, the grid end of the 6th PMOS pipe (MP6) links to each other with drain terminal in the grid end of the 7th PMOS pipe (MP7) and the negative temperature parameter circuit (24), and the 8th PMOS manages the grid end that the 3rd PMOS in the grid end of (MP8) and the PTC circuit (23) manages (MP3), the grid end of the 5th PMOS pipe (MP5) links to each other in the grid end of the 4th PMOS pipe (MP4) and the negative temperature parameter circuit (24); One end of one end of the 3rd biasing resistor (R3) and electric capacity (C1) all connects the reference source output terminal, and the other end of the other end of the 3rd biasing resistor (R3) and electric capacity (C1) all connects with reference to ground.

3. subthreshold value CMOS reference source as claimed in claim 2 is characterized in that, is provided with on described the second divider resistance (R5) on several sheets that can be shorted to separately ground and trims input end.

Images