CN114625200B - Operational amplifier and band gap reference source circuit - Google Patents
Operational amplifier and band gap reference source circuit Download PDFInfo
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- CN114625200B CN114625200B CN202210145361.XA CN202210145361A CN114625200B CN 114625200 B CN114625200 B CN 114625200B CN 202210145361 A CN202210145361 A CN 202210145361A CN 114625200 B CN114625200 B CN 114625200B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses an operational amplifier which is a circuit structure with three-end input and two-end output and is provided with a negative input end, a positive temperature coefficient current positive input end, a negative temperature coefficient current positive input end, a positive temperature coefficient operational amplifier output end and a negative temperature coefficient operational amplifier output end. The invention discloses a band gap reference source circuit adopting the operational amplifier, which can provide zero temperature coefficient voltage with any value and can save area.
Description
Technical Field
The present invention relates to semiconductor circuit technology, and more particularly, to an operational amplifier and a bandgap reference source circuit.
Background
As shown in FIG. 1 and FIG. 2, the reference voltage generated by the circuit structure of FIG. 1 isThe reference voltage generated by the circuit structure of FIG. 2 is +.>The ratio of R2 to R1 is adjusted, so that a reference voltage with any value can be generated; wherein DeltaV in the circuit structure of FIG. 1 and the structure of FIG. 2 be ＝V T * ln (N) is positive temperature coefficient, V T The thermoelectric potential is that N is the proportionality constant of the triodes Q1 and Q0, usually 8 or 24 are taken, matching is better carried out when the layout is realized, V be The voltage difference between the base and the emitter of the triode Q0 is a negative temperature coefficient.
The zero temperature coefficient reference voltage generated by the circuit structure of fig. 1 is about 1.25V, so that a positive temperature coefficient voltage and a positive temperature coefficient current can be generated, and in practical application, low power supply voltage may be involved, for example, the power supply voltage is less than 1.3V, the circuit structure cannot meet the requirement, and meanwhile, the circuit structure can only generate a positive temperature coefficient current and cannot meet the application requirement of the zero temperature coefficient current; the zero temperature coefficient reference voltage generated by the circuit structure of fig. 2 can be any value (realized by adjusting the ratio of R2 to R1), and can generate a current without a temperature coefficient, but the structure cannot generate a voltage with a positive temperature coefficient, for example, in some applications, the voltage with the positive temperature coefficient is required to detect the temperature, the structure cannot meet the requirement, and meanwhile, a plurality of voltage stabilizing working points exist in the structure, so that the design of a starting circuit is more challenging.
Disclosure of Invention
The invention aims to provide an operational amplifier which is a three-terminal input and two-terminal output circuit structure.
In order to solve the technical problems, the invention provides an operational amplifier, which comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5 and a sixth NMOS tube MN6;
the source ends of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected with a working voltage source VCC;
the source ends of the first NMOS tube MN1, the second NMOS tube MN2 and the third NMOS tube MN3 are grounded GND;
the source ends of the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are grounded GND;
the drain end of the first PMOS tube MP1 is connected with the drain end of the sixth NMOS tube MN6 and is used as a positive temperature coefficient operational amplifier output end VOUT_P;
the gate end of the first PMOS tube MP1 is connected with the gate end, the drain end and the drain end of the second PMOS tube MP2 and the first NMOS tube MN 1;
the drain end of the first NMOS tube MN1 is used as a positive temperature coefficient current positive input end INP_P;
the drain end of the fourth PMOS tube MP4 is connected with the drain end of the fourth NMOS tube MN4 and is used as a negative temperature coefficient operational amplifier output end VOUT_N;
the gate end of the fourth PMOS tube MP4 is connected with the gate end, the drain end and the drain end of the third NMOS tube MN3 of the third PMOS tube MP 3;
the drain end of the third NMOS tube MN3 is used as a negative temperature coefficient current positive input end INP_N;
the drain end of the sixth PMOS tube MP6 is connected with the drain end of the fifth NMOS tube MN5, and the gate ends of the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6;
the gate end of the sixth PMOS tube MP6 is connected with the gate end, the drain end and the drain end of the fifth PMOS tube MP5 and the second NMOS tube MN 2;
the drain of the second NMOS transistor MN2 is used as a negative input terminal INN.
Preferably, the operational amplifier further comprises a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8;
the drain end and the gate end of the seventh NMOS tube MN7 are in short circuit with the gate end of the eighth NMOS tube MN8 and are used for connecting bias current IBIAS;
the source end of the seventh NMOS tube MN7 and the source end of the eighth NMOS tube MN8 are grounded to GND;
the source ends of the first NMOS tube MN1, the second NMOS tube MN2 and the third NMOS tube MN3 are connected with the drain end of the eighth NMOS tube MN8, and are grounded GND through the eighth NMOS tube MN 8.
In order to solve the above technical problems, another operational amplifier provided by the present invention includes a first PMOS transistor MP1, a second PMOS transistor MP2, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16;
the source ends of the eleventh NMOS tube MN11, the twelfth NMOS tube MN12, the thirteenth NMOS tube MN13, the fourteenth NMOS tube MN14, the fifteenth NMOS tube MN15 and the sixteenth NMOS tube MN16 are grounded to GND;
the source ends of the first PMOS tube MP1, the second PMOS tube MP2 and the seventh PMOS tube MP7 are connected with a working voltage source VCC;
the drain end of the first PMOS tube MP1 is connected with the drain end of the fifteenth NMOS tube MN15 and is used as a positive temperature coefficient operational amplifier output end VOUT_P;
the drain end of the seventh PMOS tube MP7 is connected with the drain end of the sixteenth NMOS tube MN16 and is used as a negative temperature coefficient operational amplifier output end VOUT_N;
the gate end and the drain end of the second PMOS tube MP2, the gate end of the first PMOS tube MP1 and the gate end of the seventh PMOS tube MP7 are connected with the drain end of the fourteenth NMOS tube MN 14;
the source end of the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 is connected with bias current IBIAS;
the drain end of the eighth PMOS tube MP8 is connected with the drain end, the gate end and the gate end of the thirteenth NMOS tube MN13 and the fifteenth NMOS tube MN 15;
the gate end of the eighth PMOS tube MP8 is used as a positive temperature coefficient current positive input end INP_P;
the drain end of the ninth PMOS tube MP9 is connected with the drain end, the gate end and the gate end of the eleventh NMOS tube MN11 and the sixteenth NMOS tube MN16;
the gate end of the ninth PMOS tube MP9 is used as a negative temperature coefficient current positive input end INP_N;
the drain end of the tenth PMOS tube MP10 is connected with the drain end, the gate end and the gate end of the twelfth NMOS tube MN12 and the fourteenth NMOS tube MN 14;
the gate terminal of the tenth PMOS transistor MP10 is used as the negative input terminal INN.
The invention also provides a band-gap reference source circuit comprising the operational amplifier, which further comprises a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a reference voltage generating circuit;
the positive temperature coefficient current generating circuit comprises an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a first PNP triode Q1, a zeroth PNP triode Q0 and a zeroth resistor R0;
the negative temperature coefficient current generating circuit comprises a thirteenth PMOS tube MP13 and a first resistor R1;
the reference voltage generating circuit comprises a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15 and a second resistor R2;
the source end of the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 is connected with the working power supply positive;
gate ends of the eleventh PMOS tube MP11, the twelfth PMOS tube MP12 and the fourteenth PMOS tube MP14 are connected with the positive temperature coefficient operational amplifier output end VOUT_P;
the gate ends of the thirteenth PMOS tube MP13 and the fifteenth PMOS tube MP15 are connected with the negative temperature coefficient operational amplifier output end VOUT_N of the operational amplifier;
the drain end of the eleventh PMOS tube MP11 is connected with the positive temperature coefficient current positive input end INP_P of the operational amplifier;
the drain end of the twelfth PMOS tube MP12 is connected with the negative input end INN of the operational amplifier;
the emitter of the first PNP triode Q1 is connected with a positive temperature coefficient current positive input end INP_P of the operational amplifier through a zeroth resistor R0;
the emitter of the zeroth PNP triode Q0 is connected with the negative input end INN of the operational amplifier;
the bases of the first PNP triode Q1 and the zeroth PNP triode Q0 are short-circuited, and the collectors are grounded;
the drain end of the thirteenth PMOS tube MP13 is connected with the negative temperature coefficient current positive input end INP_N of the operational amplifier;
the first resistor R1 is connected in series between the drain end of the thirteenth PMOS tube MP13 and the ground;
the drain terminals of the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 are grounded through the second resistor R2 after being short-circuited, and the short-circuited terminal is used as an output terminal of zero temperature coefficient reference voltage VREF.
Preferably, the second resistor R2 is formed by connecting a plurality of resistors in series;
the serial connection point of the resistors is used for outputting zero temperature coefficient reference voltages VREF1 and VREF2 with different magnitudes.
Preferably, the reference voltage generating circuit further includes a sixteenth PMOS transistor MP16 and a third resistor R3;
the source end of the sixteenth PMOS tube MP16 is connected with the positive of the working power supply, the gate end is connected with the positive temperature coefficient operational amplifier output end VOUT_P, and the drain end is grounded through the third resistor R3 and used as the positive temperature coefficient voltage VPTC output end.
Preferably, the reference voltage generating circuit further includes a seventeenth PMOS transistor MP17 and a fifth resistor R5;
the seventeenth PMOS tube MP17 has its gate connected to the negative temperature coefficient operational amplifier output end VOUT_N, its source connected to the positive of the working power supply, and its drain connected to ground via the fifth resistor R5 and used as the negative temperature coefficient voltage VNTC output end.
Preferably, the bandgap reference source circuit further comprises a reference current generating circuit;
the reference current generation circuit comprises an eighteenth PMOS tube MP18 and a nineteenth PMOS tube MP19;
the source ends of the eighteenth PMOS tube MP18 and the nineteenth PMOS tube MP19 are connected with the working power supply positive;
the gate end of the eighteenth PMOS tube MP18 is connected with the positive temperature coefficient operational amplifier output end VOUT_P;
the gate end of the nineteenth PMOS tube MP19 is connected with the negative temperature coefficient operational amplifier output end VOUT_N;
drain ends of the eighteenth PMOS tube MP18 and the nineteenth PMOS tube MP19 are connected with zero temperature coefficient current IREF ZTC output ends.
Preferably, the reference current generating circuit further comprises a twentieth PMOS transistor MP20;
the twenty-first PMOS tube MP20 has its source connected to the positive of the working power supply, its gate connected to the positive temperature coefficient operational amplifier output terminal VOUT_P, and its drain connected to the positive temperature coefficient current IREFTTC output terminal.
Preferably, the reference current generating circuit further includes a second PMOS transistor MP21;
the source end of the second PMOS tube MP21 is connected with the positive of the working power supply, the gate end is connected with the output end VOUT_N of the negative temperature coefficient operational amplifier, and the drain end is connected with the output end of the negative temperature coefficient current IREFNTC.
The operational amplifier is a circuit structure with three-end input and two-end output, and is provided with a negative input end INN, a positive temperature coefficient current positive input end INP_P, a negative temperature coefficient current positive input end VOUT_P, a positive temperature coefficient operational amplifier output end VOUT_P and a negative temperature coefficient operational amplifier output end VOUT_N.
The band gap reference source circuit of the invention can provide zero temperature coefficient (ZTC: zero temperature coefficient) voltage, positive temperature coefficient (PTC: positive temperature coefficient) voltage and negative temperature coefficient (NTC: negative temperature coefficient) voltage with arbitrary values by adopting the operational amplifier with a new circuit structure and simultaneously matching the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit, the reference voltage generating circuit and the reference current generating circuit on the basis of the theory of the existing band gap reference circuit, and can generate positive temperature coefficient current, negative temperature coefficient current and zero temperature coefficient current at the same time, thereby saving the area.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following brief description of the drawings is given for the purpose of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without the need for inventive work for a person skilled in the art.
FIG. 1 is a prior art bandgap reference source circuit;
FIG. 2 is a prior art bandgap reference source circuit;
FIG. 3 is an operational amplifier of the present invention;
FIG. 4 is another operational amplifier of the present invention;
FIG. 5 is a circuit diagram of an embodiment of a bandgap reference source circuit of the present invention;
FIG. 6 is a simulation result of an output voltage of an embodiment of a bandgap reference circuit of the present invention;
FIG. 7 is a simulation result of the output current of an embodiment of the bandgap reference circuit of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 3, the operational amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6;
the source ends of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected with a working voltage source VCC;
the source ends of the first NMOS tube MN1, the second NMOS tube MN2 and the third NMOS tube MN3 are grounded GND;
the source ends of the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are grounded GND;
the drain end of the first PMOS tube MP1 is connected with the drain end of the sixth NMOS tube MN6 and is used as a positive temperature coefficient operational amplifier output end VOUT_P;
the gate end of the first PMOS tube MP1 is connected with the gate end, the drain end and the drain end of the second PMOS tube MP2 and the first NMOS tube MN 1;
the drain end of the first NMOS tube MN1 is used as a positive temperature coefficient current positive input end INP_P;
the drain end of the fourth PMOS tube MP4 is connected with the drain end of the fourth NMOS tube MN4 and is used as a negative temperature coefficient operational amplifier output end VOUT_N;
the gate end of the fourth PMOS tube MP4 is connected with the gate end, the drain end and the drain end of the third NMOS tube MN3 of the third PMOS tube MP 3;
the drain end of the third NMOS tube MN3 is used as a negative temperature coefficient current positive input end INP_N;
the drain end of the sixth PMOS tube MP6 is connected with the drain end of the fifth NMOS tube MN5, and the gate ends of the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6;
the gate end of the sixth PMOS tube MP6 is connected with the gate end, the drain end and the drain end of the fifth PMOS tube MP5 and the second NMOS tube MN 2;
the drain of the second NMOS transistor MN2 is used as a negative input terminal INN.
Preferably, the operational amplifier further comprises a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8;
the drain end and the gate end of the seventh NMOS tube MN7 are in short circuit with the gate end of the eighth NMOS tube MN8 and are used for connecting bias current IBIAS;
the source end of the seventh NMOS tube MN7 and the source end of the eighth NMOS tube MN8 are grounded to GND;
the source ends of the first NMOS tube MN1, the second NMOS tube MN2 and the third NMOS tube MN3 are connected with the drain end of the eighth NMOS tube MN8, and are grounded GND through the eighth NMOS tube MN 8.
The operational amplifier of the first embodiment is a circuit structure with three input ends and two output ends, and has a negative input end INN, a positive temperature coefficient current positive input end inp_p, a negative temperature coefficient current positive input end vout_p, a positive temperature coefficient operational amplifier output end vout_p and a negative temperature coefficient operational amplifier output end vout_n.
Example two
As shown in fig. 4, the operational amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16;
the source ends of the eleventh NMOS tube MN11, the twelfth NMOS tube MN12, the thirteenth NMOS tube MN13, the fourteenth NMOS tube MN14, the fifteenth NMOS tube MN15 and the sixteenth NMOS tube MN16 are grounded to GND;
the source ends of the first PMOS tube MP1, the second PMOS tube MP2 and the seventh PMOS tube MP7 are connected with a working voltage source VCC;
the drain end of the first PMOS tube MP1 is connected with the drain end of the fifteenth NMOS tube MN15 and is used as a positive temperature coefficient operational amplifier output end VOUT_P;
the drain end of the seventh PMOS tube MP7 is connected with the drain end of the sixteenth NMOS tube MN16 and is used as a negative temperature coefficient operational amplifier output end VOUT_N;
the gate end and the drain end of the second PMOS tube MP2, the gate end of the first PMOS tube MP1 and the gate end of the seventh PMOS tube MP7 are connected with the drain end of the fourteenth NMOS tube MN 14;
the source end of the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 is connected with bias current IBIAS;
the drain end of the eighth PMOS tube MP8 is connected with the drain end, the gate end and the gate end of the thirteenth NMOS tube MN13 and the fifteenth NMOS tube MN 15;
the gate end of the eighth PMOS tube MP8 is used as a positive temperature coefficient current positive input end INP_P;
the drain end of the ninth PMOS tube MP9 is connected with the drain end, the gate end and the gate end of the eleventh NMOS tube MN11 and the sixteenth NMOS tube MN16;
the gate end of the ninth PMOS tube MP9 is used as a negative temperature coefficient current positive input end INP_N;
the drain end of the tenth PMOS tube MP10 is connected with the drain end, the gate end and the gate end of the twelfth NMOS tube MN12 and the fourteenth NMOS tube MN 14;
the gate terminal of the tenth PMOS transistor MP10 is used as the negative input terminal INN.
The operational amplifier of the second embodiment is a circuit structure with three input terminals and two output terminals, and has a negative input terminal INN, a positive temperature coefficient current positive input terminal inp_p, a negative temperature coefficient current positive input terminal vout_p, a positive temperature coefficient operational amplifier output terminal vout_p, and a negative temperature coefficient operational amplifier output terminal vout_n.
Example III
As shown in fig. 5, a bandgap reference source circuit including an operational amplifier of the first or second embodiment further includes a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit, and a reference voltage generating circuit;
the positive temperature coefficient current generating circuit comprises an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a first PNP triode Q1, a zeroth PNP triode Q0 and a zeroth resistor R0;
the negative temperature coefficient current generating circuit comprises a thirteenth PMOS tube MP13 and a first resistor R1;
the reference voltage generating circuit comprises a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15 and a second resistor R2;
the source end of the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 is connected with the working power supply positive;
gate ends of the eleventh PMOS tube MP11, the twelfth PMOS tube MP12 and the fourteenth PMOS tube MP14 are connected with the positive temperature coefficient operational amplifier output end VOUT_P;
the gate ends of the thirteenth PMOS tube MP13 and the fifteenth PMOS tube MP15 are connected with the negative temperature coefficient operational amplifier output end VOUT_N of the operational amplifier;
the drain end of the eleventh PMOS tube MP11 is connected with the positive temperature coefficient current positive input end INP_P of the operational amplifier;
the drain end of the twelfth PMOS tube MP12 is connected with the negative input end INN of the operational amplifier;
the emitter of the first PNP triode Q1 is connected with a positive temperature coefficient current positive input end INP_P of the operational amplifier through a zeroth resistor R0;
the emitter of the zeroth PNP triode Q0 is connected with the negative input end INN of the operational amplifier;
the bases of the first PNP triode Q1 and the zeroth PNP triode Q0 are short-circuited, and the collectors are grounded;
the drain end of the thirteenth PMOS tube MP13 is connected with the negative temperature coefficient current positive input end INP_N of the operational amplifier;
the first resistor R1 is connected in series between the drain end of the thirteenth PMOS tube MP13 and the ground;
the drain terminals of the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 are grounded through the second resistor R2 after being short-circuited, and the short-circuited terminal is used as an output terminal of zero temperature coefficient reference voltage VREF.
Preferably, the second resistor R2 is formed by connecting a plurality of resistors in series;
the serial connection point of the resistors is used for outputting zero temperature coefficient reference voltages VREF1 and VREF2 with different magnitudes.
Positive temperature coefficient current generation circuit:wherein DeltaV be ＝V T * ln (N) is positive temperature coefficient, V T For thermoelectric voltage, N is the proportionality constant of the first PNP triode Q1 and the zeroth PNP triode Q0, usually taking 8 or 24, and the like, and matching is better when the layout is realized.
Negative temperature coefficient current generation circuit:wherein V is be The voltage difference between the base electrode and the emitter electrode of the zeroth PNP triode Q0 is a negative temperature coefficient;
a reference voltage generation circuit:adjusting the value of the second resistor R2 can achieve zero temperature coefficient reference voltage output of any value.
Preferably, the reference voltage generating circuit further includes a sixteenth PMOS transistor MP16 and a third resistor R3;
the source end of the sixteenth PMOS tube MP16 is connected with the positive of the working power supply, the gate end is connected with the output end VOUTP of the positive temperature coefficient operational amplifier, and the drain end is grounded through the third resistor R3 and used as the output end of the positive temperature coefficient voltage VPTC.
The positive temperature coefficient voltage output with any central value (at room temperature) can be realized by adjusting the value of the third resistor R3.
Preferably, the reference voltage generating circuit further includes a seventeenth PMOS transistor MP17 and a fifth resistor R5;
the seventeenth PMOS tube MP17 has its gate connected to the negative temperature coefficient operational amplifier output end VOUT_N, its source connected to the positive of the working power supply, and its drain connected to ground via the fifth resistor R5 and used as the negative temperature coefficient voltage VNTC output end.
The negative temperature coefficient voltage output of any center value (at room temperature) can be realized by adjusting the value of the fifth resistor R5.
Example IV
Based on the third embodiment, the bandgap reference source circuit further comprises a reference current generating circuit;
the reference current generation circuit comprises an eighteenth PMOS tube MP18 and a nineteenth PMOS tube MP19;
the source ends of the eighteenth PMOS tube MP18 and the nineteenth PMOS tube MP19 are connected with the working power supply positive;
the gate end of the eighteenth PMOS tube MP18 is connected with the positive temperature coefficient operational amplifier output end VOUT_P;
the gate end of the nineteenth PMOS tube MP19 is connected with the negative temperature coefficient operational amplifier output end VOUT_N;
drain ends of the eighteenth PMOS tube MP18 and the nineteenth PMOS tube MP19 are connected with zero temperature coefficient current IREF ZTC output ends.
Reference current generation circuit: irefztc=k1×i0+k2×i1, where K1 and K2 are constants, and selecting appropriate values can achieve zero temperature coefficient current output. I0 is the current generated by the positive temperature coefficient current generating circuit, and I1 is the current generated by the negative temperature coefficient current generating circuit.
Preferably, the reference current generating circuit further comprises a twentieth PMOS transistor MP20;
the twenty-first PMOS tube MP20 has its source connected to the positive of the working power supply, its gate connected to the positive temperature coefficient operational amplifier output terminal VOUT_P, and its drain connected to the positive temperature coefficient current IREFTTC output terminal. Irefptc=k3×i0, where K3 is a constant.
Preferably, the reference current generating circuit further includes a second PMOS transistor MP21;
the source end of the second PMOS tube MP21 is connected with the positive of the working power supply, the gate end is connected with the output end VOUT_N of the negative temperature coefficient operational amplifier, and the drain end is connected with the output end of the negative temperature coefficient current IREFNTC. Irefnct=k4×i1, where K4 is a constant.
The bandgap reference circuit of the third embodiment can provide zero temperature coefficient (ZTC: zero temperature coefficient) voltage, positive temperature coefficient (PTC: positive temperature coefficient) voltage and negative temperature coefficient (NTC: negative temperature coefficient) voltage of arbitrary values by adopting the operational amplifier of the new circuit structure and simultaneously combining the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit, the reference voltage generating circuit and the reference current generating circuit on the basis of the theory of the existing bandgap reference circuit, and can generate positive temperature coefficient current, negative temperature coefficient current and zero temperature coefficient current at the same time, thereby saving the area. The simulation results of the output voltage and current of the bandgap reference source circuit in the third embodiment are shown in fig. 6 and 7.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Claims (17)
1. The operational amplifier is characterized by comprising a first PMOS tube (MP 1), a second PMOS tube (MP 2), a third PMOS tube (MP 3), a fourth PMOS tube (MP 4), a fifth PMOS tube (MP 5), a sixth PMOS tube (MP 6), a first NMOS tube (MN 1), a second NMOS tube (MN 2), a third NMOS tube (MN 3), a fourth NMOS tube (MN 4), a fifth NMOS tube (MN 5) and a sixth NMOS tube (MN 6);
the source ends of the first PMOS tube (MP 1), the second PMOS tube (MP 2), the third PMOS tube (MP 3), the fourth PMOS tube (MP 4), the fifth PMOS tube (MP 5) and the sixth PMOS tube (MP 6) are connected with a working voltage source (VCC);
the source ends of the first NMOS tube (MN 1), the second NMOS tube (MN 2) and the third NMOS tube (MN 3) are Grounded (GND);
the source ends of the fourth NMOS tube (MN 4), the fifth NMOS tube (MN 5) and the sixth NMOS tube (MN 6) are Grounded (GND);
the drain end of the first PMOS tube (MP 1) is connected with the drain end of the sixth NMOS tube (MN 6) and is used as a positive temperature coefficient operational amplifier output end (VOUT_P);
the gate end of the first PMOS tube (MP 1) is connected with the gate end, the drain end and the drain end of the second PMOS tube (MP 2) and the first NMOS tube (MN 1);
the drain end of the first NMOS tube (MN 1) is used as a positive temperature coefficient current positive input end (INP_P);
the drain end of the fourth PMOS tube (MP 4) is connected with the drain end of the fourth NMOS tube (MN 4) and is used as a negative temperature coefficient operational amplifier output end (VOUT_N);
the gate end of the fourth PMOS tube (MP 4) is connected with the gate end, the drain end and the drain end of the third NMOS tube (MN 3) of the third PMOS tube (MP 3);
the drain end of the third NMOS tube (MN 3) is used as a negative temperature coefficient current positive input end (INP_N);
the drain end of the sixth PMOS tube (MP 6) is connected with the drain end of the fifth NMOS tube (MN 5), and the gate ends of the fourth NMOS tube (MN 4), the fifth NMOS tube (MN 5) and the sixth NMOS tube (MN 6);
the gate end of the sixth PMOS tube (MP 6) is connected with the gate end, the drain end and the drain end of the fifth PMOS tube (MP 5) and the second NMOS tube (MN 2);
the drain of the second NMOS transistor (MN 2) is used as a negative input terminal (INN).
2. The operational amplifier of claim 1, wherein the operational amplifier is configured to,
the operational amplifier further comprises a seventh NMOS tube (MN 7) and an eighth NMOS tube (MN 8);
the drain end and the gate end of the seventh NMOS tube (MN 7) are in short circuit with the gate end of the eighth NMOS tube (MN 8) and are used for connecting bias current (IBIAS);
a source end of the seventh NMOS tube (MN 7) and a source end of the eighth NMOS tube (MN 8) are Grounded (GND);
the source ends of the first NMOS tube (MN 1), the second NMOS tube (MN 2) and the third NMOS tube (MN 3) are connected with the drain end of the eighth NMOS tube (MN 8) and are Grounded (GND) through the eighth NMOS tube MN 8.
3. A bandgap reference source circuit comprising the operational amplifier of claim 1, wherein the bandgap reference source circuit further comprises a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, and a reference voltage generation circuit;
the positive temperature coefficient current generating circuit comprises an eleventh PMOS tube (MP 11), a twelfth PMOS tube (MP 12), a first PNP triode (Q1), a zeroth PNP triode (Q0) and a zeroth resistor (R0);
the negative temperature coefficient current generating circuit comprises a thirteenth PMOS tube (MP 13) and a first resistor (R1);
the reference voltage generation circuit comprises a fourteenth PMOS tube (MP 14), a fifteenth PMOS tube (MP 15) and a second resistor (R2);
the source end of the eleventh PMOS tube (MP 11), the twelfth PMOS tube (MP 12), the thirteenth PMOS tube (MP 13), the fourteenth PMOS tube (MP 14) and the fifteenth PMOS tube (MP 15) is connected with the working power supply positive;
the gate ends of the eleventh PMOS tube (MP 11), the twelfth PMOS tube (MP 12) and the fourteenth PMOS tube (MP 14) are connected with the positive temperature coefficient operational amplifier output end (VOUT_P);
the gate ends of the thirteenth PMOS tube (MP 13) and the fifteenth PMOS tube (MP 15) are connected with the negative temperature coefficient operational amplifier output end (VOUT_N) of the operational amplifier;
the drain end of the eleventh PMOS tube (MP 11) is connected with the positive temperature coefficient current positive input end (INP_P) of the operational amplifier;
the drain end of the twelfth PMOS tube (MP 12) is connected with the negative input end (INN) of the operational amplifier;
the emitter of the first PNP triode (Q1) is connected with the positive temperature coefficient current positive input end (INP_P) of the operational amplifier through a zeroth resistor (R0);
the emitter of the zeroth PNP triode (Q0) is connected with the negative input end (INN) of the operational amplifier;
the bases of the first PNP triode (Q1) and the zeroth PNP triode (Q0) are short-circuited, and the collectors are grounded;
the drain end of the thirteenth PMOS tube (MP 13) is connected with the negative temperature coefficient current positive input end (INP_N) of the operational amplifier;
the first resistor (R1) is connected in series between the drain end of the thirteenth PMOS tube (MP 13) and the ground;
the drain ends of the fourteenth PMOS tube (MP 14) and the fifteenth PMOS tube (MP 15) are grounded through the second resistor (R2) after being short-circuited, and the short-circuited end is used as an output end of zero temperature coefficient reference Voltage (VREF).
4. A bandgap reference source circuit according to claim 3, wherein,
the second resistor (R2) is formed by connecting a plurality of resistors in series;
the series connection point of the plurality of resistors is used for outputting zero temperature coefficient reference voltages with different sizes.
5. A bandgap reference source circuit according to claim 3, wherein,
the reference voltage generating circuit further comprises a sixteenth PMOS tube (MP 16) and a third resistor (R3);
the source end of the sixteenth PMOS tube (MP 16) is connected with the positive of the working power supply, the gate end is connected with the positive temperature coefficient operational amplifier output end (VOUT_P), and the drain end is grounded through the third resistor (R3) and is used as the positive temperature coefficient Voltage (VPTC) output end.
6. The bandgap reference circuit according to claim 5, wherein,
the reference voltage generating circuit further comprises a seventeenth PMOS tube (MP 17) and a fifth resistor (R5);
the seventeenth PMOS tube (MP 17) has its gate connected to the negative temperature coefficient operational amplifier output end (VOUT_N), its source connected to the working power supply positive, and its drain connected to ground via the fifth resistor (R5) and used as the negative temperature coefficient Voltage (VNTC) output end.
7. The bandgap reference circuit of claim 3, 4, 5 or 6, wherein,
the band gap reference source circuit further comprises a reference current generating circuit;
the reference current generation circuit comprises an eighteenth PMOS tube (MP 18) and a nineteenth PMOS tube (MP 19);
the source ends of the eighteenth PMOS tube (MP 18) and the nineteenth PMOS tube (MP 19) are connected with the working power supply positive;
the gate end of the eighteenth PMOS tube (MP 18) is connected with the positive temperature coefficient operational amplifier output end (VOUT_P);
the grid end of the nineteenth PMOS tube (MP 19) is connected with the negative temperature coefficient operational amplifier output end (VOUT_N);
drain ends of the eighteenth PMOS tube (MP 18) and the nineteenth PMOS tube (MP 19) are connected with zero temperature coefficient current (IREF ZTC) output ends.
8. The bandgap reference circuit according to claim 7, wherein,
the reference current generation circuit further comprises a twentieth PMOS tube (MP 20);
the source end of the twenty-first PMOS tube (MP 20) is connected with the positive of the working power supply, the gate end is connected with the positive temperature coefficient operational amplifier output end (VOUT_P), and the drain end is connected with the positive temperature coefficient current (IREFTTC) output end.
9. The bandgap reference circuit according to claim 8, wherein,
the reference current generation circuit further comprises a second PMOS tube (MP 21);
the source end of the second PMOS tube (MP 21) is connected with the positive of the working power supply, the gate end is connected with the negative temperature coefficient operational amplifier output end (VOUT_N), and the drain end is connected with the negative temperature coefficient current (IREF NTC) output end.
10. The operational amplifier is characterized by comprising a first PMOS tube (MP 1), a second PMOS tube (MP 2), a seventh PMOS tube (MP 7), an eighth PMOS tube (MP 8), a ninth PMOS tube (MP 9), a tenth PMOS tube (MP 10), an eleventh NMOS tube (MN 11), a twelfth NMOS tube (MN 12), a thirteenth NMOS tube (MN 13), a fourteenth NMOS tube (MN 14), a fifteenth NMOS tube (MN 15) and a sixteenth NMOS tube (MN 16);
source ends of an eleventh NMOS tube (MN 11), a twelfth NMOS tube (MN 12), a thirteenth NMOS tube (MN 13), a fourteenth NMOS tube (MN 14), a fifteenth NMOS tube (MN 15) and a sixteenth NMOS tube (MN 16) are Grounded (GND);
the source ends of the first PMOS tube (MP 1), the second PMOS tube (MP 2) and the seventh PMOS tube (MP 7) are connected with a working voltage source (VCC);
the drain end of the first PMOS tube (MP 1) is connected with the drain end of the fifteenth NMOS tube (MN 15) and is used as a positive temperature coefficient operational amplifier output end (VOUT_P);
the drain end of the seventh PMOS tube (MP 7) is connected with the drain end of the sixteenth NMOS tube (MN 16) and is used as a negative temperature coefficient operational amplifier output end (VOUT_N);
the gate end, the drain end and the gate end of the second PMOS tube (MP 2) and the gate end of the first PMOS tube (MP 1) and the gate end of the seventh PMOS tube (MP 7) are connected with the drain end of the fourteenth NMOS tube (MN 14) simultaneously;
the source end of the eighth PMOS tube (MP 8), the ninth PMOS tube (MP 9) and the tenth PMOS tube (MP 10) is connected with bias current (IBIAS);
the drain end of the eighth PMOS tube (MP 8) is connected with the drain end, the gate end and the gate end of the fifteenth NMOS tube (MN 13) of the thirteenth NMOS tube (MN 15);
the gate end of the eighth PMOS tube (MP 8) is used as a positive temperature coefficient current positive input end (INP_P);
the drain end of the ninth PMOS tube (MP 9) is connected with the drain end, the gate end and the gate end of the sixteenth NMOS tube (MN 11) and the gate end of the sixteenth NMOS tube (MN 16);
the gate end of the ninth PMOS tube (MP 9) is used as a negative temperature coefficient current positive input end (INP_N);
the drain end of the tenth PMOS tube (MP 10) is connected with the drain end, the gate end and the gate end of the fourteenth NMOS tube (MN 12) and the gate end of the fourteenth NMOS tube (MN 14);
the gate terminal of the tenth PMOS transistor (MP 10) is used as a negative input terminal (INN).
11. A bandgap reference source circuit comprising the operational amplifier of claim 10, wherein the bandgap reference source circuit further comprises a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, and a reference voltage generation circuit;
the positive temperature coefficient current generating circuit comprises an eleventh PMOS tube (MP 11), a twelfth PMOS tube (MP 12), a first PNP triode (Q1), a zeroth PNP triode (Q0) and a zeroth resistor (R0);
the negative temperature coefficient current generating circuit comprises a thirteenth PMOS tube (MP 13) and a first resistor (R1);
the reference voltage generation circuit comprises a fourteenth PMOS tube (MP 14), a fifteenth PMOS tube (MP 15) and a second resistor (R2);
the source end of the eleventh PMOS tube (MP 11), the twelfth PMOS tube (MP 12), the thirteenth PMOS tube (MP 13), the fourteenth PMOS tube (MP 14) and the fifteenth PMOS tube (MP 15) is connected with the working power supply positive;
the gate ends of the eleventh PMOS tube (MP 11), the twelfth PMOS tube (MP 12) and the fourteenth PMOS tube (MP 14) are connected with the positive temperature coefficient operational amplifier output end (VOUT_P);
the gate ends of the thirteenth PMOS tube (MP 13) and the fifteenth PMOS tube (MP 15) are connected with the negative temperature coefficient operational amplifier output end (VOUT_N) of the operational amplifier;
the drain end of the eleventh PMOS tube (MP 11) is connected with the positive temperature coefficient current positive input end (INP_P) of the operational amplifier;
the drain end of the twelfth PMOS tube (MP 12) is connected with the negative input end (INN) of the operational amplifier;
the emitter of the first PNP triode (Q1) is connected with the positive temperature coefficient current positive input end (INP_P) of the operational amplifier through a zeroth resistor (R0);
the emitter of the zeroth PNP triode (Q0) is connected with the negative input end (INN) of the operational amplifier;
the bases of the first PNP triode (Q1) and the zeroth PNP triode (Q0) are short-circuited, and the collectors are grounded;
the drain end of the thirteenth PMOS tube (MP 13) is connected with the negative temperature coefficient current positive input end (INP_N) of the operational amplifier;
the first resistor (R1) is connected in series between the drain end of the thirteenth PMOS tube (MP 13) and the ground;
the drain ends of the fourteenth PMOS tube (MP 14) and the fifteenth PMOS tube (MP 15) are grounded through the second resistor (R2) after being short-circuited, and the short-circuited end is used as an output end of zero temperature coefficient reference Voltage (VREF).
12. The bandgap reference circuit according to claim 11, wherein,
the second resistor (R2) is formed by connecting a plurality of resistors in series;
the series connection point of the plurality of resistors is used for outputting zero temperature coefficient reference voltages with different sizes.
13. The bandgap reference circuit according to claim 11, wherein,
the reference voltage generating circuit further comprises a sixteenth PMOS tube (MP 16) and a third resistor (R3);
the source end of the sixteenth PMOS tube (MP 16) is connected with the positive of the working power supply, the gate end is connected with the positive temperature coefficient operational amplifier output end (VOUT_P), and the drain end is grounded through the third resistor (R3) and is used as the positive temperature coefficient Voltage (VPTC) output end.
14. The bandgap reference circuit according to claim 13, wherein,
the reference voltage generating circuit further comprises a seventeenth PMOS tube (MP 17) and a fifth resistor (R5);
the seventeenth PMOS tube (MP 17) has its gate connected to the negative temperature coefficient operational amplifier output end (VOUT_N), its source connected to the working power supply positive, and its drain connected to ground via the fifth resistor (R5) and used as the negative temperature coefficient Voltage (VNTC) output end.
15. The bandgap reference circuit according to claim 11, 12, 13 or 14, characterized in that,
the band gap reference source circuit further comprises a reference current generating circuit;
the reference current generation circuit comprises an eighteenth PMOS tube (MP 18) and a nineteenth PMOS tube (MP 19);
the source ends of the eighteenth PMOS tube (MP 18) and the nineteenth PMOS tube (MP 19) are connected with the working power supply positive;
the gate end of the eighteenth PMOS tube (MP 18) is connected with the positive temperature coefficient operational amplifier output end (VOUT_P);
the grid end of the nineteenth PMOS tube (MP 19) is connected with the negative temperature coefficient operational amplifier output end (VOUT_N);
drain ends of the eighteenth PMOS tube (MP 18) and the nineteenth PMOS tube (MP 19) are connected with zero temperature coefficient current (IREF ZTC) output ends.
16. The bandgap reference circuit according to claim 15, wherein,
the reference current generation circuit further comprises a twentieth PMOS tube (MP 20);
the source end of the twenty-first PMOS tube (MP 20) is connected with the positive of the working power supply, the gate end is connected with the positive temperature coefficient operational amplifier output end (VOUT_P), and the drain end is connected with the positive temperature coefficient current (IREFTTC) output end.
17. The bandgap reference circuit according to claim 16, wherein,
the reference current generation circuit further comprises a second PMOS tube (MP 21);
the source end of the second PMOS tube (MP 21) is connected with the positive of the working power supply, the gate end is connected with the negative temperature coefficient operational amplifier output end (VOUT_N), and the drain end is connected with the negative temperature coefficient current (IREF NTC) output end.
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