CN102541149A - Reference power circuit - Google Patents
Reference power circuit Download PDFInfo
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- CN102541149A CN102541149A CN2010106204998A CN201010620499A CN102541149A CN 102541149 A CN102541149 A CN 102541149A CN 2010106204998 A CN2010106204998 A CN 2010106204998A CN 201010620499 A CN201010620499 A CN 201010620499A CN 102541149 A CN102541149 A CN 102541149A
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Abstract
The invention discloses a reference power circuit, which comprises a band gap reference power circuit, a voltage and current conversion circuit and a current add circuit, wherein the band gap reference power circuit is used for generating first current of a positive temperature coefficient and reference voltage of a negative temperature coefficient; the voltage and current conversion circuit is used for converting the reference voltage of the negative temperature coefficient into second current with a negative temperature coefficient; and the current add circuit is used for superposing the first current of the positive temperature coefficient and the second current with the negative temperature coefficient to generate reference current. The output accuracy of the reference power circuit is high, and the temperature drift characteristic and the power voltage rejection ratio characteristic are improved.
Description
Technical field
The present invention relates to electronic circuit technology, particularly relate to a kind of reference power circuit.
Background technology
Reference voltage or reference current that reference source can generation has nothing to do, has definite temperature characterisitic with power supply and technology.In IC design such as A/D converter (ADC), D/A (DAC), dynamic storage (DRAM), Flash storer, the design of the reference source of low-temperature coefficient (TC), low-power consumption, high PSRR (PSRR) is very crucial.
Fig. 1 is existing a kind of band gap (Bandgap) reference power circuit that temperature characterisitic is carried out a curvature compensation; Band-gap reference circuit (branch road of PNP pipe Q11 and Q12) produces positive temperature coefficient (PTC) (PTAT) electric current; Base stage and the emitter voltage Vbe of PNP pipe Q12 are negative temperature coefficient voltage; Both mutual superposition produce reference voltage V ref1.
Mainly there are two problems in reference power circuit shown in Figure 1: owing to the short-channel effect of PMOS pipe M11 and M12 in the circuit, the reference voltage of output receives the interference of supply voltage bigger, causes the PSRR characteristic of circuit relatively poor (1); (2) since in the circuit manufacturing process deviation of resistance R 11 and R12 and BJT manage the mismatch problems of Q11 and Q12, the reference voltage of output is acted upon by temperature changes bigger, it is relatively poor to cause the temperature of circuit to float characteristic.Therefore, the reference voltage V ref1 precision of reference power circuit output shown in Figure 1 is low, can't be applied to high-precision adc circuit.
The solution of existing a kind of addressing the above problem (1) is as shown in Figure 2; Change the PMOS pipe that links to each other with voltage source V DD among Fig. 1 into cascade (cascode) current-mirror structure; To improve inhibition ability to supply voltage VDD fluctuation; The cascode current mirror 21 and 22 of connecting among Fig. 2 has effectively suppressed the short-channel effect of PMOS pipe M11 and M12, has improved circuit in the PSRR of low-frequency range characteristic.And, increased big capacitor C 1 at the output terminal of reference voltage V ref2 and improved circuit in the PSRR of high band characteristic.Reference power circuit shown in Figure 2 is the circuit of a temperature curvature collocation structure, and it is relatively poor that the temperature of circuit is floated characteristic; And though improved the PSRR characteristic to a certain extent, in fact line-voltage regulation is still higher, and when for example changing in supply voltage 3～3.6V scope, line-voltage regulation still is higher than 100ppm/V.
The solution of existing a kind of addressing the above problem (2) is as shown in Figure 3, and it is for adopting the reference circuit of the quadratic curvature compensation of eliminating the method for nonlinear terms among the Vbe.Among Fig. 3, the voltage between BJT pipe base stage and the emitter has negative temperature coefficient, and voltage reduces with the increase of temperature, is expressed as:
Wherein, V
BGBe the PN junction external voltage that absolute zero is derived, T
0Be reference temperature, T is an absolute temperature, V
BE0For temperature is T
0The time emitter junction voltage, the value of η is relevant with the structure of triode, gets 4 usually, the value of α is relevant with the character of the electric current that flows through triode, when flowing through the PTAT electric current, gets 1, when the electric current that flows through is uncorrelated with temperature, gets 0.If make a triode flow through the PTAT electric current, another triode flows through temperature independent electric current, then the difference of the base stage of two triodes and emitter voltage will be one with following formula in the 3rd amount that is directly proportional.The base stage and the emitter voltage that promptly flow through the PNP pipe of PTAT electric current are:
The base stage and the emitter voltage that flow through the PNP pipe of temperature independent electric current are:
The base stage of two pipes and emitter voltage difference are:
Among Fig. 3; The electric current that flows through PNP pipe Q1 and Q2 is the PTAT electric current, and the electric current that flows through PMOS pipe M1 and M2 is temperature independent, and the electric current that flows through PMOS pipe M3 is the image current that flows through the electric current of PMOS pipe M1; So it is temperature independent to flow through the electric current of PNP pipe Q3, the electric current that then flows through resistance R 4 and R5 is:
The electric current that flows through PMOS pipe M4 (electric current that flows through PMOS pipe M4 is the image current that flows through the electric current of PMOS pipe M1) is made up of three parts, and therefore the reference voltage of output is:
N=S
Q2/ S
Q1, S
Q1And S
Q2Be respectively the sectional area of triode Q1 and Q2.This method has been constructed the electric current that can offset nonlinear component cleverly, makes reference voltage V ref3 realize zero-temperature coefficient.
Yet; Still there is following problem in reference power circuit shown in Figure 3: a plurality of resistance have been adopted in (1); In when, when manufacturing process variations deviation taking place; The Standard resistance range fluctuation of resistance is excessive, and the error that makes circuit itself produce may lose meaning thereby cause quadratic curvature to compensate greater than the precision of quadratic curvature compensation; (2) resistance of resistance R 4 and R5 is very big, take a large amount of layout areas, and debugging difficulty is big, occurs the situation of the reverse direction current flow of resistance R 4 and R5 easily; (3) topological structure of circuit is also complicated.
Therefore, the temperature of existing reference power circuit is floated the application requirements that characteristic and supply-voltage rejection ratio characteristic still can't satisfy high-precision simulation, mixed-signal system (the for example above adc circuit of 10bit).
Summary of the invention
The problem that the present invention solves is that the temperature of existing reference power circuit is floated characteristic and power supply rejection ratio characteristics is poor, and output accuracy is not high.
For addressing the above problem, embodiment of the present invention provides a kind of reference power circuit, comprising: the band-gap reference power circuit produces first electric current of positive temperature coefficient (PTC) and the reference voltage of negative temperature coefficient; Voltage-current converter circuit converts the reference voltage of said negative temperature coefficient in second electric current of negative temperature coefficient; Electric current adds and circuit, and first electric current of the said positive temperature coefficient (PTC) that superposes and second electric current of negative temperature coefficient produce reference current.
Optional; Said band-gap reference power circuit comprises: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, first operational amplifier, first resistance, second resistance, NMOS pipe, the 2nd NMOS pipe, PNP pipe, the 2nd PNP pipe and the 3rd PNP pipe
Said first, second source electrode with the 5th PMOS pipe connects voltage source; The source electrode of said the 3rd PMOS pipe is connected with the drain electrode of said PMOS pipe; The source electrode of said the 4th PMOS pipe is connected with the drain electrode of said the 2nd PMOS pipe; The source electrode of said the 6th PMOS pipe is connected with the drain electrode of said the 5th PMOS pipe, and said negative temperature coefficient voltage is exported in the drain electrode of said the 6th PMOS pipe;
The positive input terminal of said first operational amplifier is connected with the drain electrode of said the 3rd PMOS pipe; Negative input end is connected with the drain electrode of said the 4th PMOS pipe, and the output terminal of said first operational amplifier is connected with the grid of the 6th PMOS pipe with the said the first, second, third, fourth, the 5th;
First end of said first resistance is connected with the drain electrode of said the 3rd PMOS pipe, and first end of said second resistance is connected with the drain electrode of said the 6th PMOS pipe;
The drain electrode of said NMOS pipe is connected second end of said first resistance with the emitter of PNP pipe; The drain electrode of said the 2nd NMOS pipe is connected the drain electrode of said the 4th PMOS pipe with the emitter of the 2nd PNP pipe; The source ground of the base stage of said first and second PNP pipe, collector and said first and second NMOS pipe, the grid of said first and second NMOS pipe is imported first bias voltage;
The emitter of said the 3rd PNP pipe connects second end of said second resistance, base stage and grounded collector, and first electric current of said positive temperature coefficient (PTC) is the electric current that flows through said second resistance,
The ratio of the sectional area of said the 2nd PNP pipe and PNP pipe is set based on reference temperature, and said reference temperature is less than minimum operating temperature.
Optional, said voltage-current converter circuit comprises: second operational amplifier, the 7th PMOS pipe, the 8th PMOS pipe and the 3rd resistance,
The positive input terminal of said second operational amplifier connects first end of said the 3rd resistance; Negative input end connects the drain electrode of said the 6th PMOS pipe; Output terminal connects the grid of said the 7th PMOS pipe, the grid of said the 8th PMOS pipe and the second end ground connection of the 3rd resistance;
The source electrode of said the 7th PMOS pipe connects voltage source, and drain electrode connects the source electrode of said the 8th PMOS pipe, and the drain electrode of said the 8th PMOS pipe connects first end of said the 3rd resistance;
Second electric current of said negative temperature coefficient is the electric current that flows through said the 3rd resistance.
Optional, said the 3rd resistance is polysilicon resistance.
Optional, said electric current adds with circuit and comprises: the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe,
The grid of said the 9th PMOS pipe connects the output terminal of said second operational amplifier, and the grid of said the tenth PMOS pipe connects the output terminal of said first operational amplifier, and the said the 9th is connected voltage source with source electrode that the tenth PMOS manages;
The source electrode of said the 11 PMOS pipe connects the drain electrode of said the 9th PMOS pipe, and the source electrode of said the 12 PMOS pipe connects the drain electrode of said the tenth PMOS pipe, the grounded-grid of the said the 11 and 12 PMOS pipe, and drain electrode connects the source electrode of said the 13 PMOS pipe;
The grounded-grid of said the 13 PMOS pipe, drain electrode produces said reference current.
Optional, the said the 11 and 12 PMOS pipe is operated in dark linear zone, grounded-grid, substrate and the source shorted of the said the 11 and 12 PMOS pipe.
Optional, the substrate of said the 13 PMOS pipe connects voltage source.
Optional; Said electric current adds with circuit and also comprises: the 3rd NMOS pipe and the 4th NMOS pipe; The drain electrode of said the 3rd NMOS pipe, grid and the grid of said the 4th NMOS pipe are connected the drain electrode of said the 13 PMOS pipe; The source ground of said third and fourth NMOS pipe, the drain electrode of said the 4th NMOS pipe produces output current.
Optional, also comprise start-up circuit, be connected with said band-gap reference power circuit, to said band-gap reference power circuit said first bias voltage is provided.
Optional, said start-up circuit comprises: phase inverter, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 5th NMOS pipe and electric capacity,
Said phase inverter is exported said first bias voltage;
The grid of said the 14 PMOS pipe is connected with the input end of said phase inverter; The grid of said the 15 PMOS pipe is connected with the output terminal of said operational amplifier; The drain electrode of said the 16 PMOS pipe is connected with the negative input end of said operational amplifier, and said the 14, the 15 and the 16 PMOS pipe source electrode connects voltage source;
The said the 14 is connected with first end of said electric capacity with the drain electrode of the 15 PMOS pipe, the grid of the 16 PMOS pipe and the drain electrode of the 5th NMOS pipe; The source ground of second end of said electric capacity and said the 5th NMOS pipe, the grid of said the 5th NMOS pipe is imported second bias voltage.
Compared with prior art; The band-gap reference circuit of technique scheme provides the reference voltage of negative temperature coefficient feature and the electric current of ptc characteristics; Voltage-current converter circuit converts the reference voltage of negative temperature coefficient in the electric current of negative temperature coefficient; Electric current adds and the electric current of the positive temperature coefficient (PTC) of a temperature compensation of circuit stack and the electric current of negative temperature coefficient; Realize the curvature compensation of secondary temperature characterisitic thus, thereby generate the reference current of low-temperature coefficient, improved the temperature of circuit and floated characteristic.
Further, utilize electric current add with circuit in the power source change rate of source gate voltage and threshold voltage of PMOS pipe offset and reduce line-voltage regulation, improved the PSRR characteristic of circuit.
Band-gap reference circuit provides the reference voltage and the PTAT electric current of single order temperature compensation simultaneously, has practiced thrift circuit layout area, has also simplified the complexity of circuit.
Description of drawings
Fig. 1 is the synoptic diagram of the band-gap reference power circuit of an existing a kind of curvature compensation;
Fig. 2 is the synoptic diagram of existing a kind of improved reference power circuit;
Fig. 3 is the synoptic diagram of the improved reference power circuit of existing another kind;
Fig. 4 is the synoptic diagram of the reference power circuit of the embodiment of the invention;
Fig. 5 is the simulation curve figure of reference voltage V ref among Fig. 4;
Fig. 6 is positive temperature coefficient (PTC) electric current and negative temperature coefficient current compensation principle schematic;
Fig. 7 is reference current Iref and the simulation relation curve figure of temperature among Fig. 4;
Fig. 8 is reference current Iref among Fig. 4 synoptic diagram with mains voltage variations when the 11,12 PMOS pipe breadth length ratio is got different value;
Fig. 9 is reference current Iref and the simulation relation curve figure of supply voltage among Fig. 4.
Embodiment
The reference power circuit of embodiment of the present invention utilizes voltage-current converter circuit the reference voltage of the negative temperature coefficient of the band-gap reference circuit generation of a temperature compensation to be converted to the electric current of negative temperature coefficient; Utilize electric current to add the electric current of the positive temperature coefficient (PTC) that generates with circuit stacked tape gap reference circuit and the electric current of the negative temperature coefficient that voltage-current converter circuit is changed again; Realize the curvature compensation of secondary temperature characterisitic thus; Thereby generate the reference current of low-temperature coefficient, improved the temperature of circuit and floated characteristic.
Further, utilized electric current add with circuit in the power source change rate of source gate voltage and threshold voltage of PMOS pipe offset and reduce line-voltage regulation, improved the PSRR characteristic of circuit.
The reference power circuit of embodiment of the present invention comprises: band-gap reference power circuit, voltage-current converter circuit and electric current add and circuit, wherein,
The band-gap reference power circuit produces first electric current of positive temperature coefficient (PTC) and the reference voltage of negative temperature coefficient;
Voltage-current converter circuit converts the reference voltage of said negative temperature coefficient in second electric current of negative temperature coefficient;
Electric current adds and circuit, and first electric current of the said positive temperature coefficient (PTC) that superposes and second electric current of negative temperature coefficient produce reference current.
Below in conjunction with accompanying drawing and embodiment the specific embodiment of the invention is done detailed explanation.Fig. 4 is the synoptic diagram of the reference power circuit of the embodiment of the invention, and said reference power circuit comprises that at least band-gap reference power circuit 12, voltage-current converter circuit 13 and electric current add and circuit 14.
Band-gap reference power circuit 12 comprises: PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, first operational amplifier A 1, the first resistance R A1, the second resistance R A2, NMOS pipe MN1, the 2nd NMOS pipe MN2, PNP pipe QP1, the 2nd PNP pipe QP2 and the 3rd PNP pipe QP3.
The grid of the one PMOS pipe MP1 connects the output terminal of first operational amplifier A 1, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 3rd PMOS pipe MP3.
The grid of the 2nd PMOS pipe MP2 connects the output terminal of first operational amplifier A 1, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 4th PMOS pipe MP4.
The grid of the 3rd PMOS pipe MP3 connects the output terminal of first operational amplifier A 1, and source electrode connects the drain electrode of PMOS pipe MP1, and drain electrode connects the positive input terminal of first operational amplifier A 1.
The grid of the 4th PMOS pipe MP4 connects the output terminal of first operational amplifier A 1, and source electrode connects the drain electrode of the 2nd PMOS pipe MP2, and drain electrode connects the negative input end of first operational amplifier A 1.
First end of the first resistance R A1 connects the drain electrode of the 3rd PMOS pipe MP3 and the positive input terminal of first operational amplifier A 1, and second end connects the emitter of PNP pipe QP1.
The grid of the one NMOS pipe MN1 is imported the first bias voltage PD, and drain electrode connects second end of the first resistance R A1 and the emitter of PNP pipe QP1, source ground.
The grid of the 2nd NMOS pipe MN2 is imported the first bias voltage PD, and drain electrode connects the drain electrode of the 4th PMOS pipe MP4 and the emitter of the 2nd PNP pipe QP2, source ground.
The emitter of the one PNP pipe QP1 connects the drain electrode of NMOS pipe MN1 and second end, base stage and the grounded collector of the first resistance R A1.
The emitter of the 2nd PNP pipe QP2 connects the drain electrode of the 2nd NMOS pipe MN2 and negative input end, base stage and the grounded collector of first operational amplifier A 1.
The grid of the 5th PMOS pipe MP5 connects the output terminal of first operational amplifier A 1, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 6th PMOS pipe MP6.
The grid of the 6th PMOS pipe MP6 connects the output terminal of first operational amplifier A 1, and source electrode connects the drain electrode of the 5th PMOS pipe MP5, drains to be the output terminal of the reference voltage V ref of negative temperature coefficient.
First end of the second resistance R A2 connects the drain electrode of the 6th PMOS pipe MP6, and second end connects the emitter of the 3rd PNP pipe QP3, base stage and the grounded collector of the 3rd PNP pipe QP3.
The electric current of the second resistance R A2 branch road is first electric current I 1 of positive temperature coefficient (PTC), and the electric current that promptly flows through the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the second resistance R A2 and the 3rd PNP pipe QP3 is first electric current I 1 of positive temperature coefficient (PTC).
Need to prove; Those skilled in the art should be appreciated that; The band-gap reference power circuit is not limited to the described circuit structure of present embodiment, and it can also be the band-gap reference power circuit of a temperature compensation of the reference voltage of other existing generation PTAT electric currents and negative temperature coefficient.
The one PNP pipe QP1, the 2nd PNP pipe QP2 and the 3rd PNP pipe QP3 branch road generate the PTAT electric current, and two branch roads that promptly link to each other with the positive-negative input end of first operational amplifier A 1 generate the PTAT electric current, and the second resistance R A2 branch road generates first electric current I 1 of positive temperature coefficient (PTC).And the current mirror that uses in the circuit is cascode current mirror (first～the 6th PMOS pipe MP1～MP6) to improve the supply-voltage rejection ratio characteristic of circuit.
Band-gap reference circuit 12 utilizes the band-gap reference of a temperature compensation to obtain the reference voltage V ref of negative temperature coefficient, and the second resistance R A2 branch road generates the reference voltage of a temperature compensation.Specifically, the voltage through a voltage with positive temperature coefficient (PTC) and a negative temperature coefficient realizes that through suitable weighted sum the reference voltage that produces through the two weighting is:
Wherein, V
BE3Be base stage and the emitter voltage (voltage of negative temperature coefficient) of the 3rd PNP pipe QP3, K is a Boltzmann constant, and q is the quantity of electric charge, and T is an absolute temperature, n=S
QP2/ S
QP1, S
QP1And S
QP2Be respectively the sectional area of PNP pipe QP1 and the 2nd PNP pipe QP2.To following formula (V
RefMathematical expression) ask second derivative to get:
Wherein, constant alpha, β, q greater than zero, can know
So reference voltage V ref is the convex function that Open Side Down, the simulation curve of the MATLAB of reference voltage V ref as shown in Figure 5, when
The time T=T
0, i.e. the summit of convex function (curvature is 0) is so the working temperature of circuit is higher than T
0When (reference temperature), reference voltage raises with temperature and reduces, therefore, and reference temperature T
0Be arranged on the left side of operating temperature range,, can produce reference voltage V ref thus with negative temperature characteristic promptly less than minimum operating temperature.For example, when operating temperature range is-40 ℃～85 ℃, promptly T
0Be arranged on and be lower than-40 ℃ temperature, so just can be according to formula
Derive the design parameter of a key in the circuit, promptly BJT manages the ratio n of the sectional area of (the 2nd PNP pipe QP2 and PNP pipe QP1), wherein, and T=T
0,
Be temperature T
0The time base stage and the emitter voltage of the 3rd PNP pipe QP3, E
gBe the energy gap of silicon, m is relevant with the electric current character that flows through the BJT pipe, is the PTAT electric current here, therefore gets 1.
Continuation is with reference to figure 4, and the voltage-current converter circuit 13 of present embodiment comprises: second operational amplifier A 2, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8 and the 3rd resistance R A3.
The positive input terminal of second operational amplifier A 2 connects the drain electrode of first end and the 8th PMOS pipe MP8 of the 3rd resistance R A3; The output terminal of negative input end connecting band gap reference circuit 12 (i.e. the drain electrode of the 6th PMOS pipe MP6), output terminal connects the grid of the 7th PMOS pipe MP7.
The grid of the 7th PMOS pipe MP7 connects the output terminal of second operational amplifier A 2, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 8th PMOS pipe MP8.
The drain electrode of the 8th PMOS pipe connects first end of the 3rd resistance;
The grid of said the 8th PMOS pipe and the second end ground connection of the 3rd resistance.
The reference voltage V ref that voltage-current converter circuit 13 will have negative temperature coefficient feature converts the electric current with uniform temp coefficient feature into; Specifically, the 3rd resistance R A3 has ptc characteristics, for example is polysilicon resistance; The 3rd resistance R A3 branch road generates second electric current I 2 of negative temperature coefficient; Second operational amplifier A 2 is a high gain operational amplifier, and its positive-negative input end voltage magnitude equates that phase place is opposite; When the reference voltage V ref of negative temperature coefficient is added in the 3rd resistance R A3 of positive temperature coefficient (PTC), generate second electric current I 2 of negative temperature coefficient.
Therefore, the electric current of the 3rd resistance R A3 branch road is second electric current I 2 of negative temperature coefficient, and the electric current that promptly flows through the 7th PMOS pipe MP7, the 8th PMOS pipe MP8 and the 3rd resistance R A3 is second electric current I 2 of negative temperature coefficient.
Need to prove; Those skilled in the art should be appreciated that; Can generate the principle of the electric current of negative temperature coefficient when being added in the resistance of positive temperature coefficient (PTC) based on above-mentioned voltage with negative temperature coefficient; Voltage-current converter circuit should be not limited to the described circuit structure of present embodiment, and it can also have other multiple mapped structures.
The electric current of present embodiment adds with circuit 14 and comprises: the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 13 PMOS pipe MP13, the 3rd NMOS pipe MN3 and the 4th NMOS pipe MN4.
The grid of the 9th PMOS pipe MP9 connects the output terminal of second operational amplifier A 2, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 11 PMOS pipe MP11.
The grid of the tenth PMOS pipe MP10 connects the output terminal of first operational amplifier A 1, and source electrode connects voltage source V DD, and drain electrode connects the source electrode of the 12 PMOS pipe MP12.
The source electrode of the 11 PMOS pipe MP11 connects the drain electrode of the 9th PMOS pipe MP9, grounded-grid, and drain electrode connects the source electrode of the 13 PMOS pipe MP13.
The source electrode of the 12 PMOS pipe MP12 connects the drain electrode of the tenth PMOS pipe MP10, grounded-grid, and drain electrode connects the source electrode of the 13 PMOS pipe MP13.
The grounded-grid of the 13 PMOS pipe MP13, source electrode connect the drain electrode of the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12, and drain electrode connects the drain electrode of the 3rd NMOS pipe MN3.The electric current that the drain electrode of the 13 PMOS pipe MP13 produces is reference current Iref, and the electric current that promptly flows through the 13 PMOS pipe MP13 is reference current Iref.
The grid of the 3rd NMOS pipe MN3 is connected the drain electrode of the 13 PMOS pipe MP13, source ground with drain electrode.
The grid of the 4th NMOS pipe MN4 connects grid and the drain electrode of the 3rd NMOS pipe MN3, source ground, and draining is the output terminal of output current Iout, the electric current that flows through the 4th NMOS pipe MN4 is output current Iout.
Substrate and the source shorted of the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12 are to suppress the inclined to one side effect of lining.The substrate of the 13 PMOS pipe MP13 connects voltage source V DD, to follow the fluctuation of supply voltage.
Output current Iout is the image current of reference current Iref, and its ratio is the grid width of the 4th NMOS pipe MN4 and the ratio that the 3rd NMOS manages the grid width of MN3.Reference current Iref also can directly add the electric current of exporting with circuit as electric current.
Electric current adds the curvature compensation of realizing the secondary temperature characterisitic with circuit 14, promptly realizes the compensation of secondary temperature curvature through first electric current I 1 of the PTAT of generation in the stack band gap reference power circuit 12 and second electric current I 2 of the negative temperature characteristic of voltage-current converter circuit 13 generations.
Positive temperature coefficient (PTC) electric current and negative temperature coefficient current compensation principle are as shown in Figure 6; First electric current I 1 and 2 of second electric current I are carried out the single order temperature compensation; So by first approximation, second electric current I 2 of available straight line AB linear process negative temperature coefficient, the contact of a curve of making a straight line CD parallel with AB and I2 is in an E; The slope of this point is zero after compensation, so the corresponding temperature T 2 of E point is a reference current zero temp shift point.
With reference to figure 4, reference current Iref is: I
Ref=I
b+ I
a=m
1I
1+ m
2I
2, wherein, Ib is the image current of I1, m1 is the ratio of common source pipe on the tenth PMOS pipe MP10 and the I1 branch road (i.e. the 5th PMOS pipe MP5) grid width; Ia is the image current of I2, and m2 is the ratio of common source pipe on the 9th PMOS pipe MP9 and the I2 branch road (i.e. the 7th PMOS pipe MP7) grid width.In the present embodiment, I
a≈ I
b, with I
A, bExpression.
First electric current I 1 with the relation of temperature T is:
Reference voltage V ref is V
Ref=V
G0+ V
T(3-n) (1+lnT/T
0), V wherein
G0Be the silicon bandgap voltage under the absolute zero.
The resistance R of the 3rd resistance R A3 (polysilicon resistance)
A3With the relation of temperature T be:
Wherein
Be the resistance of the 3rd resistance R A3 under the absolute zero, α
1, α
2Be the constant relevant with technology; The 3rd resistance R A3 that is added in positive temperature coefficient (PTC) as reference voltage V ref produces second electric current I 2 of negative temperature coefficient when going up, promptly
Make the single order Fourier expansion and get I
2=I
2(T
1)+k
1(T-T
1), wherein
T1 is a zero temperature coefficient point, promptly corresponds to the zero temp shift point T2 among Fig. 6, and k1 is a coefficient of first order, and second electric current I 2 of negative temperature coefficient in the value of this point does
Therefore, the reference current Iref of the drain electrode generation of the 13 PMOS pipe MP13 is: I
Ref=m
1I
2(T
1)+m
2GT
1+ (m
1k
1+ m
2G) (T-T
1).
Fig. 7 is the simulation relation curve of reference current Iref and temperature T, and in-40 ℃～85 ℃ temperature range, under the 3.3V supply voltage, the variable quantity of reference current Iref is no more than 0.2uA, and temperature coefficient is 6.9ppm/ ℃.
The electric current of present embodiment adds with circuit 14 and has also utilized PMOSFET to utilize PMOSFET source gate voltage V
SGWith threshold voltage V
ThpThe mains voltage variations rate disappear mutually and reduce line-voltage regulation.Specifically, electric current adds with the 11 PMOS of circuit 14 pipe MP11 and the 12 PMOS pipe MP12 and is operated in dark linear zone, its grounded-grid, and source electrode and substrate short circuit are to avoid serving as a contrast inclined to one side effect.After said the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12 are operated in dark linear zone and are meant the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12 conducting (grounded-grid), its source-drain voltage V
DSVery little (＜V
GS-V
Thp), the PMOS pipe is equivalent to a resistance, and its resistance is used r
O11,12Expression.
The electric current that flows through the 13 PMOS pipe MP13 is reference current Iref, and the line-voltage regulation of reference current Iref is by V
SG13And V
Thp13Mains voltage variations rate decision, be zero for making 3.3V place line-voltage regulation, the 13 PMOS manages the V of MP13
SG13And V
Thp13Must cancel out each other in this place's mains voltage variations rate.
If the source electrode of the 13 PMOS pipe MP13 is the P point, MP13 has for the 13 PMOS pipe
Wherein, c
OxBe grid capacitance (constant relevant), μ with technology
pBe the mobility of charge carrier rate of PMOS pipe,
It is the breadth length ratio of the 13 PMOS pipe MP13; Order
Wherein, g
M9, g
M10, g
M13Be respectively the 9th, the tenth, the mutual conductance of the 13 PMOS pipe MP9, MP10, MP13, then
V wherein
PThe voltage of ordering for P; Cause
Obtain:
Wherein,
γ is body-effect coefficient (constant relevant with technology),
Be Fermi's electromotive force (constant relevant), V with semiconductor material
SD9,10It is the source-drain voltage of the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10.
Supply voltage adjustment rate is zero condition is
thereby determining the eleventh and twelfth PMOS transistor MP11 MP12 PMOS transistor width to length ratio:
Breadth length ratio through regulating the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12 can be improved the reference current line-voltage regulation; When the breadth length ratio that Fig. 8 shows the 11 PMOS pipe MP11 and the 12 PMOS pipe MP12 was got different value, reference current Iref was with the variation of supply voltage VDD.Under the 3.3V supply voltage, L is 0.6 μ m, works as W
12,13During＞30.8 μ m, rate of curve is less than zero, and promptly line-voltage regulation is less than zero; Work as W
12,13During＜30.8 μ m, rate of curve is greater than zero, and promptly line-voltage regulation is greater than zero; Work as W
12,13During=30.8 μ m, rate of curve is approximately equal to zero, and promptly line-voltage regulation is approximately equal to zero.
Fig. 9 is W
12,13During=30.8 μ m, the simulation relation curve that reference current Iref changes with supply voltage VDD.When supply voltage VDD was 3.3V, rate of curve was zero, and promptly line-voltage regulation is zero; Reference current Iref is 236.08 μ A; Supply voltage VDD is when 3V changes to 3.6V, and reference current Iref electric current has changed 1.5nA, and the reference current line-voltage regulation is 10.6ppm/V.
The first bias voltage PD among Fig. 4 is can operate as normal and the bias voltage that applies at the grid of NMOS pipe in order to ensure band-gap reference power circuit 12; The first bias voltage PD can preset according to the conditions such as manufacturing process of actual circuit structure, NMOS pipe, and it also can be provided by start-up circuit shown in Figure 4 11.
As shown in Figure 4; The reference power circuit of present embodiment also comprises start-up circuit 11; Be connected with band-gap reference power circuit 12; To said band-gap reference power circuit 12 the said first bias voltage PD is provided, can gets into normal operating conditions when system start-up (powering on) to guarantee band-gap reference power circuit 12.
Start-up circuit comprises: phase inverter 11a, the 14 PMOS pipe MP14, the 15 PMOS pipe MP15, the 16 PMOS pipe MP16, the 5th NMOS pipe MN5 and capacitor C.
The input end input offset signal PDB of phase inverter 11a, the inversion signal of output terminal output offset signal PDB, it has the first bias voltage PD, and phase inverter 11a is a kind of general CMOS phase inverter, comprises a PMOS pipe and a NMOS pipe.
The grid of the 14 PMOS pipe MP14 connects the input end (promptly importing offset signal PDB) of phase inverter 11a, and source electrode connects voltage source V DD, and drain electrode connects the drain electrode of the 15 PMOS pipe MP15.
The grid of the 15 PMOS pipe MP15 connects the output terminal of first operational amplifier A 1 of band gap reference power circuit 12, and source electrode connects voltage source V DD, and drain electrode connects the grid of the 16 PMOS pipe MP16.
The grid of the 16 PMOS pipe MP16 connects the drain electrode of the 15 PMOS pipe MP15, and source electrode connects voltage source V DD, and drain electrode connects the drain electrode of the 4th PMOS pipe MP4 of band gap reference power circuit 12.
The grid of the 5th NMOS pipe MN5 is imported the second bias voltage VN, and drain electrode connects the grid of the 16 PMOS pipe MP16, source ground.
First end of capacitor C connects the drain electrode of the 5th NMOS pipe MN5, the second end ground connection.
Those skilled in the art should understand; The offset signal PDB and the second bias voltage VN that offer start-up circuit 11 can preset according to the conditions such as manufacturing process of actual circuit structure and metal-oxide-semiconductor; Guarantee no longer to specify the first bias voltage PD of band-gap reference circuit 12 operate as normal with output at this.
The said reference power circuit has following characteristics:
Utilize the band-gap reference circuit of single order temperature compensation, through being that zero summit is moved and obtained the reference voltage with negative temperature coefficient feature to curvature;
Utilization comprises the voltage-current converter circuit of high gain operational amplifier, the reference voltage of negative temperature coefficient is added in the electric current that obtains negative temperature coefficient on the resistance of positive temperature coefficient (PTC);
Utilize the electric current of the negative temperature coefficient that electric current that electric current adds the positive temperature coefficient (PTC) that the band-gap reference circuit with a temperature compensation of circuit stack generates and voltage-current converter circuit change; Realize the curvature compensation of secondary temperature characterisitic thus; Thereby generate the reference current of low-temperature coefficient, improved the temperature of circuit and floated characteristic;
Utilized electric current add with circuit in the power source change rate of source gate voltage and threshold voltage of PMOS pipe offset and reduce line-voltage regulation, improved the PSRR characteristic of circuit;
Band-gap reference circuit provides the reference voltage and the PTAT electric current of single order temperature compensation simultaneously, has practiced thrift circuit layout area, has also simplified the complexity of circuit.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. a reference power circuit is characterized in that, comprising:
The band-gap reference power circuit produces first electric current of positive temperature coefficient (PTC) and the reference voltage of negative temperature coefficient;
Voltage-current converter circuit converts the reference voltage of said negative temperature coefficient in second electric current of negative temperature coefficient;
Electric current adds and circuit, and first electric current of the said positive temperature coefficient (PTC) that superposes and second electric current of negative temperature coefficient produce reference current.
2. reference power circuit according to claim 1; It is characterized in that; Said band-gap reference power circuit comprises: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, first operational amplifier, first resistance, second resistance, NMOS pipe, the 2nd NMOS pipe, PNP pipe, the 2nd PNP pipe and the 3rd PNP pipe
Said first, second source electrode with the 5th PMOS pipe connects voltage source; The source electrode of said the 3rd PMOS pipe is connected with the drain electrode of said PMOS pipe; The source electrode of said the 4th PMOS pipe is connected with the drain electrode of said the 2nd PMOS pipe; The source electrode of said the 6th PMOS pipe is connected with the drain electrode of said the 5th PMOS pipe, and said negative temperature coefficient voltage is exported in the drain electrode of said the 6th PMOS pipe;
The positive input terminal of said first operational amplifier is connected with the drain electrode of said the 3rd PMOS pipe; Negative input end is connected with the drain electrode of said the 4th PMOS pipe, and the output terminal of said first operational amplifier is connected with the grid of the 6th PMOS pipe with the said the first, second, third, fourth, the 5th;
First end of said first resistance is connected with the drain electrode of said the 3rd PMOS pipe, and first end of said second resistance is connected with the drain electrode of said the 6th PMOS pipe;
The drain electrode of said NMOS pipe is connected second end of said first resistance with the emitter of PNP pipe; The drain electrode of said the 2nd NMOS pipe is connected the drain electrode of said the 4th PMOS pipe with the emitter of the 2nd PNP pipe; The source ground of the base stage of said first and second PNP pipe, collector and said first and second NMOS pipe, the grid of said first and second NMOS pipe is imported first bias voltage;
The emitter of said the 3rd PNP pipe connects second end of said second resistance, base stage and grounded collector, and first electric current of said positive temperature coefficient (PTC) is the electric current that flows through said second resistance,
The ratio of the sectional area of said the 2nd PNP pipe and PNP pipe is set based on reference temperature, and said reference temperature is less than minimum operating temperature.
3. reference power circuit according to claim 2 is characterized in that, said voltage-current converter circuit comprises: second operational amplifier, the 7th PMOS pipe, the 8th PMOS pipe and the 3rd resistance,
The positive input terminal of said second operational amplifier connects first end of said the 3rd resistance; Negative input end connects the drain electrode of said the 6th PMOS pipe; Output terminal connects the grid of said the 7th PMOS pipe, the grid of said the 8th PMOS pipe and the second end ground connection of the 3rd resistance;
The source electrode of said the 7th PMOS pipe connects voltage source, and drain electrode connects the source electrode of said the 8th PMOS pipe, and the drain electrode of said the 8th PMOS pipe connects first end of said the 3rd resistance;
Second electric current of said negative temperature coefficient is the electric current that flows through said the 3rd resistance.
4. reference power circuit according to claim 3 is characterized in that, said the 3rd resistance is polysilicon resistance.
5. reference power circuit according to claim 3 is characterized in that, said electric current adds with circuit and comprises: the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe,
The grid of said the 9th PMOS pipe connects the output terminal of said second operational amplifier, and the grid of said the tenth PMOS pipe connects the output terminal of said first operational amplifier, and the said the 9th is connected voltage source with source electrode that the tenth PMOS manages;
The source electrode of said the 11 PMOS pipe connects the drain electrode of said the 9th PMOS pipe, and the source electrode of said the 12 PMOS pipe connects the drain electrode of said the tenth PMOS pipe, the grounded-grid of the said the 11 and 12 PMOS pipe, and drain electrode connects the source electrode of said the 13 PMOS pipe;
The grounded-grid of said the 13 PMOS pipe, drain electrode produces said reference current.
6. reference power circuit according to claim 5 is characterized in that, the said the 11 and 12 PMOS pipe is operated in dark linear zone, grounded-grid, substrate and the source shorted of the said the 11 and 12 PMOS pipe.
7. reference power circuit according to claim 5 is characterized in that, the substrate of said the 13 PMOS pipe connects voltage source.
8. reference power circuit according to claim 5; It is characterized in that; Said electric current adds with circuit and also comprises: the 3rd NMOS pipe and the 4th NMOS pipe; The drain electrode of said the 3rd NMOS pipe, grid and the grid of said the 4th NMOS pipe are connected the drain electrode of said the 13 PMOS pipe, the source ground of said third and fourth NMOS pipe, and the drain electrode of said the 4th NMOS pipe produces output current.
9. reference power circuit according to claim 2 is characterized in that, also comprises start-up circuit, is connected with said band-gap reference power circuit, to said band-gap reference power circuit said first bias voltage is provided.
10. reference power circuit according to claim 9 is characterized in that, said start-up circuit comprises: phase inverter, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 5th NMOS pipe and electric capacity,
Said phase inverter is exported said first bias voltage;
The grid of said the 14 PMOS pipe is connected with the input end of said phase inverter; The grid of said the 15 PMOS pipe is connected with the output terminal of said operational amplifier; The drain electrode of said the 16 PMOS pipe is connected with the negative input end of said operational amplifier, and said the 14, the 15 and the 16 PMOS pipe source electrode connects voltage source;
The said the 14 is connected with first end of said electric capacity with the drain electrode of the 15 PMOS pipe, the grid of the 16 PMOS pipe and the drain electrode of the 5th NMOS pipe; The source ground of second end of said electric capacity and said the 5th NMOS pipe, the grid of said the 5th NMOS pipe is imported second bias voltage.
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Effective date of registration: 20171129 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |