CN111552342A - Low-power-consumption reference voltage and reference current generating circuit - Google Patents
Low-power-consumption reference voltage and reference current generating circuit Download PDFInfo
- Publication number
- CN111552342A CN111552342A CN202010435167.6A CN202010435167A CN111552342A CN 111552342 A CN111552342 A CN 111552342A CN 202010435167 A CN202010435167 A CN 202010435167A CN 111552342 A CN111552342 A CN 111552342A
- Authority
- CN
- China
- Prior art keywords
- tube
- electrode
- pmos
- nmos
- pmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention discloses a low-power-consumption reference voltage and reference current generating circuit which comprises a starting circuit, a reference current generating module and a reference voltage generating module. Starting a circuit to inject current pulses to enable the circuit to be separated from a zero state; the reference voltage is used as an input signal of the reference current generation module, the temperature coefficient of an output resistor of a MOS tube working in a deep linear region in the reference current generation circuit is controlled to generate the reference current, and the reference current is used as the working current of the reference voltage generation circuit. The reference voltage generation module generates a reference voltage by linearly superimposing a portion having a negative temperature coefficient PN junction voltage and a voltage having a positive temperature coefficient. The invention can generate reference current and reference voltage at the same time, the consumed current is only 49.4-53.9nA when the circuit works normally, the reference voltage circuit and the reference current circuit with low power consumption are realized, and the defect that the power consumption of the traditional band gap reference circuit and the traditional low-power reference voltage source is increased along with the increase of temperature is simultaneously solved.
Description
Technical Field
The invention belongs to the technical field of analog circuits, and relates to a low-power-consumption reference voltage and reference current generating circuit.
Background
The reference voltage and the reference current are basic module units in an analog circuit design and a digital-analog mixed design, and the power consumption is very meaningful to reduce. In addition, the total current of the traditional band-gap reference voltage source and the existing low-power consumption reference voltage source increases along with the increase of the temperature. At present, there are two main schemes for simultaneously generating a reference voltage and a reference current: first, a reference voltage is generated and then a current circuit is converted by a voltage with a resistor, so that a large resistor is required for reducing power consumption, and the chip area is increased. Meanwhile, the voltage conversion current circuit consumes a part of power consumption; the second is to generate the reference voltage and the reference current completely independently, which increases the number of current branches consumed by the circuit. In the prior art, no circuit which has low power consumption and simultaneously generates a reference voltage and a reference current exists.
Disclosure of Invention
The invention provides a low-power-consumption reference voltage and reference current generating circuit, which not only can solve the problem that the traditional reference voltage and reference current generating circuit needs more power-consumption branches and larger chip area, but also overcomes the defect that the total current of the traditional band-gap reference voltage source and the traditional low-power-consumption reference voltage source is increased along with the increase of the temperature.
In order to achieve the purpose, the invention provides the following technical scheme:
a low-power consumption reference voltage and reference current generating circuit comprises a starting circuit, a reference current generating module and a reference voltage generating module; the starting circuit is connected with the reference current generating module to generate current pulse to be separated from a zero state; the reference current generation module is connected with the reference voltage generation module and provides working current for the reference voltage generation module; the output reference voltage of the voltage generation module is used as an input signal of the reference current generation module, and the MOS resistance temperature coefficient in the module is controlled so as to generate reference current;
the starting circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a second PMOS tube, a third NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a ninth NMOS tube; the grid electrode of the first PMOS tube is connected with a starting switch START, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with a node START 0; the grid electrode of the first NMOS tube is connected with a START switch START, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with a node START 0; the grid electrode of the second NMOS tube is connected with a node START0, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube; the source level of the second PMOS tube is connected with a power supply; the source electrode and the grid electrode of the third NMOS tube are grounded; the grid electrode of the third PMOS tube is connected with a START switch START, and the source electrode of the third PMOS tube is connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is connected with a START switch START, and the source electrode of the fourth NMOS tube is grounded; the gates of the fifth NMOS transistor and the ninth NMOS transistor are both connected with the node START0, and the sources are both grounded;
the reference current generating module comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth PMOS tube and a tenth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the grid electrode and the drain electrode of the sixth PMOS tube, the source electrode of the eighth PMOS tube and the grid electrode of the ninth PMOS tube, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the seventh PMOS tube; the source electrode of the sixth PMOS tube is connected with a power supply; the grid electrode of the seventh PMOS tube is connected with the grid electrode and the drain electrode of the eighth PMOS tube, the drain electrode of the seventh NMOS tube, the drain electrode of the ninth NMOS tube and the grid electrode of the tenth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the seventh NMOS tube and the grid electrode and the drain electrode of the sixth NMOS tube; the source electrode of the sixth NMOS tube is grounded; the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube; the grid electrode of the eighth NMOS tube is connected with an output reference voltage VREF, and the source electrode of the eighth NMOS tube is grounded; the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube; the drain electrode of the tenth POMS tube is connected with an output reference current IREF;
the reference voltage generating module comprises a voltage dividing circuit and a positive temperature coefficient voltage generating circuit; the voltage dividing circuit obtains 2/3 times of PN junction voltage, and the output of the voltage dividing circuit is used as an input signal of the positive temperature coefficient voltage generating module to obtain a reference voltage approximate to a zero temperature coefficient; the voltage division circuit comprises an eleventh PMOS (P-channel metal oxide semiconductor) tube, a twelfth PMOS tube, a first PNP (plug-and-play) tube, a tenth NMOS (N-channel metal oxide semiconductor) tube, an eleventh NMOS tube and a twelfth NMOS tube; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the eleventh PMOS tube is connected with the power supply, and the drain electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the grid electrode of the tenth NMOS tube and the emitter electrode of the first PNP tube; the base electrode and the collector electrode of the first PNP tube are grounded; the drain electrode of the tenth NMOS tube is connected with the power supply, and the source electrode of the tenth NMOS tube is connected with the grid electrode and the drain electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the grid electrode and the drain electrode of the twelfth NMOS tube; the source electrode of the twelfth NMOS tube is grounded; the positive temperature coefficient voltage generating circuit comprises a plurality of sub-circuits connected in series; each sub-circuit comprises a thirteenth PMOS (P-channel metal oxide semiconductor) tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a thirteenth NMOS (N-channel metal oxide semiconductor) tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube; the source electrode of the thirteenth PMOS tube is connected with the power supply, the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube, and the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the eleventh PMOS tube; the drain electrode of the fourteenth PMOS tube is connected with the source electrode of the fifteenth PMOS tube and the source electrode of the sixteenth PMOS tube, and the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the twelfth PMOS tube; the drain electrode of the fifteenth PMOS tube is connected with the grid electrode of the fourteenth NMOS tube and the grid electrode and the drain electrode of the thirteenth NMOS tube; the grid electrode and the drain electrode of the sixteenth PMOS tube are connected with the drain electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube is connected with the grid electrode of the sixteenth NMOS tube and the grid electrode and the drain electrode of the fifteenth NMOS tube; the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube; the source electrodes of the fifteenth NMOS tube and the sixteenth NMOS tube are grounded; the grid electrode of a fifteenth PMOS tube in the first sub-circuit is connected with the source electrode of a tenth NMOS tube in the voltage division circuit, the grid electrodes of the fifteenth PMOS tubes of all the sub-circuits except the first sub-circuit are connected with the grid electrode of a sixteenth PMOS tube in the previous sub-circuit, and the grid electrode of the sixteenth PMOS tube in the last sub-circuit is used for outputting reference voltage VREF.
Furthermore, in the reference current generation module and the reference voltage generation module, except for the eighth NMOS transistor, the other NMOS transistors and PMOS transistors all work in the sub-threshold region; the eighth NMOS transistor operates in the deep linear region.
Furthermore, the reference current is used as the working current of the reference voltage generating circuit; the reference voltage is used as an input signal of the reference current module, and the temperature coefficient of an output resistor of an eighth NMOS tube used as an MOS resistor in the reference current module is controlled to form a closed loop structure.
Furthermore, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor have the same size.
Further, the gate voltage of the fifteenth PMOS transistor is 2/3 of the difference between the emitter and the base of the first PNP transistor.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the defect that the power consumption of a traditional band-gap reference voltage source and an existing low-power-consumption reference voltage source is increased along with the increase of temperature is overcome, and the total power consumption of the circuit is basically unchanged within a wide temperature range.
2. The single circuit simultaneously generates the reference voltage and the reference current, reduces the number of circuit branches with the reference voltage and the reference current, and reduces the power consumption of the chip.
Drawings
Fig. 1 is a circuit diagram of a low power consumption reference voltage and reference current generating circuit provided in the present invention.
FIG. 2 is a circuit diagram of a reference current generating module according to the present invention.
Fig. 3 is a circuit diagram of the voltage divider circuit of the present invention.
FIG. 4 is a circuit diagram of a sub-circuit of the PTC voltage generating circuit according to the present invention.
Detailed Description
The technical solutions provided by the present invention will be described in detail below with reference to specific examples, and it should be understood that the following specific embodiments are only illustrative of the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1, the reference voltage and reference current generating circuit with low power consumption provided by the present invention includes a start circuit, a reference current generating module and a reference voltage generating module. The starting circuit is connected with the reference current generating module to generate current pulse to be separated from a zero state; the reference current generation module is connected with the reference voltage generation module and provides working current for the reference voltage generation module; the output reference voltage of the voltage generation module is used as an input signal of the reference current generation module, and the MOS resistance temperature coefficient in the module is controlled so as to generate the reference current.
The starting circuit comprises a first PMOS tube MP1, a first NMOS tube MN1, a second NMOS tube MN2, a second PMOS tube MP2, a third NMOS tube MN3, a third PMOS tube MP3, a fourth PMOS tube MP4, a fourth NMOS tube MN4, a fifth NMOS tube MN5 and a ninth NMOS tube MN 9; the grid electrode of the first PMOS pipe MP1 is connected with the starting switch START, the source electrode of the first PMOS pipe MP1 is connected with the power supply, and the drain electrode of the first PMOS pipe MP1 is connected with the node START 0; the gate of the first NMOS transistor MN1 is connected to the START switch START, the source thereof is grounded, and the drain thereof is connected to the node START 0; the gate of the second NMOS transistor MN2 is connected to the node START0, the source thereof is grounded and the drain thereof is connected to the drain of the second PMOS transistor MP2, the drain of the third NMOS transistor MN3 and the gate of the fourth PMOS transistor MP 4; the source of the second PMOS pipe MP2 is connected with the power supply; the source and the gate of the third NMOS transistor MN3 are grounded; the grid electrode of the third PMOS pipe MP3 is connected with the starting switch START, and the source electrode of the third PMOS pipe MP3 is connected with the power supply; the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN 4; the gate of the fourth NMOS transistor MN4 is connected to the START switch START, and the source thereof is grounded; the gates of the fifth NMOS transistor MN5 and the ninth NMOS transistor MN9 are both connected to the node START0, and the sources are both connected to ground.
The circuit diagram of the reference current generating module is shown in fig. 2, and includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP 10; the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrode of the second PMOS tube MP2, the drain electrode of the third PMOS tube MP3, the source electrode of the fourth PMOS tube MP4, the grid electrode and the drain electrode of the sixth PMOS tube MP6, the source electrode of the eighth PMOS tube MP8 and the grid electrode of the ninth PMOS tube MP9, the source electrode of the fifth PMOS tube MP5 is connected with the power supply, and the drain electrode is connected with the source electrode of the seventh PMOS tube MP 7; the source electrode of the sixth PMOS pipe MP6 is connected with the power supply; the grid electrode of the seventh PMOS tube MP7 is connected with the grid electrode and the drain electrode of the eighth PMOS tube MP8, the drain electrode of the seventh NMOS tube MN7, the drain electrode of the ninth NMOS tube MN9 and the grid electrode of the tenth PMOS tube MP 10; the drain electrode of the seventh PMOS transistor MP7 is connected with the drain electrode of the fifth NMOS transistor MN5, the gate electrode of the seventh NMOS transistor MN7 and the gate electrode and the drain electrode of the sixth NMOS transistor MN 6; the source electrode of the sixth NMOS transistor MN6 is grounded; the source electrode of the seventh NMOS transistor MN7 is connected with the drain electrode of the eighth NMOS transistor MN 8; the gate of the eighth NMOS transistor MN8 is connected to the output reference voltage VREF, and the source thereof is grounded; the source electrode of the ninth PMOS tube MP9 is connected with the power supply, and the drain electrode of the ninth PMOS tube MP9 is connected with the source electrode of the tenth PMOS tube MP 10; the drain of the tenth POMS tube MP10 is connected to the output reference current IREF.
The reference voltage generation module comprises a voltage division circuit and a positive temperature coefficient voltage generation circuit. The voltage divider circuit obtains 2/3 times of PN junction voltage, and the output of the voltage divider circuit is used as the input signal of the positive temperature coefficient voltage generation module to obtain the reference voltage with the approximate zero temperature coefficient. As shown in fig. 3, the voltage divider circuit includes an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a first PNP transistor Q1, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN 12; the gate of the eleventh PMOS transistor MP11 is connected to the gate of the ninth PMOS transistor MP9, the source thereof is connected to the power supply, and the drain thereof is connected to the source of the twelfth PMOS transistor MP 12; the grid of the twelfth PMOS tube MP12 is connected with the grid of the tenth PMOS tube MP10, and the drain is connected with the grid of the tenth NMOS tube MN10 and the emitter of the first PNP tube Q1; the base electrode and the collector electrode of the first PNP tube Q1 are grounded; the drain electrode of the tenth NMOS tube MN10 is connected with the power supply, and the source electrode of the tenth NMOS tube MN10 is connected with the gate electrode and the drain electrode of the eleventh NMOS tube MN 11; the source of the eleventh NMOS transistor MN11 is connected to the gate and the drain of the twelfth NMOS transistor MN 12; the source of the twelfth NMOS transistor MN12 is grounded. The positive temperature coefficient voltage generating circuit comprises a plurality of sub-circuits which are connected in series; in the present embodiment, the ptc generating module comprises four sub-circuits. Each sub-circuit comprises a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube. The thirteenth PMOS transistor corresponds to the transistor MP13, the transistor MP17, the transistor MP21, and the transistor MP25 in fig. 1, the fourteenth PMOS transistor corresponds to the transistor MP25, and the transistor MP25 in fig. 1, the fifteenth PMOS transistor corresponds to the transistor MP25, and the transistor MP25 in fig. 1, the sixteenth PMOS transistor corresponds to the transistor MP25, and the transistor MP25 in fig. 1, the thirteenth NMOS transistor corresponds to the transistor MN25, and the transistor MN25 in fig. 1, the fourteenth NMOS transistor corresponds to the transistor MN25, and the transistor MN25 in fig. 1, and the fifteenth NMOS transistor MN25, the transistor MN25 in fig. 1. Taking the first sub-circuit as an example, as shown in fig. 4, the sub-circuit includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN 16. In each sub-circuit, the source electrode of the thirteenth PMOS tube is connected with the power supply, the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube, and the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the eleventh PMOS tube MP 11; the drain electrode of the fourteenth PMOS tube is connected with the source electrode of the fifteenth PMOS tube and the source electrode of the sixteenth PMOS tube, and the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the twelfth PMOS tube MP 12; the drain electrode of the fifteenth PMOS tube is connected with the grid electrode of the fourteenth NMOS tube and the grid electrode and the drain electrode of the thirteenth NMOS tube; the grid electrode and the drain electrode of the sixteenth PMOS tube are connected with the drain electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube is connected with the grid electrode of the sixteenth NMOS tube and the grid electrode and the drain electrode of the fifteenth NMOS tube; the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube; the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are both grounded. The gate of the fifteenth PMOS transistor in the first sub-circuit is connected to the source of the tenth NMOS transistor MN10 in the voltage divider circuit, i.e., the gate of the fifteenth PMOS transistor MP15 is connected to the source of the tenth NMOS transistor MN10, the gates of the fifteenth transistors in each sub-circuit except the first sub-circuit are connected to the gate of the sixteenth PMOS transistor in the previous sub-circuit, and the gate of the sixteenth PMOS transistor in the last sub-circuit is the output reference voltage VREF, i.e., the gate of the twenty-eighth PMOS transistor MP28 is connected to VREF.
In the reference current generation module and the reference voltage generation module, except for the eighth NMOS transistor MN8, the remaining NMOS transistors and PMOS transistors all operate in the sub-threshold region. In the reference current generation module, as shown in fig. 2, the eighth NMOS transistor MN8 operates in a deep linear region as a MOS resistor having a temperature coefficient controlled by a gate voltage; the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 working in the subthreshold region generate positive temperature coefficient voltage, and the voltage and the MOS resistor coact to generate reference current; the operation of the tube MP5-MP10 in the subthreshold region is required for low power consumption. The NMOS tube and the PMOS tube in the voltage division circuit of the reference voltage generation module work in a subthreshold region due to the requirement of low power consumption. The differential pair transistors of the sub-circuit of the positive temperature coefficient voltage generating circuit should work in a sub-threshold region to generate positive temperature coefficient voltage, different positive temperature coefficients can be obtained by setting the ratio of the width to the length of the differential pair transistors, and the rest NMOS transistors and the PMOS transistors of the sub-circuit work in the sub-threshold region due to the requirement of low power consumption. Taking the first sub-circuit as an example, as shown in fig. 4, the fifteenth NMOS transistor MP15 and the sixteenth NMOS transistor MP16 operate in the sub-threshold region, and by increasing the ratio of the width-to-length ratios of the transistor MP16 and the transistor MP15, the positive temperature coefficient of the voltage difference between the gate voltage of the transistor MP16 and the gate voltage of the transistor MP15 is larger, and the transistors MP13-MP14 and MN13-MP16 operate in the sub-threshold region.
The reference current is used as the working current of the reference voltage generating circuit; the reference voltage is used as an input signal of the reference current module, and the temperature coefficient of an eighth NMOS transistor MN8 which is used as a MOS resistor in the reference current module is controlled to form a closed loop structure.
In fig. 1, the dimensions of the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12 are the same, so the source terminal voltage of the tenth NMOS transistor MN10 is 2/3 of the voltage difference between the emitter and the base of the first PNP transistor Q1, and the voltage is used as the input signal of the positive temperature coefficient voltage generating circuit, that is, the gate of the fifteenth PMOS transistor is connected to the source of the tenth NMOS transistor, so that the positive and negative temperature coefficients are cancelled, and a 2/3 bandgap reference voltage, that is, VREF is obtained, and at this time, VREF is used as the gate voltage of the eighth NMOS transistor MN8 to obtain the reference current, that is, IREF.
The differential pair transistors in the sub-circuits of the positive temperature coefficient voltage generating circuit are PMOS transistors, and taking the first sub-circuit as an example, as shown in fig. 4, the fifteenth NMOS transistor MN15 and the sixteenth NMOS transistor MN16 are PMOS transistors. The output reference voltage VREF is 2/3 times of the bandgap reference voltage 1.2V, so the gate voltage of the differential pair transistor in the sub-circuit of the positive temperature coefficient voltage generating circuit is less than or equal to 800mV, and the differential pair transistor should be a PMOS transistor.
The basic principle of the starting circuit is as follows: when the START signal is at a low level, the fourth NMOS transistor MN4 is turned off, the second NMOS transistor MN2, the third PMOS transistor MP3, the fifth NMOS transistor MN5, and the ninth NMOS transistor MN9 are turned on, the gate of the fourth PMOS transistor MP4 is pulled down to a low level, the current of each branch is zero, and the circuit is turned off. When the START signal changes from low level to high level, the third PMOS transistor MP3, the fifth NMOS transistor MN5, and the ninth NMOS transistor MN9 are turned off, and the fourth NMOS transistor is turned on, so that the current of each branch of the reference current generating module and the reference voltage generating module rapidly rises, the circuit is out of zero state, the second NMOS transistor MN2 is turned off, the gate voltage of MP4 rapidly rises to the power supply voltage, the START circuit is turned off, and the reference current and reference voltage generating circuit reaches a steady state according to its inherent feedback mechanism.
The reference current generation module provides working current for the reference voltage generation module, voltage difference between an emitter and a base of the PNP 2/3 is obtained through an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a first PNP tube Q1, a tenth NMOS tube MN10, an eleventh NMOS tube MN11 and a twelfth NMOS tube, the voltage has a negative temperature coefficient, positive temperature coefficient voltage is generated through MP13-MP28 and MN13-MN28, and the reference voltage is obtained through linear superposition of the two voltages; the reference voltage is used as the gate voltage of the eighth NMOS transistor, the temperature coefficient of the output resistor of the eighth NMOS transistor MN8 is controlled, meanwhile, the source-drain voltage of the eighth NMOS transistor MN8 is the difference between the gate-source voltages of the sixth NMOS transistor and the seventh NMOS transistor, and the positive temperature coefficient is achieved, so that the reference current is generated. Based on the method, the reference voltage and the reference current can be generated simultaneously, the overall power consumption is low, and the temperature does not change basically. The problem that more power consumption branches and larger chip area are needed in the traditional generation of reference voltage and reference circuit is solved, the defect that the total current of the traditional band-gap reference voltage source and the existing low-power consumption reference voltage source is increased along with the increase of temperature is overcome, and the working current can be reduced by reducing the width-to-length ratio of the eighth NMOS transistor MN8 and the width-to-length ratio of the seventh NMOS transistor MN7 to the sixth NMOS transistor MN 6. In the temperature range of-40 to 100 ℃, the circuit of the invention has the total current variation range of 49.4 to 53.9nA and can work normally. Therefore, the whole circuit has the characteristic of low power consumption.
The technical means disclosed in the invention scheme are not limited to the technical means disclosed in the above embodiments, but also include the technical scheme formed by any combination of the above technical features. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and such improvements and modifications are also considered to be within the scope of the present invention.
Claims (5)
1. A low power reference voltage and reference current generating circuit, characterized by: the device comprises a starting circuit, a reference current generating module and a reference voltage generating module; the starting circuit is connected with the reference current generating module to generate current pulse to be separated from a zero state; the reference current generation module is connected with the reference voltage generation module and provides working current for the reference voltage generation module; the output reference voltage of the voltage generation module is used as an input signal of the reference current generation module, and the MOS resistance temperature coefficient in the module is controlled so as to generate reference current;
the starting circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a second PMOS tube, a third NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a ninth NMOS tube; the grid electrode of the first PMOS tube is connected with a starting switch START, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with a node START 0; the grid electrode of the first NMOS tube is connected with a START switch START, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with a node START 0; the grid electrode of the second NMOS tube is connected with a node START0, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube; the source level of the second PMOS tube is connected with a power supply; the source electrode and the grid electrode of the third NMOS tube are grounded; the grid electrode of the third PMOS tube is connected with a START switch START, and the source electrode of the third PMOS tube is connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is connected with a START switch START, and the source electrode of the fourth NMOS tube is grounded; the gates of the fifth NMOS transistor and the ninth NMOS transistor are both connected with the node START0, and the sources are both grounded;
the reference current generating module comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth PMOS tube and a tenth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the grid electrode and the drain electrode of the sixth PMOS tube, the source electrode of the eighth PMOS tube and the grid electrode of the ninth PMOS tube, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the seventh PMOS tube; the source electrode of the sixth PMOS tube is connected with a power supply; the grid electrode of the seventh PMOS tube is connected with the grid electrode and the drain electrode of the eighth PMOS tube, the drain electrode of the seventh NMOS tube, the drain electrode of the ninth NMOS tube and the grid electrode of the tenth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the seventh NMOS tube and the grid electrode and the drain electrode of the sixth NMOS tube; the source electrode of the sixth NMOS tube is grounded; the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube; the grid electrode of the eighth NMOS tube is connected with an output reference voltage VREF, and the source electrode of the eighth NMOS tube is grounded; the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube; the drain electrode of the tenth POMS tube is connected with an output reference current IREF;
the reference voltage generating module comprises a voltage dividing circuit and a positive temperature coefficient voltage generating circuit; the voltage dividing circuit obtains 2/3 times of PN junction voltage, and the output of the voltage dividing circuit is used as an input signal of the positive temperature coefficient voltage generating module to obtain a reference voltage approximate to a zero temperature coefficient; the voltage division circuit comprises an eleventh PMOS (P-channel metal oxide semiconductor) tube, a twelfth PMOS tube, a first PNP (plug-and-play) tube, a tenth NMOS (N-channel metal oxide semiconductor) tube, an eleventh NMOS tube and a twelfth NMOS tube; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the eleventh PMOS tube is connected with the power supply, and the drain electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the grid electrode of the tenth NMOS tube and the emitter electrode of the first PNP tube; the base electrode and the collector electrode of the first PNP tube are grounded; the drain electrode of the tenth NMOS tube is connected with the power supply, and the source electrode of the tenth NMOS tube is connected with the grid electrode and the drain electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the grid electrode and the drain electrode of the twelfth NMOS tube; the source electrode of the twelfth NMOS tube is grounded; the positive temperature coefficient voltage generating circuit comprises a plurality of sub-circuits connected in series; each sub-circuit comprises a thirteenth PMOS (P-channel metal oxide semiconductor) tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a thirteenth NMOS (N-channel metal oxide semiconductor) tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube; the source electrode of the thirteenth PMOS tube is connected with the power supply, the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube, and the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the eleventh PMOS tube; the drain electrode of the fourteenth PMOS tube is connected with the source electrode of the fifteenth PMOS tube and the source electrode of the sixteenth PMOS tube, and the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the twelfth PMOS tube; the drain electrode of the fifteenth PMOS tube is connected with the grid electrode of the fourteenth NMOS tube and the grid electrode and the drain electrode of the thirteenth NMOS tube; the grid electrode and the drain electrode of the sixteenth PMOS tube are connected with the drain electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube is connected with the grid electrode of the sixteenth NMOS tube and the grid electrode and the drain electrode of the fifteenth NMOS tube; the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube; the source electrodes of the fifteenth NMOS tube and the sixteenth NMOS tube are grounded; the grid electrode of a fifteenth PMOS tube in the first sub-circuit is connected with the source electrode of a tenth NMOS tube in the voltage division circuit, the grid electrodes of the fifteenth PMOS tubes of all the sub-circuits except the first sub-circuit are connected with the grid electrode of a sixteenth PMOS tube in the previous sub-circuit, and the grid electrode of the sixteenth PMOS tube in the last sub-circuit is used for outputting reference voltage VREF.
2. The low-power reference voltage and reference current generating circuit according to claim 1, wherein: in the reference current generation module and the reference voltage generation module, except the eighth NMOS tube, the rest NMOS tubes and PMOS tubes work in a sub-threshold region; the eighth NMOS transistor operates in the deep linear region.
3. The low-power reference voltage and reference current generating circuit according to claim 1, wherein: the reference current is used as the working current of the reference voltage generating circuit; the reference voltage is used as an input signal of the reference current module, and the temperature coefficient of an output resistor of an eighth NMOS tube used as an MOS resistor in the reference current module is controlled to form a closed loop structure.
4. The low-power reference voltage and reference current generating circuit according to claim 1, wherein: the tenth NMOS tube, the eleventh NMOS tube and the twelfth NMOS tube have the same size.
5. The low-power reference voltage and reference current generating circuit according to claim 1, wherein: the gate voltage of the fifteenth PMOS transistor is 2/3 of the difference between the emitter and the base of the first PNP transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010435167.6A CN111552342A (en) | 2020-05-21 | 2020-05-21 | Low-power-consumption reference voltage and reference current generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010435167.6A CN111552342A (en) | 2020-05-21 | 2020-05-21 | Low-power-consumption reference voltage and reference current generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111552342A true CN111552342A (en) | 2020-08-18 |
Family
ID=72008402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010435167.6A Pending CN111552342A (en) | 2020-05-21 | 2020-05-21 | Low-power-consumption reference voltage and reference current generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111552342A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112286337A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption bandgap circuit for MCU and implementation method thereof |
| CN112489712A (en) * | 2020-12-21 | 2021-03-12 | 中国电子科技集团公司第四十七研究所 | EEPROM programming period control circuit |
| CN114281142A (en) * | 2021-12-23 | 2022-04-05 | 江苏稻源科技集团有限公司 | High transient response LDO (low dropout regulator) without off-chip capacitor |
| CN114740938A (en) * | 2022-04-18 | 2022-07-12 | 西安航天民芯科技有限公司 | Reference circuit and reference voltage applied to Sigma-Delta ADC |
| WO2024036743A1 (en) * | 2022-08-15 | 2024-02-22 | 长鑫存储技术有限公司 | Power supply circuit and chip |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2884287Y (en) * | 2005-11-16 | 2007-03-28 | 上海贝岭股份有限公司 | Circuit for starting current-source or valtage-source |
| CN101840242A (en) * | 2010-05-21 | 2010-09-22 | 广州市广晟微电子有限公司 | CMOS low power consumption voltage current offset start-up circuit |
| CN102541149A (en) * | 2010-12-31 | 2012-07-04 | 无锡华润上华半导体有限公司 | Reference power circuit |
| CN103309391A (en) * | 2013-05-24 | 2013-09-18 | 福州大学 | Reference current and reference voltage generation circuit with high power-supply rejection ratio and low power consumption |
| KR20140019497A (en) * | 2012-08-06 | 2014-02-17 | (주)샌버드 | Start-up circuit |
| CN104950971A (en) * | 2015-06-11 | 2015-09-30 | 中国人民解放军国防科学技术大学 | Low-power-consumption sub-threshold type CMOS band gap reference voltage circuit |
| CN205375264U (en) * | 2016-01-19 | 2016-07-06 | 桂林电子科技大学 | CMOS reference voltage source of no bipolar transistor |
| WO2017165696A1 (en) * | 2016-03-23 | 2017-09-28 | Avnera Corporation | Wide supply range precision startup current source |
| CN107368143A (en) * | 2017-08-29 | 2017-11-21 | 电子科技大学 | A kind of reference voltage source of low-power consumption |
| CN107390757A (en) * | 2017-08-03 | 2017-11-24 | 电子科技大学 | A kind of low-power consumption Low Drift Temperature CMOS subthreshold value reference circuits |
| CN107402592A (en) * | 2016-12-01 | 2017-11-28 | 上海韦玏微电子有限公司 | Start-up circuit |
| JP2019057204A (en) * | 2017-09-22 | 2019-04-11 | 新日本無線株式会社 | Method of detecting start circuit fault |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
-
2020
- 2020-05-21 CN CN202010435167.6A patent/CN111552342A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2884287Y (en) * | 2005-11-16 | 2007-03-28 | 上海贝岭股份有限公司 | Circuit for starting current-source or valtage-source |
| CN101840242A (en) * | 2010-05-21 | 2010-09-22 | 广州市广晟微电子有限公司 | CMOS low power consumption voltage current offset start-up circuit |
| CN102541149A (en) * | 2010-12-31 | 2012-07-04 | 无锡华润上华半导体有限公司 | Reference power circuit |
| KR20140019497A (en) * | 2012-08-06 | 2014-02-17 | (주)샌버드 | Start-up circuit |
| CN103309391A (en) * | 2013-05-24 | 2013-09-18 | 福州大学 | Reference current and reference voltage generation circuit with high power-supply rejection ratio and low power consumption |
| CN104950971A (en) * | 2015-06-11 | 2015-09-30 | 中国人民解放军国防科学技术大学 | Low-power-consumption sub-threshold type CMOS band gap reference voltage circuit |
| CN205375264U (en) * | 2016-01-19 | 2016-07-06 | 桂林电子科技大学 | CMOS reference voltage source of no bipolar transistor |
| WO2017165696A1 (en) * | 2016-03-23 | 2017-09-28 | Avnera Corporation | Wide supply range precision startup current source |
| CN107402592A (en) * | 2016-12-01 | 2017-11-28 | 上海韦玏微电子有限公司 | Start-up circuit |
| CN107390757A (en) * | 2017-08-03 | 2017-11-24 | 电子科技大学 | A kind of low-power consumption Low Drift Temperature CMOS subthreshold value reference circuits |
| CN107368143A (en) * | 2017-08-29 | 2017-11-21 | 电子科技大学 | A kind of reference voltage source of low-power consumption |
| JP2019057204A (en) * | 2017-09-22 | 2019-04-11 | 新日本無線株式会社 | Method of detecting start circuit fault |
| CN110502056A (en) * | 2019-08-22 | 2019-11-26 | 成都飞机工业（集团）有限责任公司 | A kind of threshold voltage reference circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112286337A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption bandgap circuit for MCU and implementation method thereof |
| CN112489712A (en) * | 2020-12-21 | 2021-03-12 | 中国电子科技集团公司第四十七研究所 | EEPROM programming period control circuit |
| CN112489712B (en) * | 2020-12-21 | 2023-07-18 | 中国电子科技集团公司第四十七研究所 | EEPROM programming cycle control circuit |
| CN114281142A (en) * | 2021-12-23 | 2022-04-05 | 江苏稻源科技集团有限公司 | High transient response LDO (low dropout regulator) without off-chip capacitor |
| CN114740938A (en) * | 2022-04-18 | 2022-07-12 | 西安航天民芯科技有限公司 | Reference circuit and reference voltage applied to Sigma-Delta ADC |
| CN114740938B (en) * | 2022-04-18 | 2023-11-10 | 西安航天民芯科技有限公司 | Reference circuit and reference voltage ware applied to Sigma-Delta ADC |
| WO2024036743A1 (en) * | 2022-08-15 | 2024-02-22 | 长鑫存储技术有限公司 | Power supply circuit and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111552342A (en) | Low-power-consumption reference voltage and reference current generating circuit | |
| KR100400304B1 (en) | Current mirror type bandgap reference voltage generator | |
| CN103389766B (en) | Sub-threshold non-bandgap reference voltage source | |
| US8786324B1 (en) | Mixed voltage driving circuit | |
| CN102495661A (en) | Band-gap reference circuit based on two threshold voltage metal oxide semiconductor (MOS) devices | |
| CN106549639B (en) | Gain self-adaptive error amplifier | |
| CN109710017B (en) | Low-dropout linear voltage regulator system | |
| CN111190453A (en) | High power supply rejection ratio reference circuit | |
| CN114200994B (en) | Low dropout linear regulator and laser ranging circuit | |
| CN113050743B (en) | Current reference circuit capable of outputting multiple temperature coefficients | |
| CN108536210B (en) | Smooth temperature compensation band gap reference source circuit | |
| CN113703510B (en) | Band gap reference circuit with low power consumption | |
| CN111781983A (en) | High power supply rejection ratio sub-threshold MOSFET compensation band-gap reference voltage circuit | |
| CN111381625B (en) | Reference source circuit | |
| CN111752325A (en) | High-precision linear voltage stabilizing circuit | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN115437446B (en) | High-precision curvature compensation band gap reference circuit | |
| CN211207200U (en) | High power supply rejection ratio reference circuit | |
| CN212484194U (en) | CMOS voltage reference source | |
| CN111722668A (en) | LDO circuit | |
| CN110568902B (en) | Reference voltage source circuit | |
| CN110365326B (en) | Anti-irradiation over-temperature protection circuit for satellite | |
| CN212341758U (en) | LDO circuit | |
| CN218332402U (en) | Band gap reference source circuit and electronic equipment | |
| CN215264537U (en) | VREGVoltage and reference voltage generating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200818 |