CN112286337A - Low-power-consumption bandgap circuit for MCU and implementation method thereof - Google Patents
Low-power-consumption bandgap circuit for MCU and implementation method thereof Download PDFInfo
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- CN112286337A CN112286337A CN202011193431.6A CN202011193431A CN112286337A CN 112286337 A CN112286337 A CN 112286337A CN 202011193431 A CN202011193431 A CN 202011193431A CN 112286337 A CN112286337 A CN 112286337A
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- G06F1/26—Power supply means, e.g. regulation thereof
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Abstract
The embodiment of the application discloses a low-power-consumption bandgap circuit for an MCU (microprogrammed control Unit) and an implementation method thereof; the method comprises the following steps: the temperature coefficient reference current generating circuit, the reference voltage generating circuit and the reference current generating circuit; the temperature coefficient reference current generating circuit comprises a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit; the reference voltage generating circuit comprises a fourth PMOS tube, a fifth PMOS tube, a third resistor and a zero temperature coefficient reference voltage output end; the reference current generating circuit comprises a sixth PMOS tube, a seventh PMOS tube and a zero temperature coefficient reference current output end; according to the embodiment of the application, the reference current is obtained by inputting the positive temperature coefficient reference current and the negative temperature coefficient reference current, the corresponding reference voltage is obtained, and the reference voltage and the reference current in the low power consumption mode are provided for the MCU; through the bandgap circuit with a simple structure, low power consumption is realized, the consumption of a battery is reduced, high-performance output voltage and current are provided, and the optimal performance-power consumption ratio is realized.
Description
Technical Field
The embodiment of the application relates to the technical field of bandgap circuits, in particular to a low-power-consumption bandgap circuit for an MCU (microprogrammed control unit) and an implementation method thereof.
Background
The MCU, i.e., a micro control unit, also called a single-chip microcomputer or a single-chip microcomputer, properly reduces the frequency and specification of the cpu, and integrates peripheral interfaces such as a memory, a counter, a USB, a UART, a PLC, a DMA, a GPIO, etc., a detection circuit such as an analog-to-digital converter, a comparator, an operational amplifier, etc., and even an LCD driving circuit on a single chip to form a chip-level computer, which is controlled in different combinations for different applications.
In recent years, with the great development of the internet of things and artificial intelligence, the difference between consumer electronics and computers is smaller and smaller, and the functional requirements of consumer electronics are higher and the design is more and more complex. Therefore, many consumer electronics products use the MCU as the core of their product control. As handheld devices become more and more mainstream of consumer electronics, the requirement of low power consumption and low cost of the MCU also becomes a mainstream trend of the current development. For example, in the application of the MCU to the bluetooth device, the MCU is generally required to wake up every several hundred milliseconds to perform data processing, so that the MCU is mostly in a sleep mode, i.e., a low power consumption mode, and thus the MCU is required to have low power consumption enough to meet the requirement of long-time battery operation when sleeping.
Generally, a power management circuit of an MCU is shown in fig. 1, and when the MCU normally operates, a power supply supplies power to different modules in the MCU through a high-power-consumption high-performance LDO. When the MCU is in low power mode, the high performance LDO will be turned off along with other unwanted functions, and the MCU will be powered by a lower voltage power supply. However, it is not enough to reduce the power consumption of the LDO, and the bandgap circuit also has a larger power consumption. The circuit structure of the bandgap circuit adopted in the MCU is complex at present, the power consumption is large, excessive battery energy consumption is caused, and particularly, the circuit structure is in a low power consumption mode.
Disclosure of Invention
The embodiment of the application provides a low-power-consumption bandgap circuit for an MCU (microprogrammed control unit) and an implementation method thereof, and aims to solve the problems that the circuit structure of the bandgap circuit in the MCU is complex, the power consumption is high, and excessive battery energy consumption is caused in a low-power-consumption mode in the prior art.
In a first aspect, an embodiment of the present application provides a low power consumption bandgap circuit for an MCU, including: the temperature coefficient reference current generating circuit, the reference voltage generating circuit and the reference current generating circuit;
the temperature coefficient reference current generating circuit comprises a positive temperature coefficient reference current output end and a negative temperature coefficient reference current output end; the reference voltage generating circuit comprises a fourth PMOS tube, a fifth PMOS tube, a third resistor and a zero temperature coefficient reference voltage output end; the reference current generating circuit comprises a sixth PMOS tube, a seventh PMOS tube and a zero temperature coefficient reference current output end;
the source electrode of the fourth PMOS tube is connected with a power supply end, the grid electrode of the fourth PMOS tube is connected with the negative temperature coefficient reference current output end, and the drain electrode of the fourth PMOS tube is connected with the first end of the third resistor and the drain electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with a power supply end, and the grid electrode of the fifth PMOS tube is connected with the positive temperature coefficient reference current output end; the second end of the third resistor is connected with a ground terminal; the zero temperature coefficient reference voltage output end is connected with the first end of the third resistor, and the zero temperature coefficient reference voltage output end outputs zero temperature coefficient reference voltage.
The source electrode of the sixth PMOS tube is connected with a power supply end, the grid electrode of the sixth PMOS tube is connected with the negative temperature coefficient reference current output end, and the drain electrode of the sixth PMOS tube is connected with the zero temperature coefficient reference current output end; the source electrode of the seventh PMOS tube is connected with a power supply end, the grid electrode of the seventh PMOS tube is connected with a positive temperature coefficient reference current output end, and the drain electrode of the seventh PMOS tube is connected with the zero temperature coefficient reference current output end; and the zero temperature coefficient reference current output end outputs zero temperature coefficient reference current.
Furthermore, the temperature coefficient reference current generating circuit comprises a starting circuit, a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit; the start-up circuit includes: a fourth NMOS transistor, an eighth PMOS transistor and a ninth PMOS transistor;
the source electrode of the eighth PMOS tube is connected with a power supply end, the grid electrode of the eighth PMOS tube is connected with the positive temperature coefficient reference current generating circuit and the negative temperature coefficient reference current generating circuit, the drain electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply end, and the drain electrode of the ninth PMOS tube is connected with the positive temperature coefficient reference current generating circuit and the negative temperature coefficient reference current generating circuit; and the grid electrode of the fourth NMOS tube is connected with a power supply end, and the source electrode of the fourth NMOS tube is connected with a grounding end.
Further, the positive temperature coefficient reference current generating circuit includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first triode, a second triode and a first resistor;
the source electrode of the first PMOS tube is connected with a power supply end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the positive temperature coefficient reference current output end, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the drain electrode of the ninth PMOS tube; the source electrode of the second PMOS tube is connected with a power supply end, and the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the drain electrode of the first NMOS tube and the negative temperature coefficient reference current generating circuit, and the source electrode of the second NMOS tube is connected with the first end of the first resistor; the source electrode of the first NMOS tube is connected with the emitting electrode of the second triode; the base electrode of the second triode is connected with the grounding end, and the collector electrode of the second triode is connected with the grounding end; the second end of the first resistor is connected with the emitting electrode of the first triode; the base electrode of the first triode is connected with the grounding end, and the collector electrode of the first triode is connected with the grounding end.
Further, the negative temperature coefficient reference current generating circuit includes: the first PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the second PMOS tube, the third PMOS tube, the second triode and the second resistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the third NMOS tube is connected with the first end of the second resistor; the second end of the second resistor is connected with a ground terminal; and the source electrode of the third PMOS tube is connected with a power supply end, and the grid electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and the negative temperature coefficient reference current output end.
Further, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor all adopt PMOS transistors with low threshold voltage, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor all adopt NMOS transistors with low threshold voltage.
In a second aspect, an embodiment of the present application provides a low power consumption bandgap circuit implementation method for an MCU, where the method includes:
the power supply end is electrified, negative temperature coefficient reference current is input into the fourth PMOS tube, positive temperature coefficient reference current is input into the fifth PMOS tube, zero temperature coefficient reference current is obtained through combination of the negative temperature coefficient reference current and the positive temperature coefficient reference current and is input into the third resistor, zero temperature coefficient reference voltage is obtained, and the zero temperature coefficient reference voltage is output to the output end of the zero temperature coefficient reference voltage;
the negative temperature coefficient reference current is input into the sixth PMOS tube, the positive temperature coefficient reference current is input into the seventh PMOS tube, the zero temperature coefficient reference current is obtained through the combination of the negative temperature coefficient reference current and the positive temperature coefficient reference current, and the zero temperature coefficient reference current is output to the zero temperature coefficient reference current output end.
Further, the generating of the positive temperature coefficient reference current comprises:
according to VBEQ2＝VBEQ1+ I _ MN2 × R1, resulting in I _ ptat ═ I _ MN2 ═ VBE (VBE)Q2-VBEQ1)/R1；
According to the characteristic of the triode, the voltage parameter VBE between the base electrode and the emitter electrode is kT/q l n (I)0/IS) It is possible to obtain:
I_ptat＝kT/q*(ln(I_MN1/Is)-ln(I_MN1/Is/M)/R1，
i.e., I _ ptat ═ kT/q lnM/R1;
according to dI _ ptat/dT ═ k/q lnM/R1> 0; thereby obtaining I _ ptat as a positive temperature coefficient reference current I _ ptat;
wherein, I _ MN2 is the current of the second NMOS transistor; VBEQ2The voltage between the base electrode and the emitter of the second triode is obtained; VBEQ1The voltage between the base electrode and the emitter of the first triode; r1 is the resistance of the first resistor; k is Boltzmann constant, q is the constant of charge, T is the absolute temperature, I0Is the current of the triode collector; is triode saturation current; and I _ ptat is the current of the fifth PMOS tube.
Further, the generating of the negative temperature coefficient reference current comprises:
i _ MN3 is set to I _ MN1, according to I _ MN3 to I _ MN1 to VA/R2 to VBEQ2the/R2, the dVBE/dT is a constant according to the negative temperature coefficient voltage VBE between the base and the emitter of the triode. The I _ MN3 obtains I _ ntat as negative temperature coefficient current through a certain copy proportion (n:1), namely n I _ ntat is I _ MN 3;
VA is the voltage of a first node, and the first node is a connection point of a source electrode of the first NMOS tube and an emitting electrode of the second triode; VBEQ2The voltage between the base electrode and the emitter of the second triode is obtained; i _ MN1 is the current of the first NMOS transistor; i _ MN3 is the current of the second resistor; r2 is the resistance of the second resistor; i _ ntat is the current of the fourth PMOS tube, and n is a constant.
Further, the obtaining the zero temperature coefficient reference voltage includes:
zero temperature coefficient reference voltage: v _ VREF ═ I _ R3 ═ R3 ═ I _ ptat + I _ ntat) · R3;
wherein, I _ R3 is the current of the third resistor, and R3 is the resistance of the third resistor.
Further, the obtaining the zero temperature coefficient reference current includes:
zero temperature coefficient reference current: i _ IREF — I _ MP6+ I _ MP7 — I _ ptat + I _ ntat;
wherein, I _ MP6 is the current of the sixth PMOS transistor; i _ MP7 is the current of the seventh PMOS transistor.
According to the embodiment of the application, positive and negative temperature coefficient reference currents are respectively input to a reference voltage generating circuit by setting a temperature coefficient reference current generating circuit, the positive and negative temperature coefficient reference currents are input to the reference current generating circuit, the positive temperature coefficient reference current and the negative temperature coefficient reference current are added to obtain a reference current, and a corresponding reference voltage is obtained according to the reference current, so that the reference voltage and the reference current in a low power consumption mode are provided for the MCU; through the bandgap circuit with a simple structure, low power consumption is realized, the consumption of a battery is reduced, the cost is saved, and meanwhile, reference current and reference voltage meeting performance requirements can be provided.
Drawings
FIG. 1 is a schematic structural diagram of a low power consumption power management circuit module of an MCU;
fig. 2 is a schematic structural diagram of a low-power consumption bandgap circuit for an MCU according to an embodiment of the present application;
fig. 3 is a graph of a current-year temperature change of a low-power bandgap circuit for an MCU according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, specific embodiments of the present application will be described in detail with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some but not all of the relevant portions of the present application are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
According to the low-power-consumption bandgap circuit for the MCU, the positive temperature coefficient reference current and the negative temperature coefficient reference current are respectively input to the reference voltage generating circuit and the reference current generating circuit through the temperature coefficient reference current generating circuit, the reference currents are obtained by adding the currents, the corresponding reference voltage is obtained according to the reference currents, and the purpose that the reference voltage and the reference current in the low-power-consumption mode are provided for the MCU is achieved; the bandgap circuit with a simple structure is used for realizing low power consumption, reducing the consumption of batteries and saving the cost; the whole circuit is simple in structure and adopts the MOS tube with low threshold voltage, so that the starting voltage and power consumption of the circuit are reduced, and the cost is saved. When the MCU works normally, the power supply supplies power to different modules in the MCU through a high-power-consumption high-performance LDO. When the MCU is in low power mode, the high performance LDO is turned off along with other unwanted functions, and the MCU is powered by a low power and low output voltage power supply. But only reduces the power consumption of the LDO, the bandgap circuit also has higher power consumption; the embodiment adopts the low-power consumption bandgap circuit, realizes the performance close to the normal mode bandgap by using the minimum current consumption, has large output voltage range and convenient and flexible adjustment, is only related to the resistor and is not limited by other factors; the circuit of the embodiment has the advantages of simple structure, small area, low implementation cost, reliable function and performance close to that of a common bandgap circuit, and is suitable for low-cost and low-power consumption MCU application.
Fig. 2 is a schematic structural diagram of a low power consumption bandgap circuit for an MCU according to an embodiment of the present application. Referring to fig. 2, the circuit specifically includes: a temperature coefficient reference current generation circuit 200, a reference voltage generation circuit 300, and a reference current generation circuit 400; the temperature coefficient reference current generating circuit 200 includes a start-up circuit, a positive temperature coefficient reference current generating circuit, and a negative temperature coefficient reference current generating circuit.
Specifically, the temperature coefficient reference current generating circuit 200 includes a positive temperature coefficient reference current output terminal and a negative temperature coefficient reference current output terminal; the reference voltage generating circuit 300 includes: a fourth PMOS tube MP4, a fifth PMOS tube MP5, a third resistor R3 and a zero temperature coefficient reference voltage output end; the reference current generating circuit 400 includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and a zero temperature coefficient reference current output terminal.
Specifically, the start-up circuit includes: a fourth NMOS transistor MN4, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP 9.
Specifically, the positive temperature coefficient reference current generating circuit includes: the transistor comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first triode Q1, a second triode Q2 and a first resistor R1.
Specifically, the negative temperature coefficient reference current generating circuit includes: the first PMOS transistor MP1, the first NMOS transistor MN1, the second NMOS transistor MN2, the second PMOS transistor MP2, the third NMOS transistor MN3, the third PMOS transistor MP3, the second triode Q2, and the second resistor R2.
The source of the fourth PMOS transistor MP4 is connected to a power source, the gate thereof is connected to the negative temperature coefficient reference current output terminal, and the drain thereof is connected to the first end of the third resistor R3 and the drain of the fifth PMOS transistor MP 5; the source electrode of the fifth PMOS tube MP5 is connected with a power supply end, and the grid electrode of the fifth PMOS tube MP5 is connected with the positive temperature coefficient reference current output end; a second end of the third resistor R3 is connected with the ground terminal; the zero temperature coefficient reference voltage output end is connected with a first end of the third resistor R3, and the zero temperature coefficient reference voltage output end outputs a zero temperature coefficient reference voltage.
The source electrode of the sixth PMOS transistor MP6 is connected to a power supply terminal, the gate electrode is connected to the negative temperature coefficient reference current output terminal, and the drain electrode is connected to the zero temperature coefficient reference current output terminal; the source electrode of the seventh PMOS tube MP7 is connected with a power supply end, the grid electrode of the seventh PMOS tube MP7 is connected with a positive temperature coefficient reference current output end, and the drain electrode of the seventh PMOS tube MP7 is connected with the zero temperature coefficient reference current output end; and the zero temperature coefficient reference current output end outputs zero temperature coefficient reference current.
The source electrode of the eighth PMOS transistor MP8 is connected to a power supply terminal, the gate electrode of the eighth PMOS transistor MP8 is connected to the gate electrode of the first PMOS transistor MN1, the drain electrode of the eighth PMOS transistor MP9 is connected to the gate electrode of the ninth PMOS transistor MP4, and the source electrode and the drain electrode of the ninth PMOS transistor MP9 are connected to the power supply terminal and the gate electrode of the first NMOS transistor MN 1; the gate of the fourth NMOS transistor MN4 is connected to a power supply terminal, and the source is connected to a ground terminal.
The source electrode of the first PMOS transistor MP1 is connected to a power supply terminal, the gate electrode of the first PMOS transistor MP 358978 is connected to the gate electrode of the second PMOS transistor MP2 and the positive temperature coefficient reference current output terminal, and the drain electrode of the first NMOS transistor MN1 is connected to the drain electrode of the ninth PMOS transistor MP 9; the source electrode of the second PMOS transistor MP2 is connected to a power supply terminal, and the drain electrode is connected to the gate electrode of the first PMOS transistor MP1, the gate electrode of the eighth PMOS transistor MP8 and the drain electrode of the second NMOS transistor MN 2; the grid electrode of the second NMOS transistor MN2 is connected with the grid electrode of the first NMOS transistor MN1 and the drain electrode of the first NMOS transistor MN1, and the source electrode of the second NMOS transistor MN2 is connected with the first end of the first resistor R1; the source electrode of the first NMOS transistor MN1 is connected with the emitter electrode of the second triode Q2; the base electrode of the second triode Q2 is connected with the grounding end, and the collector electrode of the second triode Q2 is connected with the grounding end; the second end of the first resistor R1 is connected with the emitter of the first triode Q1; the base electrode of the first triode Q1 is connected with the grounding end, and the collector electrode is connected with the grounding end.
The drain of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3, the gate is connected to the gate of the first NMOS transistor MN1, and the source is connected to the first end of the second resistor R2; a second end of the second resistor R2 is connected with the ground terminal; the source electrode of the third PMOS transistor MP3 is connected to a power supply terminal, and the gate electrode is connected to the drain electrode of the third NMOS transistor MN3 and the negative temperature coefficient reference current output terminal.
In this embodiment, the generation of the ptc reference current is realized by a ptc reference current generation circuit, and the channel width-to-length ratios of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be equal (W/L)MP1＝(W/L)MP2The channel width-length ratio of the first NMOS transistor MN1 to the second NMOS transistor MN2 is set to be equal (W/L)MN1＝(W/L)MN2Therefore, I _ MN1 that the current of the first NMOS transistor MN1 is equal to the current of the second NMOS transistor MN2 is obtained as I _ MN2, and the gate-source voltage of the first NMOS transistor MN1 is equal to the gate-source voltage of the second NMOS transistor MN2, and the gate-source voltage is VGSMN1＝VGSMN2(ii) a According to the fact that the grid electrode of the first NMOS tube MN1 is connected with the grid electrode of the second NMOS tube MN2, namely the grid electrodes of the first NMOS tube MN1 and the second NMOS tube MN2 are at the same potential, the source voltages of the first NMOS tube MN1 and the second NMOS tube MN2 are equal, and the voltage between the base electrode and the emitter electrode of the second triode Q2 is obtained to be equal to the VBE (voltage between the base electrode and the emitter electrode of the first triode Q1 and the sum of the voltage of the first resistor R1)Q2＝VBEQ1+ I _ MN2 × R1, so as to obtain the current value I _ MN2 ═ I _ MN1 ═ VBE (VBE) of the first NMOS transistor MN1 and the second NMOS transistor MN2Q2-VBEQ1) /R1; setting the number of the first triodes Q1 to be M and the number of the second triodes Q2 to be 1, and obtaining that the current of each first triode Q1 is 1/M of the current of the second triode Q2; according to the voltage parameter between the base electrode and the emitter of the triode characteristic: VBE ═ kT/q ═ ln (I)0/IS) It is possible to obtain:
the current value of the second NMOS transistor MN2 is:
I_MN2＝kT/q*(ln(I_MN1/Is)-ln(I_MN1/Is/M))/R1；
the channel width-length ratio of the first NMOS transistor MN1 to the fifth NMOS transistor is equal (W/L)MP2＝(W/L)MP5Obtaining that the current of the fifth PMOS transistor MP5 is equal to the current I _ ptat ═ I _ MN2 ═ kT/q ═ lnM/R1 of the second PMOS transistor MP 2;
according to dI _ ptat/dT ═ k/q lnM/R1> 0; thereby obtaining a positive temperature coefficient reference current I _ ptat.
In this embodiment, the sum of the gate-source voltage of the third NMOS transistor MN3 and the voltage of the second node B is equal to the sum of the gate-source voltage of the first NMOS transistor MN1 and the voltage of the first node a, that is, VB ═ VA + VGSMN1-VGSMN3And VB _ MN 3R 2;
the channel width-length ratio of the first NMOS transistor MN1 to the third NMOS transistor MN3 is set to be equal (W/L)MN1＝(W/L)MN3；
According to the formula of the MOS saturation region I-V, Id ═ beta (W/L) × (Vgs-Vth)2When the resistance of the second resistor R2 is adjusted, and the current of I _ MN3 is adjusted so that T is 25 ℃, VGS is obtainedMN3＝VGSMN1。
The current of the third NMOS transistor MN3 is equal to the current of the first NMOS transistor MN 1:
I_MN3＝I_MN1＝VA/R2＝VBEQ2/R2；
obtaining I _ MN3 as negative temperature coefficient current according to the conditions that VBE of the triode is negative temperature coefficient voltage, dVBE/dT is a constant and dVBE/dT is close to-1.5 mV/DEG C; the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and the ratio of the channel width-to-length ratio of the third PMOS transistor MP3 to the channel width-to-length ratio of the fourth PMOS transistor MP4 is n:1, I _ ntat is obtained as a negative temperature coefficient current.
In this embodiment, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fifth PMOS transistor MP5, the current I _ ntat of the fourth PMOS transistor MP4 and the current I _ ptat of the fifth PMOS transistor MP5 are added to obtain the current I _ R3 of the third resistor R3, the temperature coefficient of the current I _ R3 of the third resistor R3 is 0, I _ R3 is a zero temperature coefficient reference current, the zero temperature coefficient reference voltage V _ VREF is obtained according to the resistance of the zero temperature coefficient reference current and the resistance of the third resistor R3 as I _ R3R 3, and the reference voltage is output through the zero temperature coefficient reference voltage output terminal VREF _ OUT to provide the reference voltage for the MCU, thereby implementing the low power mode operation of the MCU.
In this embodiment, the current with zero temperature coefficient of I _ R3 can be obtained by obtaining n ((k/q) (-lnM/σ) ((R2/R1) from dI _ ntat/dT ═ k/q ═ lnM/R1 and dI _ ptat/dT ═ dVBE/dT/R2/n ═ σ/R2/n.
In this embodiment, the gate of the sixth PMOS transistor MP6 is connected to the gate of the fourth PMOS transistor MP4, so that the current I _ MP6 of the sixth PMOS transistor MP6 is I _ ntat, and the gate of the seventh PMOS transistor MP7 is connected to the gate of the fifth PMOS transistor MP5, so that the current I _ MP7 of the seventh PMOS transistor MP7 is I _ ptat; the drain electrode of the sixth PMOS transistor MP6 is connected to the drain electrode of the seventh PMOS transistor MP7, the current I _ MP6 of the sixth PMOS transistor MP6 and the current I _ MP7 of the seventh PMOS transistor MP7 are added to obtain the zero-temperature-coefficient reference current I _ IREF ═ I _ ptat + I _ ntat, and the reference current is output through the zero-temperature-coefficient reference current output terminal IREF _ ZTAT to provide the reference current for the MCU, thereby realizing the low power mode operation of the MCU.
In this embodiment, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 all adopt PMOS transistors with low threshold voltage, and the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 all adopt NMOS transistors with low threshold voltage; the low threshold voltage of the PMOS tube and the NMOS tube enables the operating voltage of the bandgap circuit to be lower, and lower power consumption is achieved.
On the basis of the foregoing embodiment, an embodiment of the present application further provides a method for implementing a low power consumption bandgap circuit for an MCU, where the method for implementing a low power consumption bandgap circuit for an MCU provided in this embodiment includes:
the power supply end is electrified, negative temperature coefficient reference current is input into the fourth PMOS tube MP4, positive temperature coefficient reference current is input into the fifth PMOS tube MP5, zero temperature coefficient reference current is obtained through combination of the negative temperature coefficient reference current and the positive temperature coefficient reference current and is input into the third resistor R3, zero temperature coefficient reference voltage is obtained, and the zero temperature coefficient reference voltage is output to the output end of the zero temperature coefficient reference voltage;
the negative temperature coefficient reference current is input to the sixth PMOS tube MP6, the positive temperature coefficient reference current is input to the seventh PMOS tube MP7, the zero temperature coefficient reference current is obtained by combining the negative temperature coefficient reference current and the positive temperature coefficient reference current, and the zero temperature coefficient reference current is output to the zero temperature coefficient reference current output end.
In this embodiment, the generating of the ptc reference current includes:
setting (W/L)MP1＝(W/L)MP2,(W/L)MN1＝(W/L)MN2Then, I _ MN1 is obtained as I _ MN2, thereby obtaining VGSMN1＝VGSMN2；
According to the connection of the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, the source voltage of the first NMOS transistor MN1 is equal to the source voltage of the second NMOS transistor MN2, namely VBEQ2＝VBEQ1+ I _ MN2 × R1, so that I _ MN2 ═ I _ MN1 (VBE)Q2-VBEQ1)/R1；
Setting the number of the first triodes Q1 to be M and the number of the second triodes Q2 to be 1, and obtaining that the current of each first triode Q1 is 1/M of the current of the second triode Q2;
according to the characteristic of the triode, the voltage parameter VBE between the base electrode and the emitter electrode is kT/q l n (I)0/IS) It is possible to obtain:
the current of the second NMOS transistor MN2 is:
I_MN2＝kT/q*(ln(I_MN1/Is)-ln(I_MN1/Is/M)/R1；
setting (W/L)MN1＝(W/L)MP5The current of the fourth PMOS transistor MP4 is:
I_ptat＝I_MN2＝kT/q*lnM/R1；
according to dI _ ptat/dT ═ k/q lnM/R1> 0; thereby obtaining I _ ptat as a positive temperature coefficient reference current I _ ptat; and obtaining the reference current with the positive temperature coefficient.
Wherein (W/L)MP1The channel width-to-length ratio of the first PMOS transistor MP 1; (W/L)MP2The channel width-to-length ratio of the second PMOS transistor MP 2; (W/L)MN1Is the channel width-length ratio of the first NMOS transistor MN 1; (W/L)MN2Is the channel width and length of the second NMOS transistor MN2A ratio; (W/L)MP5The channel width-to-length ratio of the fifth PMOS transistor MP 5; i _ MN1 is the current of the first NMOS transistor MN 1; i _ MN2 is the current of the second NMOS transistor MN 2; VGSMN1Is the gate-source voltage of the first NMOS transistor MN 1; VGSMN2The gate-source voltage of the second NMOS transistor MN 2; VBEQ2Is the voltage between the base and the emitter of the second triode Q2; VBEQ1Is the voltage between the base and the emitter of the first triode Q1; r1 is the resistance of the first resistor R1; k is Boltzmann constant, q is the constant of charge, T is the absolute temperature, I0Is the current of the triode collector; is triode saturation current; i _ ptat is the current of the fifth PMOS transistor MP 4.
In this embodiment, the generating of the negative temperature coefficient reference current includes:
according to VB ═ VA + VGSMN1-VGSMN3，VB＝I_MN3*R2；
The channel width-length ratio of the first NMOS transistor MN1 to the third NMOS transistor MN3 is set to be equal (W/L)MN1＝(W/L)MN3；
According to the formula of the MOS saturation region I-V, Id ═ beta (W/L) × (Vgs-Vth)2When the resistance of the second resistor R2 is adjusted, and the current of I _ MN3 is adjusted so that T is 25 ℃, VGS is obtainedMN3＝VGSMN1。
The current of the third NMOS transistor is equal to the current I _ MN3 ═ I _ MN1 ═ VA/R2 ═ VBE of the first NMOS transistor MN1Q2/R2；
Obtaining I _ MN3 as negative temperature coefficient current according to the conditions that VBE of the triode is negative temperature coefficient voltage, dVBE/dT is a constant and dVBE/dT is close to-1.5 mV/DEG C; the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and the ratio of the channel width-to-length ratio of the third PMOS transistor MP3 to the channel width-to-length ratio of the fourth PMOS transistor MP4 is n:1, obtaining I _ ntat as negative temperature coefficient current to realize obtaining positive temperature coefficient reference current.
VA is a voltage of a first node, and the first node is a connection point between a source electrode of the first NMOS transistor MN1 and an emitter electrode of the second triode Q2; VB is the voltage of a second node, and the second node is the connection point of the source electrode of the third NMOS transistor MN3 and the first end of the second resistor R2; VGSMN3The gate-source voltage of the third NMOS transistor MN 3; i _ MN3 is theThe current of two resistors R2; r2 is the resistance of the second resistor R2; i _ ntat is the current of the fourth PMOS transistor MP 4.
In this embodiment, the obtaining the zero temperature coefficient reference voltage includes:
according to the connection of the drain electrode of the fourth PMOS transistor MP4 and the drain electrode of the fifth PMOS transistor MP5,
obtaining I _ R3 ═ I _ ptat + I _ ntat;
thus obtaining a zero temperature coefficient reference voltage: v _ VREF ═ I _ R3 × R3;
wherein, I _ R3 is the current of the third resistor R3, i.e. the zero temperature coefficient reference current, and R3 is the resistance of the third resistor R3.
In this embodiment, the current I _ R3 with zero temperature coefficient can be obtained by obtaining n ((k/q) (-lnM/σ) (-R2/R1) from the values of n obtained by dI _ ntat/dT ═ k/q ═ lnM/R1 and dI _ ptat/dT ═ dVBE/dT/R2/n ═ σ/R2/n.
In this embodiment, the obtaining the zero temperature coefficient reference current includes:
according to the connection between the gate of the sixth PMOS transistor MP6 and the gate of the fourth PMOS transistor MP4, I _ MP6 is equal to I _ ntat, and I _ MP7 is equal to I _ ptat;
according to the connection of the drain electrode of the sixth PMOS transistor MP6 and the drain electrode of the seventh PMOS transistor MP7,
obtaining a zero temperature coefficient reference current: i _ IREF ═ I _ ptat + I _ ntat;
wherein, I _ MP6 is the current of the sixth PMOS transistor MP 6; i _ MP7 is the current of the seventh PMOS transistor MP 7.
Specifically, a zero temperature coefficient reference voltage and a zero temperature coefficient reference current are obtained and input into the MCU circuit, and the low power consumption mode operation of the MCU is realized.
In the present embodiment, referring to fig. 3, the ptc reference current I _ ptat increases with the increase of temperature; the negative temperature coefficient reference current I _ ntat decreases with increasing temperature, the zero temperature coefficient reference current I _ R3 ═ I _ ptat + I _ ntat, and the zero temperature coefficient reference current changes substantially without being affected by temperature; the output of zero temperature coefficient current is realized through the bandgap circuit, the influence of temperature on the voltage and the current on the precision of reference voltage and reference current is avoided, and excessive power consumption is generated.
In this embodiment, simulation software may be adopted to implement the test of the low power consumption bandgap circuit implementation method for the MCU in this embodiment, the power supplies of 2V, 3.3V, and 3.6V are respectively set at the power supply terminals, and meanwhile, the temperatures of-40 degrees, 25 degrees, and 125 degrees are respectively set for the power supplies set for each time to perform the reference voltage and reference current tests, and the simulation result shows that, at different temperatures and voltages, the deviation of the reference voltage is less than 5%, the change of the reference current with the temperature is less than 5%, and the quiescent current is less than 1uA, so as to meet the requirements of the low power consumption and the accuracy of the low power consumption mode of the MCU and the bandgap circuit.
The positive temperature coefficient reference current and the negative temperature coefficient reference current are respectively input to the reference voltage generating circuit 300, the positive temperature coefficient reference current and the negative temperature coefficient reference current are input to the reference current generating circuit 400, the positive temperature coefficient reference current and the negative temperature coefficient reference current are added to obtain the reference current, the corresponding reference voltage is obtained according to the reference current, and the purpose of providing the reference voltage and the reference current in the low power consumption mode for the MCU is achieved; through the bandgap circuit with a simple structure, low power consumption is realized, the consumption of the battery is reduced, and the cost is saved.
The foregoing is considered as illustrative of the preferred embodiments of the invention and the technical principles employed. The present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the claims.
Claims (10)
1. A low power consumption bandgap circuit for an MCU, comprising: the temperature coefficient reference current generating circuit, the reference voltage generating circuit and the reference current generating circuit;
the temperature coefficient reference current generating circuit comprises a positive temperature coefficient reference current output end and a negative temperature coefficient reference current output end; the reference voltage generating circuit comprises a fourth PMOS tube, a fifth PMOS tube, a third resistor and a zero temperature coefficient reference voltage output end; the reference current generating circuit comprises a sixth PMOS tube, a seventh PMOS tube and a zero temperature coefficient reference current output end;
the source electrode of the fourth PMOS tube is connected with a power supply end, the grid electrode of the fourth PMOS tube is connected with the negative temperature coefficient reference current output end, and the drain electrode of the fourth PMOS tube is connected with the first end of the third resistor and the drain electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with a power supply end, and the grid electrode of the fifth PMOS tube is connected with the positive temperature coefficient reference current output end; the second end of the third resistor is connected with a ground terminal; the zero temperature coefficient reference voltage output end is connected with the first end of the third resistor and outputs zero temperature coefficient reference voltage;
the source electrode of the sixth PMOS tube is connected with a power supply end, the grid electrode of the sixth PMOS tube is connected with the negative temperature coefficient reference current output end, and the drain electrode of the sixth PMOS tube is connected with the zero temperature coefficient reference current output end; the source electrode of the seventh PMOS tube is connected with a power supply end, the grid electrode of the seventh PMOS tube is connected with a positive temperature coefficient reference current output end, and the drain electrode of the seventh PMOS tube is connected with the zero temperature coefficient reference current output end; and the zero temperature coefficient reference current output end outputs zero temperature coefficient reference current.
2. The low-power consumption bandgap circuit for the MCU of claim 1, wherein the temperature coefficient reference current generating circuit comprises a start-up circuit, a positive temperature coefficient reference current generating circuit and a negative temperature coefficient reference current generating circuit; the start-up circuit includes: a fourth NMOS transistor, an eighth PMOS transistor and a ninth PMOS transistor;
the source electrode of the eighth PMOS tube is connected with a power supply end, the grid electrode of the eighth PMOS tube is connected with the positive temperature coefficient reference current generating circuit and the negative temperature coefficient reference current generating circuit, the drain electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply end, and the drain electrode of the ninth PMOS tube is connected with the positive temperature coefficient reference current generating circuit and the negative temperature coefficient reference current generating circuit; and the grid electrode of the fourth NMOS tube is connected with a power supply end, and the source electrode of the fourth NMOS tube is connected with a grounding end.
3. The low power consumption bandgap circuit for MCU of claim 2, wherein said positive temperature coefficient reference current generating circuit comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first triode, a second triode and a first resistor;
the source electrode of the first PMOS tube is connected with a power supply end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the positive temperature coefficient reference current output end, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the drain electrode of the ninth PMOS tube; the source electrode of the second PMOS tube is connected with a power supply end, and the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the drain electrode of the first NMOS tube and the negative temperature coefficient reference current generating circuit, and the source electrode of the second NMOS tube is connected with the first end of the first resistor; the source electrode of the first NMOS tube is connected with the emitting electrode of the second triode; the base electrode of the second triode is connected with the grounding end, and the collector electrode of the second triode is connected with the grounding end; the second end of the first resistor is connected with the emitting electrode of the first triode; the base electrode of the first triode is connected with the grounding end, and the collector electrode of the first triode is connected with the grounding end.
4. The low power consumption bandgap circuit for MCU of claim 2, wherein said negative temperature coefficient reference current generating circuit comprises: the first PMOS tube, the first NMOS tube, the second PMOS tube, the third NMOS tube, the third PMOS tube, the second triode and the second resistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the third NMOS tube is connected with the first end of the second resistor; the second end of the second resistor is connected with a ground terminal; and the source electrode of the third PMOS tube is connected with a power supply end, and the grid electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and the negative temperature coefficient reference current output end.
5. The low-power consumption bandgap circuit for the MCU of any one of claims 1 to 4, wherein the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth PMOS transistors are all low-threshold voltage PMOS transistors, and the first, second, third and fourth NMOS transistors are all low-threshold voltage NMOS transistors.
6. A method for implementing a low power consumption bandgap circuit for an MCU, based on the low power consumption bandgap circuit for an MCU of any one of claims 1-5, wherein the method comprises the following steps:
the power supply end is electrified, the negative temperature coefficient reference current is input into the fourth PMOS tube, the positive temperature coefficient reference current is input into the fifth PMOS tube, the zero temperature coefficient reference current is obtained by combining the negative temperature coefficient reference current and the positive temperature coefficient reference current in a certain proportion and is input into the third resistor, the zero temperature coefficient reference voltage is obtained, and the zero temperature coefficient reference voltage is output to the output end of the zero temperature coefficient reference voltage;
the negative temperature coefficient reference current is input into the sixth PMOS tube, the positive temperature coefficient reference current is input into the seventh PMOS tube, the zero temperature coefficient reference current is obtained by combining the negative temperature coefficient reference current and the positive temperature coefficient reference current in a certain proportion, and the zero temperature coefficient reference current is output to the zero temperature coefficient reference current output end.
7. The method of claim 6, wherein the generating of the PTC reference current comprises:
according to VBEQ2＝VBEQ1+ I _ MN2 × R1, resulting in I _ ptat ═ I _ MN2 ═ VBE (VBE)Q2-VBEQ1)/R1；
According to the characteristic of the triode, the voltage parameter VBE between the base electrode and the emitter electrode is kT/q l n (I)0/IS) It is possible to obtain:
I_ptat＝kT/q*(ln(I_MN1/Is)-ln(I_MN1/Is/M)/R1，
i.e., I _ ptat ═ kT/q lnM/R1;
according to dI _ ptat/dT ═ k/q lnM/R1> 0; thereby obtaining I _ ptat as a positive temperature coefficient reference current I _ ptat;
wherein, I _ MN2 is the current of the second NMOS transistor; VBEQ2The voltage between the base electrode and the emitter of the second triode is obtained; VBEQ1The voltage between the base electrode and the emitter of the first triode; r1 is the resistance of the first resistor; k is Boltzmann constant, q is the constant of charge, T is the absolute temperature, I0Is the current of the triode collector; is triode saturation current; and I _ ptat is the current of the fifth PMOS tube.
8. The method of claim 7, wherein the generating of the negative temperature coefficient reference current comprises:
i _ MN3 is set to I _ MN1, according to I _ MN3 to I _ MN1 to VA/R2 to VBEQ2The transistor is characterized in that the transistor/resistor (I _ MN) 2 is characterized in that according to the fact that the voltage VBE between the base electrode and the emitter of the transistor is negative temperature coefficient voltage, the dVBE/dT is a constant, I _ MN3 obtains I _ ntat which is negative temperature coefficient current through the proportion n:1, and n is I _ ntat which is I _ MN 3;
VA is the voltage of a first node, and the first node is a connection point of a source electrode of the first NMOS tube and an emitting electrode of the second triode; VBEQ2The voltage between the base electrode and the emitter of the second triode is obtained; i _ MN1 is the current of the first NMOS transistor; i _ MN3 is the current of the second resistor; r2 is the resistance of the second resistor; i _ ntat is the current of the fourth PMOS tube, and n is a constant.
9. The method of claim 8, wherein the obtaining the zero temperature coefficient reference voltage comprises:
zero temperature coefficient reference voltage: v _ VREF ═ I _ R3 ═ R3 ═ I _ ptat + I _ ntat) · R3;
wherein, I _ R3 is the current of the third resistor, and R3 is the resistance of the third resistor.
10. The method of claim 8, wherein the obtaining the zero temperature coefficient reference current comprises:
zero temperature coefficient reference current: i _ IREF — I _ MP6+ I _ MP7 — I _ ptat + I _ ntat;
wherein, I _ MP6 is the current of the sixth PMOS transistor; i _ MP7 is the current of the seventh PMOS transistor.
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