CN201589987U

CN201589987U - Reference voltage and bias current generating circuit

Info

Publication number: CN201589987U
Application number: CN2010201023934U
Authority: CN
Inventors: 职春星; 胡永华; 徐滔; 惠国瑜
Original assignee: BRITE SEMICONDUCTOR (SHANGHAI) Corp
Current assignee: BRITE SEMICONDUCTOR (SHANGHAI) Corp
Priority date: 2010-01-26
Filing date: 2010-01-26
Publication date: 2010-09-22
Anticipated expiration: 2020-01-26

Abstract

The utility model relates to a reference voltage and a bias current generating circuit, wherein a bias current generating circuit generates bias current, a reference voltage generating circuit generates reference voltages, a current mirror circuit copies the bias current to a low-voltage bias power supply circuit and a bias current output circuit, the low-voltage bias power supply circuit is used to provide currents for the bias current generating circuit, the reference voltage generating circuit and the current mirror circuit, the bias current output circuit transmits the bias current to an internal circuit and other circuits of a power chip to start up a block circuit to generate a startup current to transmit to the bias current generating circuit, the bias current generating circuit is conductive and generated a bias current, the bias current crosses the current mirror circuit to conduct the low-voltage bias power supply circuit, once the low-voltage bias power supply circuit is conductive, the block circuit is started to generate a block signal, and startup is end. The utility model is capable of withstanding high voltage, has higher destabilization resistant capability, and the reference voltage generated by the circuit is hardly affected by the variation of an external power source.

Description

A kind of reference voltage and bias current generating circuit

Technical field

The utility model relates to a kind of reference voltage and bias current generating circuit.

Background technology

In a lot of power chips, external power source is the unique power supply of chip.For example, in the AC-DC power chip, the interchange input of 220V is unique power supply, behind overcommutation and filtering circuit, a High Level DC Voltage is used to chip for driving, and in the automotive electronics chip, (voltage 12～40V) is given chip power supply to on-vehicle battery, in the power-supply management system of desktop computer, the supply voltage of chip is 12V.And, generally having only high power device directly to power by external power source at chip internal, all logics and control circuit all are made of the CMOS (complementary metal oxide semiconductor (CMOS)) of low pressure.Convert the dc high voltage (VHV) of outside input to DC low-voltage (VREG) so have an internal electric source (Linear Regulator) in the chip, so that be used for to logic and control circuit power supply.

On the other hand, internal electric source need utilize reference voltage and bias current to produce DC low-voltage (VREG), therefore, just needs a reference voltage and the bias current generating circuit that can directly be powered by outside dc high voltage in the chip.In addition, because external dc high voltage generally all can be attended by big disturbance, so this reference voltage and bias current generating circuit also need to have very high disturbance rejection ability.

The utility model content

A kind of reference voltage and bias current generating circuit that the utility model provides, this circuit can be high pressure resistant, and have higher disturbance rejection ability, and the influence that the reference voltage that is produced is changed by external power source is very little.

In order to achieve the above object, the utility model provides a kind of reference voltage and bias current generating circuit, the startup cut-off circuit, bias current generating circuit, the reference voltage generating circuit that comprise circuit connection successively, comprise also that circuit connects the current mirroring circuit of described bias current generating circuit, circuit connects the low pressure bias power supply circuit of described startup cut-off circuit, bias current generating circuit, reference voltage generating circuit and current mirroring circuit respectively, and circuit connects the bias current output circuit of described current mirroring circuit;

Bias current generating circuit produces bias current PTAT (positive temperature coefficient (PTC) electric current);

Bias current flows through reference voltage generating circuit, produces reference voltage V BG;

Current mirroring circuit is given low pressure bias power supply circuit and bias current output circuit with bias current PTAT mirror-Symmetrical Copying Technique, electric current is provided for bias current generating circuit, reference voltage generating circuit and current mirroring circuit by the low pressure bias power supply circuit, the bias current output circuit then is transferred to bias current PTAT internal circuit and other circuit of power chip;

Bias current generating circuit and reference voltage generating circuit are low-voltage circuit;

Current mirroring circuit, low pressure bias power supply circuit and bias current output circuit are high-tension circuit;

Because bias current generating circuit and reference voltage generating circuit all are low-voltage circuits, these low-voltage circuits all are to be powered by the low pressure bias power supply circuit, and the bias current of low pressure bias power supply circuit is produced by low-voltage circuit, so, this structure can not start voluntarily, can rest on the state that can not generate bias current PTAT, therefore, must introduce the startup cut-off circuit and solve this problem, when just powering on, start cut-off circuit and produce a starting current, and this current mirror is transferred to bias current generating circuit, make bias current generating circuit conducting and produce bias current PTAT, bias current makes the conducting of low pressure bias power supply circuit and obtains correct bias through current mirroring circuit again, makes that the low pressure bias power supply circuit can be to bias current generating circuit, reference voltage generating circuit and current mirroring circuit are powered, in case low pressure bias power supply circuit conducting, start cut-off circuit and produce pick-off signal, start and finish, entire circuit enters normal operating conditions.

The utility model provides reference voltage and bias current can for the internal circuit of power chip, make internal circuit to convert the dc high voltage (VHV) of outside input to DC low-voltage (VREG), so that be used for to logic and control circuit power supply, make the logic and the control of chip internal can obtain correct realization, have high disturbance rejection ability simultaneously, the influence that the reference voltage that is produced is changed by external power source is very little.

Description of drawings

Fig. 1 is a kind of reference voltage that provides of the utility model and the circuit block diagram of bias current generating circuit;

Fig. 2 is a kind of reference voltage that provides of the utility model and the circuit diagram of bias current generating circuit.

Figure 3 shows that the antijamming capability oscillogram of circuit.

Figure 4 shows that the startup and the operate as normal oscillogram of circuit.

Embodiment

Following according to Fig. 1～Fig. 4, specify better embodiment of the present utility model:

As shown in Figure 1, be that the utility model provides a kind of reference voltage and bias current generating circuit, comprise the startup cut-off circuit 101 of circuit connection successively, bias current generating circuit 102, reference voltage generating circuit 103, also comprise the current mirroring circuit 104 that circuit connects described bias current generating circuit 102, circuit connects described startup cut-off circuit 101 respectively, bias current generating circuit 102, the low pressure bias power supply circuit 105 of reference voltage generating circuit 103 and current mirroring circuit 104, and circuit connects the bias current output circuit 106 of described current mirroring circuit 104;

As shown in Figure 2, PMOS (P-channel metal-oxide-semiconductor) manages MP1, MP2, and NMOS (N NMOS N-channel MOS N) manages MN1, MN2, triode Q1, Q2, PMOS manages MP8, and resistance R 1 constituted bias current generating circuit 102, and the PTAT electric current of generation is:

Iptat＝ΔVBE/R1，

Wherein, Δ VBE=VBE_Q2-VBE_Q1, VBE_Q1 and VBE_Q2 are respectively ground level-emitting stage voltage of triode Q1 and Q2;

PMOS manages MP3, and resistance R 2 and triode Q3 have constituted reference voltage generating circuit 103, the PTAT electric current that current mirror MP3 replica bias current generating circuit 102 produces, and make this bias current flow through resistance R 2 and triode Q3, thereby produce reference voltage be:

VBG＝VBE_Q3+(R2/R1)×ΔVBE，

Wherein, VBE_Q3 is ground level-emitting stage voltage of triode Q3;

By choose reasonable R1, the value of R2 and Δ VBE can obtain a stable benchmark voltage VBG who is not subjected to temperature drift;

PMOS manages MP4, and NMOS manages MN3, MN4, and PMOS pipe MP6 has constituted current mirroring circuit 104;

PMOS pipe MP5 is as low pressure bias power supply circuit 105;

PMOS manages MP7, and NMOS pipe MN5 and MN6 constitute bias current output circuit 106;

Current mirroring circuit 104 to MP5 and MP7, is given MP1 by MP5 with bias current PTAT mirror-Symmetrical Copying Technique, MP2, and MP3, MP4, MP8 provides electric current, and MP7 then is transferred to internal circuit and other circuit with bias current PTAT through NMOS pipe MN5 and MN6;

Voltage VDDR is:

VDDR＝VBE_Q2+VGS_MN2+VGS_MP8，

Wherein, VBE_Q2 is ground level-emitting stage voltage of triode Q2, and VGS_MN2 is the gate source voltage of NMOS pipe MN2, and VGS_MP8 is the gate source voltage of PMOS pipe MP8;

PMOS manages MP10, MP11, and MP12 and resistance R 3, and PMOS pipe MP9 forms startup cut-off circuit 101.

Because VDDR is a low-voltage (in typical case for about 3V), so NMOS pipe MN1, MN2, PMOS manage MP1, MP2, and MP3, MP4, MP8, resistance R 1, R2, triode Q1, Q2, Q3 are the devices of low-voltage.So not only can reduce the area of circuit, and improve the matching degree (matching degree of low-voltage device is well more a lot of than high tension apparatus) between the device.

PMOS manages MP5, and MP6, MP7, MP9 are high tension apparatus, and MP5 provides bias current for low-voltage device, bears VHV simultaneously to the high voltage between the VDDR, because coupling and high voltage bearing needs, MN3, MN4 also are high tension apparatus.

When just powering on, the MP10 and the resistance R 3 that start in the cut-off circuit 101 can produce a starting current, and this current mirror is transferred to MP11 and MP12, MP11 and MP12, to MP1, MP2, MP3, MP4, common source node VDDR and the MN1 of MP8, MN2, the common Gate node V2 charging of MP8 is with the current potential lifting of VDDR and V2, thereby make MN1, MN2, MP1, the MP2 conducting also produces bias current PTAT, bias current makes the MP5 conducting and obtains correct bias through current mirroring circuit 104 again, make that MP5 can be to bias current generating circuit 102, reference voltage generating circuit 103 and current mirroring circuit 104 are powered, in case the MP5 conducting, also conducting of PMOS pipe MP9, with MP10, MP11, the current potential of the common grid node V1 of MP12 is drawn high, and makes MP10, MP11, MP12 ends, and starts to finish, and entire circuit enters normal operating conditions.

Figure 3 shows that the capable figure of antijamming capability ripple of circuit, horizontal ordinate is the time, ordinate is a decibel (db), vbgvm is the anti-interference AC wave shape of reference voltage, vddrvm is the anti-interference AC wave shape of the voltage of node VDDR, exchange input on VHV, VBG is under 1,000,000 now frequencies, and antijamming capability reaches-50db;

Figure 4 shows that the startup and the operate as normal oscillogram of circuit, horizontal ordinate is the time, and ordinate is a voltage, and Vhv is the dc high voltage waveform of outside input, the reference voltage waveform of Vbg for producing, and Vddr is the voltage waveform of node VDDR.

Claims

1. reference voltage and bias current generating circuit, it is characterized in that, comprise the startup cut-off circuit (101) of circuit connection successively, bias current generating circuit (102), reference voltage generating circuit (103), also comprise the current mirroring circuit (104) that circuit connects described bias current generating circuit (102), circuit connects described startup cut-off circuit (101) respectively, bias current generating circuit (102), the low pressure bias power supply circuit (105) of reference voltage generating circuit (103) and current mirroring circuit (104), and circuit connects the bias current output circuit (106) of described current mirroring circuit (104);

Bias current generating circuit (102) produces bias current PTAT;

Bias current flows through reference voltage generating circuit (103), produces reference voltage V BG;

Current mirroring circuit (104) is given low pressure bias power supply circuit (105) and bias current output circuit (106) with bias current PTAT mirror-Symmetrical Copying Technique, electric current is provided for bias current generating circuit (102), reference voltage generating circuit (103) and current mirroring circuit (104) by low pressure bias power supply circuit (105), bias current output circuit (106) then is transferred to bias current PTAT internal circuit and other circuit of power chip;

Start cut-off circuit (101) generation starting current and be transferred to bias current generating circuit (102), make bias current generating circuit (102) conducting and produce bias current PTAT, bias current passes through current mirroring circuit (104) again and makes (105) conducting of low pressure bias power supply circuit and obtain correct bias, make that low pressure bias power supply circuit (105) can be to bias current generating circuit (102), reference voltage generating circuit (103) and current mirroring circuit (104) are powered, in case low pressure bias power supply circuit (105) conducting, start cut-off circuit (101) and produce pick-off signal, start and finish, entire circuit enters normal operating conditions;

Described bias current generating circuit (102) and reference voltage generating circuit (103) are low-voltage circuit;

Described current mirroring circuit (104), low pressure bias power supply circuit (105) and bias current output circuit (106) are high-tension circuit.

2. a kind of reference voltage as claimed in claim 1 and bias current generating circuit, it is characterized in that, P-channel metal-oxide-semiconductor pipe MP1, MP2, N NMOS N-channel MOS N pipe MN1, MN2, triode Q1, Q2, P-channel metal-oxide-semiconductor pipe MP8, and resistance R 1 constituted bias current generating circuit (102), and the PTAT electric current of generation is:

Iptat＝ΔVBE/R1，

Wherein, Δ VBE=VBE_Q2-VBE_Q1, VBE_Q1 and VBE_Q2 are respectively ground level-emitting stage voltage of triode Q1 and Q2.

3. a kind of reference voltage as claimed in claim 2 and bias current generating circuit, it is characterized in that, P-channel metal-oxide-semiconductor pipe MP3, resistance R 2 and triode Q3 have constituted reference voltage generating circuit (103), the PTAT electric current that current mirror MP3 replica bias current generating circuit (102) produces, and make this bias current flow through resistance R 2 and triode Q3, thereby produce reference voltage be:

VBG＝VBE_Q3+(R2/R1)×ΔVBE，

Wherein, VBE_Q3 is ground level-emitting stage voltage of triode Q3.