CN207352505U - A kind of non-resistance formula high-precision low-power consumption a reference source - Google Patents
A kind of non-resistance formula high-precision low-power consumption a reference source Download PDFInfo
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- CN207352505U CN207352505U CN201721080404.1U CN201721080404U CN207352505U CN 207352505 U CN207352505 U CN 207352505U CN 201721080404 U CN201721080404 U CN 201721080404U CN 207352505 U CN207352505 U CN 207352505U
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- nmos tube
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Abstract
A kind of non-resistance formula high-precision low-power consumption a reference source, belongs to technical field of power management.Start-up circuit enables reference circuit to work normally in circuit initial phase；Bias current of the reference current that bias current generating circuit produces as reference voltage generating circuit, while the bias voltage of high order compensation circuit is also served as, the bias current of generation can realize high-order compensation and automatic biasing demand；Collector current of the negative temperature coefficient voltage generation section by the use of bias current as BJT in reference voltage generating circuit, obtained negative temperature coefficient voltage VCTATRelative to traditional VBEGreatly reduce VBESubzero temperature characteristic, positive temperature coefficient voltage VPTATWith negative temperature coefficient voltage VCTATSuperposition obtains reference voltage.In addition high order compensation circuit is introduced, to obtain the more preferable reference voltage of temperature characterisitic；Output par, c increase low-pass filter circuit is used for improving the power supply rejection ratio PSRR of reference circuit.The a reference source of the utility model can realize nanowatt level power consumption, and not have resistance, reduce chip area.
Description
Technical field
The utility model belongs to technical field of power management, and in particular to a kind of non-resistance formula high-precision low-power consumption a reference source
The design of circuit.
Background technology
Nucleus module of a reference source as electronic system, is analog-digital converter (ADC), digital analog converter (DAC), linear steady
Indispensable portion in numerous circuits such as depressor, switching regulator, temperature sensor, secondary battery protective chip and telecommunication circuit
Point, provide derived reference signal that is accurate, stablizing for circuit.
With electronic system, especially battery powered or self-contained electric system, for example environmental sensor network, collection of energy
System, bioelectronics system etc., to the increasingly urgent of low-voltage and low-power dissipation requirement, reduce a reference source power consumption and keeps the steady of a reference source
It is qualitative of increased attention.Since the obtained reference output voltage of traditional bandgap structure is 1.2V or so, it is desirable to
The minimum supply voltage of a reference source limits the application range of a reference source at least in 1.5V or so；In addition the use of resistance can increase
The area of concrete-cored, so as to increase the design cost of chip.
Utility model content
The purpose of this utility model be in order to solve the restricting relation between existing a reference source power consumption and performance, it is especially low
It can not meet high accuracy and high PSRR demand under power consumption.Set forth herein a kind of non-resistance high-precision low-power consumption benchmark
Source, under nanowatt level power consumption, constructs high-order compensation non-resistance a reference source, its power supply rejection ratio gets a promotion, and realizes high-precision
Spend a reference source output.
The technical solution of the utility model is：
A kind of non-resistance formula high-precision low-power consumption a reference source, including start-up circuit, bias current generating circuit, reference voltage
Generation circuit, high order compensation circuit and low-pass filter circuit, the output terminal of the start-up circuit connect the bias current and produce
The control terminal of circuit, the output terminal of the reference voltage generating circuit pass through output reference voltage Vref after low-pass filter circuit；
The bias current generating circuit includes the second NMOS tube MN2, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the
Three PMOS tube MP3 and the 4th PMOS tube MP4,
Control terminal of the drain electrode of 3rd PMOS tube MP3 as the bias current generating circuit, its grid meet the 4th PMOS
The grid of pipe MP4 and drain electrode and the drain electrode of the 4th NMOS tube MN4；
The grid of 4th NMOS tube MN4 connects grid and the drain electrode of the second NMOS tube MN2, its source electrode connects the 5th NMOS tube
The grid of MN5 and drain electrode；
The source electrode of 3rd PMOS tube MP3 and the 4th PMOS tube MP4 meets supply voltage VDD, the second NMOS tube MN2 and the 5th
The source electrode ground connection GND of NMOS tube MN5；
The reference voltage generating circuit includes the 6th NMOS tube MN6, the 5th PMOS tube MP5 and the first triode Q1,
The grid of 5th PMOS tube MP5 connects the grid of the 3rd PMOS tube MP3 in the bias current generating circuit, its source
Pole meets supply voltage VDD, its drain connection the 6th NMOS tube MN6 grid and drain and be used as the reference voltage generating circuit
Output terminal；The emitter of first triode Q1 connects the source electrode of the 6th NMOS tube MN6, its base stage and grounded collector GND；
The high order compensation circuit includes the 3rd NMOS tube MN3, the 7th NMOS tube MN7 and the 8th NMOS tube MN8,
The grid leak short circuit of 3rd NMOS tube MN3 and the output for connecting the grid and the start-up circuit of the 7th NMOS tube MN7
End, its source electrode connect the grid of the second NMOS tube MN2 in the bias current generating circuit；The grid leak of 8th NMOS tube MN8 is short
Connect and connect the output terminal of the reference voltage generating circuit, its source electrode connects the drain electrode of the 7th NMOS tube MN7；7th NMOS tube
The source electrode of MN7 connects the source electrode of the 6th NMOS tube MN6 in the reference voltage generating circuit.
Specifically, the start-up circuit includes the first NMOS tube MN1, the first PMOS tube MP1 and the second PMOS tube MP2,
The grid of second PMOS tube MP2 connects the drain electrode of the grid and the first PMOS tube MP1 of the first NMOS tube MN1, it is leaked
Output terminal of the pole as the start-up circuit；
The source electrode of first PMOS tube MP1 and the second PMOS tube MP2 meet supply voltage VDD, the drain electrode of the first NMOS tube MN1 and
The grounded-grid GND of source electrode and the first PMOS tube MP1.
Specifically, the low-pass filter circuit includes the 9th NMOS tube MN9 and the tenth NMOS tube MN10,
The drain electrode of 9th NMOS tube MN9 connects the output terminal of the reference voltage generating circuit, its grid connects its source electrode
With the grid of the tenth NMOS tube MN10 and export the reference voltage V ref, the source electrode and grounded drain of the tenth NMOS tube MN10
GND。
Specifically, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4,
Five NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS
Pipe MN10, the first PMOS tube MP1, the second PMOS tube MP2, the 3rd PMOS tube MP3, the 4th PMOS tube MP4 and the 5th PMOS tube MP5
It is operated in sub-threshold region.
The operation principle of the utility model is：
Start-up circuit causes the coherent signal of bias current generating circuit to work normally in circuit initial phase, so as to produce
Raw bias current so that reference circuit can work normally.
Bias current generating circuit mainly produces the bias current of reference circuit, the biasing as reference voltage generating circuit
Electric current, while the bias voltage of high order compensation circuit is also served as, the bias current of generation can realize high-order compensation and automatic biasing
Demand.
Reference voltage generating circuit includes positive temperature coefficient voltage generation section and negative temperature coefficient voltage generation section, its
Collector current of the middle negative temperature coefficient voltage generation section by the use of bias current as BJT, obtained negative temperature coefficient voltage
VCTATRelative to traditional VBE, positive warm item is introduced, greatly reduces VBESubzero temperature characteristic.Positive temperature coefficient voltage VPTATAnd subzero temperature
Spend coefficient voltages VCTATSuperposition obtains reference voltage.
In addition the reference circuit introduces high order compensation circuit, to obtain the more preferable reference voltage of temperature characterisitic.Output section
Increase low-pass filter circuit is divided to be used for improving the power supply rejection ratio PSRR of reference circuit.
The beneficial effects of the utility model：High order compensation circuit is added on the basis of traditional subthreshold value benchmark, not
The temperature characterisitic of reference voltage is improved on the premise of increase power consumption；Subzero temperature voltage is produced using BJT to reduce technologic drift
Move, while the power supply rejection ratio of whole base modules is improved using the RC wave filters being made of metal-oxide-semiconductor, produce high precision reference
Voltage；Nanowatt level power consumption is realized, does not have resistance in circuit, reduces chip area, reduce the design cost of chip.
Brief description of the drawings
Fig. 1 be the utility model proposes low-voltage and low-power dissipation non-resistance formula high precision reference source equivalent architectures figure.
Fig. 2 is that the one kind in the low-voltage and low-power dissipation non-resistance formula high precision reference source in embodiment realizes circuit diagram.
MP1, MP2, MP3, MP4, MP5 manage for PMOS (P-Metal-Oxide-Semiconductor)；MN1、MN2、MN3、
MN4, MN5, MN6, MN7, MN8, MN9, MN10 manage for NMOS (N-Metal-Oxide-Semiconductor).
Embodiment
The utility model is further elaborated with specific embodiment below in conjunction with the accompanying drawings.
The utility model proposes non-resistance formula high precision reference source circuit figure as shown in Fig. 2, including start-up circuit, biasing
Current generating circuit, reference voltage generating circuit, high order compensation circuit and low-pass filter circuit, the start-up circuit in the present embodiment
Including the grid of the first NMOS tube MN1, the first PMOS tube MP1 and the second PMOS tube MP2, the second PMOS tube MP2 connection first
The drain electrode of the grid of NMOS tube MN1 and the first PMOS tube MP1, its output terminal to drain as the start-up circuit；First PMOS
The source electrode of pipe MP1 and the second PMOS tube MP2 meet supply voltage VDD, the drain electrode of the first NMOS tube MN1 and source electrode and the first PMOS
The grounded-grid GND of pipe MP1.
Boot leg is when circuit initializes, the grounded-grid of the first PMOS tube MP1, and the first PMOS tube MP1 is to first
NMOS tube MN1 charges, and the first NMOS tube MN1 is used as start-up capacitance, at this time the grid of the first NMOS tube MN1 i.e. the 2nd PMOS
The grid potential of pipe MP2 is low, and the second PMOS tube MP2 conductings, the electric current that the second PMOS tube MP2 is produced causes the second NMOS tube
The grid potential of MN2 is raised, and bias current produces the normal foundation in part, whole reference circuit normal work；When NMOS capacitor is
During the first NMOS tube MN1 charging completes, the grid potential of the second PMOS tube MP2 is driven high, and pipe shut-off, boot leg exits,
Reference circuit works normally.
Bias current generating circuit includes the 3rd PMOS tube MP3, the 4th PMOS tube MP4, the second NMOS tube MN2, the 4th
NMOS tube MN4 and the 5th NMOS tube MN5, utilizes the second NMOS tube MN2, the 4th NMOS tube MN4 for working in sub-threshold region and
Five NMOS tube MN5 produce the electric current with positive temperature characteristics, the electric current as the 5th PMOS tube MP5 in reference voltage generating circuit,
The bias current of 6th NMOS tube MN6 and the first triode Q1.The gate source voltage of second NMOS tube MN2 pipes is through the 4th NMOS tube
MN4 and the 5th NMOS tube MN5 divide equally, and the 4th NMOS tube MN4 and the 5th NMOS tube MN5 produce electric current as the 4th PMOS tube MP4
Drain current.
The bias current and the second NMOS tube MN2, the 4th NMOS that bias current generating circuit produces are derived in detail below
The temperature characterisitic of pipe MN4 and the 5th NMOS tube MN5 grid potentials.When benchmark establish complete when, the grid of the second NMOS tube MN2 and
Drain potential is height, and the 4th NMOS tube MN4 and the 5th NMOS tube MN5 produce electric current ID1, ID1It is through the 4th PMOS tube MP4 mirror images
It is I that second NMOS tube MN2, which provides bias current,D2.All metal-oxide-semiconductors of reference circuit all work in sub-threshold region, by the second NMOS tube
MN2, the 4th NMOS tube MN4 and the 5th NMOS tube MN5 sub-threshold regions current formula can obtain：
Wherein, VTHFor threshold voltage, VTFor thermal voltage, m is the sub-threshold slope factor, ID2=K1ID1, K1 is the 3rd PMOS
The image ratio of pipe MP3 and the 4th PMOS tube MP4, the grid potential of the second NMOS tube MN2 is VG, the grid of the 5th NMOS tube MN5
Current potential is VG1, SMNiFor the breadth length ratio of transistor MNi, ISQThe subthreshold region saturation current for the unit transistor for being 1/1 for breadth length ratio.
Sub-threshold region is worked in view of the second NMOS tube MN2, its grid potential VGCurrent potential is relatively low, the 5th NMOS tube MN5
Grid potential VG1It is lower, then the drain-source voltage V of the 5th NMOS tube MN5DS_MN54V may be less thanT, therefore in the 5th NMOS tube
V is included inside the drain current formula of MN5DS_MN5Influence.
In standard CMOS process, NMOS tube substrate electric potential is typically grounded, and the 4th NMOS tube MN4 serves as a contrast inclined influence and causes it
Threshold voltage and the 5th NMOS tube MN5 are unequal.Consider that the 4th NMOS tube MN4 serves as a contrast inclined influence, can with reference to formula (1) and (3)
：
WhereinFor Fermi potential, γ is the bulk effect factor.
The grid potential V of the 5th NMOS tube MN5 can be obtained by arrangingG1, the second NMOS tube MN2 grid potential VGExpression formula：
It can be obtained by formula (5), the grid potential VG1 of the 5th NMOS tube MN5 is the voltage (PTAT with absolute temperature is proportional to
Voltage), its temperature coefficient is related with the breadth length ratio and image ratio K1 of the second NMOS tube MN2 and the 4th NMOS tube MN4.Second
The grid potential VG of NMOS tube MN2 is also voltage (PTAT voltage) with absolute temperature is proportional to, its temperature coefficient not only with MOS
Pipe, K1 are related, its positive temperature characteristics is also related to sub-threshold slope factor m, therefore, the grid potential VG's of the second NMOS tube MN2
Positive temperature characteristics should be affected by temperature greatly than the grid potential VG1 of the 5th NMOS tube MN5.
Formula (5), (6) are substituted into formula (2) and obtain reference bias current ID1：
Temperature independent item is proposed, abbreviation can obtain：
Wherein, coefficient a, b is temperature independent, with the second NMOS tube MN2, the 4th NMOS tube MN4 and the 5th NMOS tube MN5
Size is related (being more than 0).N1 is metal-oxide-semiconductor mobility temperature power term coefficient, less than 2；VTHIt is remote with subzero temperature characteristic, its subzero temperature
More than mVTPositive temperature characteristics, general performance is positive temperature characteristics in exponential term；Therefore, the bias current I of reference circuitD1With just
Temperature characteristics.
Reference voltage generating circuit includes positive temperature coefficient voltage generation section and negative temperature voltage generation section, positive temperature
Coefficient voltages VPTATProduced by the 6th NMOS tube MN6, the drain current of the 6th NMOS tube MN6 is by bias current through the 5th PMOS tube
MP5 mirror images provide, image ratio K2.6th NMOS tube MN6 works in sub-threshold region, it can thus be concluded that the pipe gate source voltage expression formula
For：
By bias current I in formula (8)D1Substituting into above formula can obtain：
If ignoring the inclined influence of the 6th NMOS tube MN6 linings, positive temperature coefficient voltage V in the reference circuitPTATExpression formula
For：
From formula (11), if without considering the influence of sub-threshold slope factor m, positive temperature coefficient voltage VPTATJust
Temperature characteristics are related to the second NMOS tube MN2, the 5th NMOS tube MN5, the 4th NMOS tube MN4 and image ratio K1.Since subthreshold value is oblique
Rate factor m has positive temperature characteristics, and especially at high temperature, positive temperature characteristics sharply increase.Therefore, positive temperature coefficient voltage VPTAT
Positive warm nature may increase with increased temperature.
Negative temperature coefficient voltage VCTATTied and produced by the BE of i.e. the first triode Q1 of BJT, the collector current of BJT is by biasing
Electric current is provided through the 5th PMOS tube MP5 mirror images, image ratio K2.It can thus be concluded that VBEThat is negative temperature coefficient voltage VCTATFor：
Wherein ISFor BJT reverse saturation currents, c is temperature independent constant.
Formula (12) expansion can be obtained：
Wherein TrFor reference temperature, βTHFor threshold voltage temperature coefficient, VTH0For 0K when threshold voltage value, n2 is internal
Mobility temperature power, VgFor semiconductor energy gap.
From formula (13), the bias current of BJT is K2ID1When, negative temperature coefficient voltage VCTATThe positive temperature item of addition (a,
b、βTH) so that negative temperature coefficient voltage VCTATSubzero temperature characteristic reduce.On the other hand, the negative temperature coefficient produced with traditional BJT
Voltage is compared, negative temperature coefficient voltage VCTATSubtract VTH0So that the supply voltage needed for the BJT reduces.
High order compensation circuit includes the 3rd NMOS tube MN3, the 7th NMOS tube MN7 and the 8th NMOS tube MN8, for correcting just
Temperaturecoefficient voltage VPTATTo improve the temperature characterisitic of reference voltage.Since bias current has positive temperature characteristics, the second NMOS tube
The grid potential of MN2 is the voltage with absolute temperature is proportional to, therefore, the grid of the 3rd NMOS tube MN3 (working in sub-threshold region)
(leakage) pole tension has positive temperature characteristics.Temperature raises, the gate source voltage increase of the 3rd NMOS tube MN3, when more than the 7th NMOS tube
During the threshold voltage of MN7, the conducting of the 7th NMOS tube MN7 pipes, then the 8th NMOS tube MN8 conductings, high-order compensation addition.High-order compensation
Add, the breadth length ratio increase equivalent to the 6th NMOS tube MN6, then positive temperature coefficient voltage VPTATPositive temperature characteristics weaken.
Low-pass filter circuit in the present embodiment includes the 9th NMOS tube MN9 and the tenth NMOS tube MN10, the 9th NMOS tube
The drain electrode of MN9 connects the output terminal of the reference voltage generating circuit, its grid connects its source electrode and the tenth NMOS tube MN10
Source electrode simultaneously exports the reference voltage V ref, the source electrode and grounded drain GND of the tenth NMOS tube MN10.
9th NMOS tube MN9 works in cut-off region and is used quite as mos capacitance equivalent to resistance, the tenth NMOS tube MN10
In capacitance, therefore, RC low-pass filters are formed.Increase low-pass filter circuit can improve power supply of the reference voltage at higher-frequency
Suppress than (PSRR).
Those of ordinary skill in the art can these technical inspirations according to disclosed in the utility model make and various not taking off
From the other various specific deformations and combination of the utility model in essence, these deformations and combination are still in the protection of the utility model
In the range of.
Claims (4)
1. a kind of non-resistance formula high-precision low-power consumption a reference source, it is characterised in that produce electricity including start-up circuit, bias current
Road, reference voltage generating circuit, high order compensation circuit and low-pass filter circuit, the output terminal connection of the start-up circuit are described partially
The control terminal of current generating circuit is put, the output terminal of the reference voltage generating circuit passes through output reference after low-pass filter circuit
Voltage Vref；
The bias current generating circuit includes the second NMOS tube MN2, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 3rd
PMOS tube MP3 and the 4th PMOS tube MP4,
Control terminal of the drain electrode of 3rd PMOS tube MP3 as the bias current generating circuit, its grid meet the 4th PMOS tube MP4
Grid and drain electrode and the 4th NMOS tube MN4 drain electrode；
The grid of 4th NMOS tube MN4 connects grid and the drain electrode of the second NMOS tube MN2, its source electrode connects the 5th NMOS tube MN5
Grid and drain electrode；
The source electrode of 3rd PMOS tube MP3 and the 4th PMOS tube MP4 connects supply voltage VDD, the second NMOS tube MN2 and the 5th NMOS tube
The source electrode ground connection GND of MN5；
The reference voltage generating circuit includes the 6th NMOS tube MN6, the 5th PMOS tube MP5 and the first triode Q1,
The grid of 5th PMOS tube MP5 connects the grid of the 3rd PMOS tube MP3 in the bias current generating circuit, its source electrode connects
Supply voltage VDD, the grid of its 6th NMOS tube MN6 of connection that drains is with drain electrode and as the defeated of the reference voltage generating circuit
Outlet；The emitter of first triode Q1 connects the source electrode of the 6th NMOS tube MN6, its base stage and grounded collector GND；
The high order compensation circuit includes the 3rd NMOS tube MN3, the 7th NMOS tube MN7 and the 8th NMOS tube MN8,
The grid leak short circuit of 3rd NMOS tube MN3 simultaneously connects the grid of the 7th NMOS tube MN7 and the output terminal of the start-up circuit, its
Source electrode connects the grid of the second NMOS tube MN2 in the bias current generating circuit；The grid leak short circuit of 8th NMOS tube MN8 and company
The output terminal of the reference voltage generating circuit is connect, its source electrode connects the drain electrode of the 7th NMOS tube MN7；7th NMOS tube MN7's
Source electrode connects the source electrode of the 6th NMOS tube MN6 in the reference voltage generating circuit.
2. non-resistance formula high-precision low-power consumption a reference source according to claim 1, it is characterised in that the start-up circuit bag
The first NMOS tube MN1, the first PMOS tube MP1 and the second PMOS tube MP2 are included,
The grid of second PMOS tube MP2 connects the drain electrode of the grid and the first PMOS tube MP1 of the first NMOS tube MN1, it, which drains, makees
For the output terminal of the start-up circuit；
The source electrode of first PMOS tube MP1 and the second PMOS tube MP2 connect supply voltage VDD, the drain electrode of the first NMOS tube MN1 and source electrode
And first PMOS tube MP1 grounded-grid GND.
3. non-resistance formula high-precision low-power consumption a reference source according to claim 2, it is characterised in that the low-pass filtering electricity
Road includes the 9th NMOS tube MN9 and the tenth NMOS tube MN10,
The drain electrode of 9th NMOS tube MN9 connects the output terminal of the reference voltage generating circuit, its grid connects its source electrode and the
The grid of ten NMOS tube MN10 simultaneously exports the reference voltage V ref, the source electrode and grounded drain GND of the tenth NMOS tube MN10.
4. non-resistance formula high-precision low-power consumption a reference source according to claim 3, it is characterised in that first NMOS tube
MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6,
Seven NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the first PMOS tube MP1, the 2nd PMOS
Pipe MP2, the 3rd PMOS tube MP3, the 4th PMOS tube MP4 and the 5th PMOS tube MP5 are operated in sub-threshold region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721080404.1U CN207352505U (en) | 2017-08-22 | 2017-08-22 | A kind of non-resistance formula high-precision low-power consumption a reference source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721080404.1U CN207352505U (en) | 2017-08-22 | 2017-08-22 | A kind of non-resistance formula high-precision low-power consumption a reference source |
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| CN207352505U true CN207352505U (en) | 2018-05-11 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107340796A (en) * | 2017-08-22 | 2017-11-10 | 成都信息工程大学 | A kind of non-resistance formula high-precision low-power consumption a reference source |
| CN109254188A (en) * | 2018-10-09 | 2019-01-22 | 成都信息工程大学 | A kind of high-speed current detection circuit suitable for Switching Power Supply |
| CN110502061A (en) * | 2018-05-19 | 2019-11-26 | 丹阳恒芯电子有限公司 | A kind of super low-power consumption reference circuit |
| CN112286337A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption bandgap circuit for MCU and implementation method thereof |
-
2017
- 2017-08-22 CN CN201721080404.1U patent/CN207352505U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107340796A (en) * | 2017-08-22 | 2017-11-10 | 成都信息工程大学 | A kind of non-resistance formula high-precision low-power consumption a reference source |
| CN110502061A (en) * | 2018-05-19 | 2019-11-26 | 丹阳恒芯电子有限公司 | A kind of super low-power consumption reference circuit |
| CN109254188A (en) * | 2018-10-09 | 2019-01-22 | 成都信息工程大学 | A kind of high-speed current detection circuit suitable for Switching Power Supply |
| CN109254188B (en) * | 2018-10-09 | 2023-12-01 | 成都铱通科技有限公司 | High-speed current detection circuit suitable for switching power supply |
| CN112286337A (en) * | 2020-10-30 | 2021-01-29 | 广州鸿博微电子技术有限公司 | Low-power-consumption bandgap circuit for MCU and implementation method thereof |
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Granted publication date: 20180511 Effective date of abandoning: 20190101 |