CN202041870U - Band-gap reference voltage source without resistors - Google Patents

Abstract

The utility model discloses a band-gap reference voltage source without resistors, which specifically comprises a start-up circuit, an automatic biasing current source circuit and a voltage follower with PTAT (proportional to absolute temperature) imbalance. The start-up circuit is connected with the automatic biasing current source circuit, and the voltage follower with the PTAT imbalance is connected with the automatic biasing current source circuit. As a circuit structure does not adopt the resistors, the band-gap reference voltage source can be compatible to CMOS (complementary metal-oxide semiconductor) process, design complexity is reduced, and the area of a chip is reduced. In addition, by the aid of the automatic biasing current source circuit and the voltage follower with the PTAT imbalance, the power supply rejection ratio of the band-gap reference voltage source is increased while reference voltage has lower temperature coefficients.

Description

A kind of bandgap voltage reference of non-resistance

Technical field

The utility model belongs to power technique fields, is specifically related to a kind of design of bandgap voltage reference.

Background technology

In the design process of reference voltage source, usually employing produces reference voltage based on the technology of the band gap voltage generation fixed voltage of silicon, its principle is, the voltage of a positive temperature coefficient (PTC) and the voltage of a negative temperature coefficient are superposeed in certain proportion, produce not magnitude of voltage with environment temperature, mains voltage variations.When temperature during near 0K, this reference voltage is called " band-gap reference " voltage near the band gap voltage of silicon.

The voltage of positive temperature coefficient (PTC) comes from the difference Δ V of the base-emitter voltage of two DJ transistors usually _BE, the voltage of negative temperature coefficient promptly is the base-emitter voltage V of DJ transistor _BE, these two voltages will superpose in certain proportion, and ability compensation temperature coefficient makes the voltage that obtains have reasonable temperature characterisitic.Reference voltage can be expressed as:

V _BEF=V _BE+ K * Δ V _BEFormula (1)

COEFFICIENT K in the formula (1) is the ratio of two resistance of the same type normally.And the digital circuit of standard does not provide corresponding Resistance model for prediction, can realize that the method for equivalent resistance solves with switching capacity here, but needs extra circuit to come clocking, has increased the complexity of circuit, can introduce noise simultaneously; The chip internal integrated capacitance can increase the area of chip layout again, increases cost.

Document " Buck A E; McDonald C L; Lewis H.et al.A CMOS bandgap reference without resistors.IEEE JOURNAL of Solid-State Circuits; 2002.37 (1): 81-83 " has solved above problem well, MOS in the circuit structure all works in strong inversion or cut-off region, so there is not the problem of device model accuracy.But the required supply voltage of circuit operate as normal is too high, is not suitable for the low pressure applications environment; Power Supply Rejection Ratio is not high, and temperature characterisitic neither be fine; In order to suppress the channel length modulation effect of metal-oxide-semiconductor, have to increase the channel length of device, thereby increased area of chip.Document " Tetsuya Hiros; et al.Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs; IEICE Electronics Express; Vol.5; No.6; pp.204-210, Mar.2008 " the band-gap reference source circuit of the non-resistance that proposes; the part metal-oxide-semiconductor works in sub-threshold region; but in this interval not precise analytic model the characteristic of metal-oxide-semiconductor is not described, thereby increased the complexity of design.

The utility model content

The purpose of this utility model is the problem that exists for the band-gap reference source circuit that solves existing non-resistance, has proposed a kind of Bandgap Reference Without Resistors.

Technical solutions of the utility model are: a kind of Bandgap Reference Without Resistors, comprise start-up circuit, the self-bias current source circuit, with the voltage follower circuit that has the PTAT imbalance, wherein, start-up circuit is connected with the self-bias current source circuit, and the voltage follower that has the PTAT imbalance links to each other with the self-bias current source circuit.

Further, the self-bias current source circuit comprises PMOS pipe MP1, MP2, MP3, NMOS manages MN1, MN2, MN3, MN4, MN6, triode Q1, Q2, Q3, wherein, the source electrode of PMOS pipe and substrate all connect external power source, the equal ground connection of the substrate of NMOS pipe, the equal ground connection of the base stage of triode and collector, the grid leak short circuit of PMOS pipe MP3, be connected with the grid of MP1 and MP2 simultaneously, PMOS manages MP1, MP2, the drain electrode of MP3 is managed MN1 with NMOS respectively, MN3, the drain electrode of MN4 connects, the drain electrode of MP3 is as the Vbias point of self-bias current source circuit, NMOS pipe MN1 grid leak short circuit, and be connected with the grid of MN2 and MN3, the source electrode of MN1 is connected with the drain electrode of MN2, the source electrode of NMOS pipe MN2 is connected with the emitter of triode Q1, the drain electrode of NMOS pipe MN3 is connected with the grid of MN4, the grid that connects MN6 simultaneously, the source electrode of NMOS pipe MN6 is connected with the emitter of triode Q2, the positive input that connects the voltage follower that has the PTAT imbalance simultaneously, the source electrode of NMOS pipe MN4 is connected the source electrode of MN6 and grounded drain with the emitter of triode Q3.

Further, the voltage follower that has the PTAT imbalance comprises NMOS pipe M1, M2, first current source, second current source, the 3rd current source and current mirror, wherein, the grid of NMOS pipe M1 and M2 is respectively as the forward and the negative input of voltage follower, drain electrode is connected with the second current source anode with first current source respectively, ground connection behind source series the 3rd current source, first current source, the negative terminal of second current source connects external power source respectively, anode is by power supply mirror ground connection, described first current source, the ratio of the size of current of second current source and the 3rd current source is A+1: B+1: A+B.

Further, the voltage follower that has the PTAT imbalance comprises 10 PMOS pipe MPA1-MPA10,12 NMOS pipe MNA1-MNA12, wherein, the equal ground connection of substrate of all NMOS pipes, the source electrode of MPA1-MPA6 and substrate all connect external power source, the grid of MPA1-MPA5 interconnects, and the Vbias point of connection self-bias current source circuit, the drain electrode of MPA1 is connected with the drain electrode of MNA1, the source electrode of MNA1 and substrate ground connection, its grid leak short circuit, and with MNA2, MNA4, MNA6, the grid of MNA8 connects, the grid leak short circuit of MPA6, and connect MPA7 and the grid of MPA8 and the drain electrode of MNA2, the source electrode of MNA2 is connected with the drain electrode of MNA3, the source ground of MNA3, its grid and MNA5, MNA7, the grid of MNA9 and the drain electrode of MNA6 connect, the drain electrode of MPA2 is connected with the grid of the source electrode of MPA9 and MNA10, the substrate of MPA9 is connected with the source, its grid is the positive input of voltage follower, drain electrode connects external power source, the drain electrode of MPA3 is connected with the grid of the source electrode of MPA10 and MNA11, the source electrode of MPA10 and substrate short circuit, its grid is the negative input of voltage follower, grounded drain, the source electrode of MNA10 and MNA11 interconnects, and connect the drain electrode of MNA4, the source electrode of MNA4 is connected with the drain electrode of MNA5, the source ground of MNA5, MNA10 and the drain electrode of MNA11 are connected the drain electrode of MPA4 and MPA5 respectively, the source electrode of MPA7 and MPA8 and substrate short circuit, and connect the drain electrode of MPA4 and MPA5 respectively, the drain electrode of MPA7 is connected with the drain electrode of MNA6, the source electrode of MNA6 is connected with the drain electrode of MNA7, the source ground of MNA7, and the drain electrode of MPA8 is connected with the drain electrode of MNA8, the source electrode of MNA8 is connected with the drain electrode of MNA9 and as the output terminal of voltage follower, the source electrode of MNA9 connects external power source, and connects the grid of MNA12, the source electrode of MNA12 and the equal ground connection of drain electrode.

The beneficial effects of the utility model are: the Bandgap Reference Without Resistors that the utility model provides, because circuit structure does not use resistance, thereby can be compatible mutually with CMOS technology, and then reduced the complexity that designs, reduced area of chip; Reference voltage source of the present utility model in addition is by described self-bias current source circuit and have the voltage follower that PTAT lacks of proper care, and makes reference voltage when having lower temperature coefficient, has improved the Power Supply Rejection Ratio of band gap reference.

Description of drawings

Fig. 1 is the circuit diagram of non-resistance band gap reference of the present utility model.

Fig. 2 is the schematic diagram that has the follower of PTAT offset voltage of the present utility model.

Fig. 3 is the physical circuit figure that has the follower of PTAT offset voltage of the present utility model.

Fig. 4 is the emulation synoptic diagram of the non-resistance band gap reference temperature characterisitic of the utility model embodiment.

Fig. 5 is the emulation synoptic diagram of the non-resistance band gap reference voltage regulation factor of the utility model embodiment.

Fig. 6 is the emulation synoptic diagram of the non-resistance band gap reference Power Supply Rejection Ratio of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the utility model is further elaborated.

As shown in Figure 1, Bandgap Reference Without Resistors comprises start-up circuit, self-bias current source circuit and have the voltage follower circuit of PTAT imbalance, wherein, start-up circuit is connected with the self-bias current source circuit, and the voltage follower that has the PTAT imbalance links to each other with the self-bias current source circuit.

Here, self-bias current source circuit such as figure comprise PMOS pipe MP1, MP2, MP3, NMOS manages MN1, MN2, MN3, MN4, MN6, triode Q1, Q2, Q3, wherein, the source electrode of PMOS pipe and substrate all connect external power source, the equal ground connection of the substrate of NMOS pipe, the equal ground connection of the base stage of triode and collector, the grid leak short circuit of MP3 is connected with the grid of MP1 and MP2 simultaneously, MP1, MP2, the drain electrode of MP3 respectively with MN1, MN3, the drain electrode of MN4 connects, the drain electrode of MP3 is as the Vbias point of self-bias current source circuit, MN1 grid leak short circuit, and be connected with the grid of MN2 and MN3, the source electrode of MN1 is connected with the drain electrode of MN2, the source electrode of MN2 is connected with the emitter of Q1, and the drain electrode of MN3 is connected with the grid of MN4, connects the grid of MN6 simultaneously, the source electrode of MN6 is connected with the emitter of Q2, connect the positive input of the voltage follower that has the PTAT imbalance simultaneously, the source electrode of MN4 is connected with the emitter of Q3, the source electrode of MN6 and grounded drain VSS.

The follower that has the PTAT offset voltage is as collapsible cascode differential operational amplifier, and operational amplifier is to connect in the voltage follower mode, so it is output as:

V _BEF=V _BE(Q)+V _OS=V _BE(Q)+L * V _PTATFormula (2)

The middle L of formula (2) is temperature independent constant, V _BEIn negative temperature coefficient item V _BE(Q) and the V of positive temperature coefficient (PTC) _PTATStack in certain proportion, temperature coefficient is cancelled out each other, and makes V _REFMagnitude of voltage and temperature variation are irrelevant.

Start-up circuit comprises PMOS pipe MPS1, NMOS manages MS, MSN1, wherein, the source electrode of MPS1 and substrate all meet external power source VDD, and its grid is connected with the grid of MSN1, and are connected to the A point of self-bias current source, the drain electrode of MPS1 is connected with the drain electrode of MNS1, be connected to simultaneously on the grid of MS, the drain electrode of MS is connected to the Vbias point of self-bias current source circuit, the equal earthing potential VSS of the source electrode of MS and MSN1 and substrate.

Here the voltage follower that has the PTAT imbalance is actually a collapsible cascode differential operational amplifier, its the most general design proposal as shown in Figure 2, comprise NMOS pipe M1, M2, current source (A+1) I, (B+1) I, (A+B) I, with current mirror, wherein, the grid of NMOS pipe M1 and M2 is respectively the forward and the negative input of voltage follower, their drain electrode is connected with (B+1) I anode with sources (A+1) I respectively, ground connection VSS behind source series current source (A+B) I, current source (A+1) I, (B+1) negative terminal of I all meets external power source VDD, and anode is by power supply mirror ground connection VSS.Here (A+1) I, (B+1) I and (A+B) the I ratio that refers to the size of current of these three current sources be A+1: B+1: A+B, wherein, A, B are constant.

The input of voltage follower works in the saturation region to pipe, then the gate source voltage V of input pipe _GSWith bias current I _DThe pass be:

$V_{\mathrm{GS}}=V_{\mathrm{TH}}+\sqrt{\frac{{2I}_D}{\mathrm{\μ}{C}_{\mathrm{OX}}(W/L)}}$ Formula (3)

In the formula (3), V _THBe the threshold voltage of metal-oxide-semiconductor, C _OXBe gate oxide electric capacity, μ is a metal-oxide-semiconductor mobility of charge carrier rate, and W/L is the breadth length ratio of metal-oxide-semiconductor.

Because two input pipes are biased under the different electric currents, the electric current that wherein flows through M1 is AI, and the electric current that flows through M2 is BI, so the offset voltage V of input end introducing _OSFor:

$V_{\mathrm{OS}}=V_{\mathrm{IN}-}-V_{\mathrm{IN}+}=\sqrt{\frac{2\mathrm{BI}}{\mathrm{\&mu;}{C}_{\mathrm{OX}}{(W/L)}_{M_2}}}-\sqrt{\frac{2\mathrm{AI}}{\mathrm{\&mu;}{C}_{\mathrm{OX}}{(W/L)}_{{\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA0000060377100000012.png"\; state="\{\{state\}\}">M</figure-callout>}}_1}}}$ Formula (4)

A and B are constant in the formula (4).In order to make voltage source that the reasonable linearity be arranged, require the mutual conductance of input pipe M1, M2 to equate.The transconductance value of metal-oxide-semiconductor is

Thereby M1 and M2 need satisfy following formula:

$B{(W/L)}_{M_2}=A{(W/L)}_{{\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA0000060377100000012.png"\; state="\{\{state\}\}">M</figure-callout>}}_1}$ Formula (5)

Like this, M1 has identical transconductance value with M2

Formula (3) can be transformed to:

$V_{\mathrm{IN}-}-V_{\mathrm{IN}+}=M\sqrt{\frac{I}{\mathrm{\&mu;}}}$ Formula (6)

In the formula (6),

It is temperature independent amount.

The carrier mobility of metal-oxide-semiconductor and the pass of temperature are:

$\mathrm{\&mu;}=\mathrm{\&mu;}\left(T_0\right){\left(\frac{T}{T_0}\right)}^{\mathrm{\&alpha;}}$ Formula (7)

In the formula (7), μ (T ₀) that represent is T ₀Carrier mobility during temperature, the parameter alpha span is-1.5～-2, generally gets-1.5.In order to guarantee the offset voltage V of input end _OSBe PTAT voltage, electric current I and temperature T in the formula (6) need satisfy following relation:

I ∝ T ^{2+ α}Formula (8)

Because the bias current of collapsible cascode differential operational amplifier is provided by the self-bias current source circuit, so the electric current that requires the self-bias current source circuit to provide also will satisfy the requirement of formula (8).

Fig. 3 is a kind of implementation that has PTAT offset voltage follower.In order to improve Power Supply Rejection Ratio, this collapsible amplifier adopts the cascode structure.MPA9 in the circuit and MPA10 play the effect of level shift.MPA1, MPA6, MNA1, MNA2 and MNA3 constitute biasing circuit, and for follower provides biasing, the MNA12 equivalence is a mos capacitance, is used for filtering noise and stable reference voltage.

Wherein, MP1, MP2, MN1, MN2, MN3, Q1 and Q2 have formed current feedback circuit, the voltage that MP3, MN4, Q3 sampling B order, and make A point equal with the maintenance of B point voltage by negative feedback.The connection of MN6 forms a mos capacitance in the circuit, is used for stablizing loop.The ratio of the emitter area of Q1, Q2 and Q3 is respectively N in the circuit: 1: 1, MN1, MN2, MN3 and MN4 had identical breadth length ratio, and MP1, MP2 also have identical breadth length ratio with MP3, and the breadth length ratio of MN10 and MN11 satisfies A (W/L) _MN10=B (W/L) _MN11

Narration can be established (W/L) for convenience _MN1=(W/L) _MN2=(W/L) _MN3=(W/L) _MN4=(W/L) _N, (W/L) _MP1=(W/L) _MP2=(W/L) _MP3=(W/L) _PBecause the V of MN2 _GD＞V _THNSo MN2 works in linear zone.According to Kirchhoff's law:

V _{GS (MN1)}+ V _{DS (MN2)}+ V _{EB (Q1)}=V _{GS (MN3)}+ V _{EB (Q2)}Formula (9)

Because MN1, MN2 have same current density, so V _{GS (MN1)}=V _{GS (MN3)}The ratio of Q1, Q2 emitter area is N: 1, be biased under the identical electric current, so V _{EB (Q2)}-V _{EB (Q1)}=V _TLnN.V _TBe thermal voltage kT/q=26mv300K.Thereby can obtain:

V _{DS (MN2)}=V _{EB (Q2)}-V _{EB (Q1)}=V _TLnN formula (10)

MN2 works in linear zone, and flowing through electric current is I, can get:

I=μ C _OX(W/L) _N(V _{GS (MN2)}-V _TH-1/2V _{DS (MN2)}) * V _{DS (MN2)}Formula (11)

And V _{GS (MN2)}=V _{GS (MN1)}+ V _{DS (MN2)}, then formula (11) can be designated as:

I=μ C _OX(W/L) _N(V _{GS (MN1)}-V _TH+ 1/2V _{DS (MN2)}) * V _{DS (MN2)}Formula (12)

$V_{\mathrm{GS}\left(\mathrm{MN}1\right)}=\sqrt{\frac{2I}{\mathrm{\&mu;}{C}_{\mathrm{OX}}{(W/L)}_N}}+V_{\mathrm{TH}}$ Formula (13)

Formula (10) and formula (13) are updated to formula (12), can get:

$I=\mathrm{\&mu;}{C}_{\mathrm{OX}}{(W/L)}_N(\sqrt{\frac{2I}{\mathrm{\&mu;}{C}_{\mathrm{OX}}{(W/L)}_N}}+\frac{1}{2}{V}_T\ln N)V_T\ln N$ Formula (14)

Solve I from formula (14), can get:

I=JT ^{2+ α}Formula (15)

Wherein,

It is a temperature independent amount.Because this current source provides current offset for amplifier, so, can get formula (15) substitution formula (6):

$V_{\mathrm{IN}-}-V_{\mathrm{IN}+}=M\sqrt{J\frac{{T_0}^{\mathrm{\&alpha;}}}{\mathrm{\&mu;}\left(T_0\right)}}T$ Formula (16)

The offset voltage of introducing as can be seen from formula (16) is a PTAT voltage, formula (16) substitution formula (2), can get again:

$V_{\mathrm{REF}}=V_{\mathrm{EB}}+M\sqrt{J\frac{{T_0}^{\mathrm{\&alpha;}}}{\mathrm{\&mu;}\left(T_0\right)}}T$ Formula (17)

Wherein

Be a temperature independent amount, by appropriate design

These several variablees of A and B can be so that positive temperature coefficient (PTC) item and V _EBIn the negative temperature coefficient item offset, thereby make reference voltage in certain temperature range, have good temperature characterisitic.

Among Fig. 1, the voltage that MP3, MN4 in the self-bias current source circuit, Q3 sampling B orders, and regulate by feedback loop and to make A point equal with the maintenance of B point voltage, thereby suppressed metal-oxide-semiconductor channel length modulation effect.So for metal-oxide-semiconductor, long channel length is not necessary, thereby can reduce the chip area of chip.Feedback loop gain and dominant pole in the circuit are respectively:

$T_0\&ap;{\left(\frac{{\mathrm{<figure-callout\; id="1"\; label="g\; mN"\; filenames="HDA0000060377100000012.png"\; state="\{\{state\}\}">g</figure-callout>}}_{\mathrm{mN}}}{1+g_{\mathrm{mN}}/g_{\mathrm{mQ}}}\right)}^2{R}_{\mathrm{ON}\left(\mathrm{MN}2\right)}\left[(\frac{g_{\mathrm{mN}}}{g_{\mathrm{mQ}}}{r}_{\mathrm{oN}}+\frac{1}{g_{\mathrm{mQ}}}+r_{\mathrm{oN}})\right|\left|r_{\mathrm{oP}}\right]$ Formula (18)

$P_{\mathrm{do}\min \mathrm{ant}}=\frac{1}{2\mathrm{\&pi;}\left[(\frac{g_{\mathrm{mN}}}{g_{\mathrm{mQ}}}{r}_{\mathrm{oN}}+\frac{1}{g_{\mathrm{mQ}}}+r_{\mathrm{oN}})\right|\left|r_{\mathrm{oP}}\right]C_{\mathrm{MN}6}}$ Formula (19)

G in the formula _MNAnd g _MQIt is respectively the mutual conductance of NMOSFET and BJT; r _ONAnd r _OPIt is respectively the output resistance of NMOSFET and PMOSFET; C _MN6It is the mos capacitance of MN6 equivalence; R _{ON (MN2)}It is the conducting resistance of MN2.

As can be seen, bandgap voltage reference described in the utility model comprises 3 parts: start-up circuit, self-bias current source circuit and have the voltage follower of PTAT imbalance.Reference voltage V _REFPromptly be the voltage V that C is ordered _EBIntroduce offset voltage V with amplifier _OSSum.Because current source is an automatic biasing, has zero current condition, can influence the operate as normal of circuit, so need start-up circuit to break away from zero current condition.When circuit was in zero current condition, the grid potential of MP1, MP2 and MP3 was a noble potential, and the grid potential of MN1, MN2 and MN3 is an electronegative potential.This phase inverter that will make MNS1 and MPS1 form is output as noble potential, and the MS conducting drags down the grid potential of MP1, MP2 and MP3, begins to have electric current to flow through in the circuit, and circuit is broken away from zero current condition.After the circuit operate as normal, the current potential that A is ordered will make that reverser is output as electronegative potential, and MS ends, and start-up circuit no longer influences the operate as normal of main body circuit.

The simulation waveform of temperature characterisitic as shown in Figure 4.Bandgap voltage reference works under the supply voltage of 3.6v, and the reference voltage value under the normal temperature is 1.2256V.In-40 ℃ to 155 ℃ temperature range, reference voltage value has only changed 0.28%, and its temperature coefficient is 14.3ppm/ ℃.

The simulation waveform of voltage regulation factor as shown in Figure 5.The operating voltage of bandgap voltage reference changes to 5v from 2.7v, and it only is 4.51mv that its reference voltage value changes, so its line voltage regulation is 1.96mv/v.

The simulation waveform of the Power Supply Rejection Ratio of band gap reference as shown in Figure 6.Bandgap voltage reference of the present utility model has improved the Power Supply Rejection Ratio of bandgap voltage reference by self-bias current source circuit and collapsible cascode differential amplifier.1kHz frequency place, the Power Supply Rejection Ratio of bandgap voltage reference reaches 57dB; 10kHz frequency place, the Power Supply Rejection Ratio of bandgap voltage reference reaches 43.5dB.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present utility model, should to be understood that protection domain of the present utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these technology enlightenments of the utility model, and these distortion and combination are still in protection domain of the present utility model.

Claims (5)

1. a Bandgap Reference Without Resistors is characterized in that, comprises start-up circuit, self-bias current source circuit and the voltage follower that has the PTAT imbalance, wherein, start-up circuit is connected with the self-bias current source circuit, and the voltage follower that has the PTAT imbalance links to each other with the self-bias current source circuit.

2. Bandgap Reference Without Resistors according to claim 1, it is characterized in that, described self-bias current source circuit comprises PMOS pipe MP1, MP2, MP3, NMOS manages MN1, MN2, MN3, MN4, MN6, triode Q1, Q2, Q3, wherein, the source electrode of PMOS pipe and substrate all connect external power source, the equal ground connection of the substrate of NMOS pipe, the equal ground connection of the base stage of triode and collector, the grid leak short circuit of MP3, be connected with the grid of MP1 and MP2 simultaneously, MP1, MP2, the drain electrode of MP3 respectively with MN1, MN3, the drain electrode of MN4 connects, the drain electrode of MP3 is as the Vbias point of self-bias current source circuit, MN1 grid leak short circuit, and be connected with the grid of MN2 and MN3, the source electrode of MN1 is connected with the drain electrode of MN2, the source electrode of MN2 is connected with the emitter of Q1, the drain electrode of MN3 is connected with the grid of MN4, the grid that connects MN6 simultaneously, the source electrode of MN6 is connected with the emitter of Q2, connects the positive input of the voltage follower that has the PTAT imbalance simultaneously, the source electrode of MN4 is connected with the emitter of Q3, the source electrode of MN6 and grounded drain.

3. Bandgap Reference Without Resistors according to claim 2, it is characterized in that, the voltage follower of the described PTAT of having imbalance comprises NMOS pipe M1, M2, first current source, second current source, the 3rd current source and current mirror, wherein, the grid of NMOS pipe M1 and M2 is respectively as the forward and the negative input of voltage follower, drain electrode is connected with the second current source anode with first current source respectively, ground connection behind source series the 3rd current source, first current source, the negative terminal of second current source connects external power source respectively, anode is by power supply mirror ground connection, described first current source, the ratio of the size of current of second current source and the 3rd current source is A+1: B+1: A+B.

4. Bandgap Reference Without Resistors according to claim 2, it is characterized in that, the voltage follower of the described PTAT of having imbalance comprises 10 PMOS pipe MPA1-MPA10,12 NMOS pipe MNA1-MNA12, wherein, the equal ground connection of substrate of all NMOS pipes, the source electrode of MPA1-MPA6 and substrate all connect external power source, the grid of MPA1-MPA5 interconnects, and the Vbias point of connection self-bias current source circuit, the drain electrode of MPA1 is connected with the drain electrode of MNA1, the source electrode of MNA1 and substrate ground connection, its grid leak short circuit, and with MNA2, MNA4, MNA6, the grid of MNA8 connects, the grid leak short circuit of MPA6, and connect MPA7 and the grid of MPA8 and the drain electrode of MNA2, the source electrode of MNA2 is connected with the drain electrode of MNA3, the source ground of MNA3, its grid and MNA5, MNA7, the grid of MNA9 and the drain electrode of MNA6 connect, the drain electrode of MPA2 is connected with the grid of the source electrode of MPA9 and MNA10, the substrate of MPA9 is connected with the source, its grid is the positive input of voltage follower, drain electrode connects external power source, the drain electrode of MPA3 is connected with the grid of the source electrode of MPA10 and MNA11, the source electrode of MPA10 and substrate short circuit, its grid is the negative input of voltage follower, grounded drain, the source electrode of MNA10 and MNA11 interconnects, and connect the drain electrode of MNA4, the source electrode of MNA4 is connected with the drain electrode of MNA5, the source ground of MNA5, MNA10 and the drain electrode of MNA11 are connected the drain electrode of MPA4 and MPA5 respectively, the source electrode of MPA7 and MPA8 and substrate short circuit, and connect the drain electrode of MPA4 and MPA5 respectively, the drain electrode of MPA7 is connected with the drain electrode of MNA6, the source electrode of MNA6 is connected with the drain electrode of MNA7, the source ground of MNA7, the drain electrode of MPA8 is connected with the drain electrode of MNA8, the source electrode of MNA8 is connected with the drain electrode of MNA9 and as the output terminal of voltage follower, the source electrode of MNA9 connects external power source, and the grid that connects MNA12, the source electrode of MNA12 and the equal ground connection of drain electrode.

5. according to the described arbitrary Bandgap Reference Without Resistors of claim 2 to 4, it is characterized in that, described start-up circuit comprises PMOS pipe MPS1, NMOS manages MS, MSN1, wherein, the source electrode of MPS1 and substrate all meet external power source VDD, its grid is connected with the grid of MSN1, and be connected to the A point of self-bias current source, the drain electrode of MPS1 is connected with the drain electrode of MNS1, be connected to simultaneously on the grid of MS, the drain electrode of MS is connected to the Vbias point of self-bias current source circuit, the equal earthing potential of the source electrode of MS and MSN1 and substrate.

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