CN105468075B - Negative pressure charge pump feedback circuit - Google Patents
Negative pressure charge pump feedback circuit Download PDFInfo
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- CN105468075B CN105468075B CN201510977066.0A CN201510977066A CN105468075B CN 105468075 B CN105468075 B CN 105468075B CN 201510977066 A CN201510977066 A CN 201510977066A CN 105468075 B CN105468075 B CN 105468075B
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- Prior art keywords
- circuit
- reference voltage
- negative pressure
- input
- charge pump
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/562—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices with a threshold detection shunting the control path of the final control device
Abstract
The invention discloses a kind of negative pressure charge pump feedback circuit, including：Bleeder circuit, is connected by the extremely short MOS transistor connect of multiple drain-gates and is formed, and bleeder circuit is connected between the negative pressure of charge pump output and the first reference voltage and exports partial pressure as feedback voltage；Feedback voltage is connected to the first input end of the first operational amplifier, and the second input end grounding of the first operational amplifier, the amplified signal of the output of the first operational amplifier is used as clock control signal；Clock signal is input to the input of charge pump by clock control circuit, and clock control signal is input to clock control circuit so as to adjust clock signal input to the amplitude of charge pump, the size of negative pressure is adjusted by the regulation of the amplitude to clock signal.Energy reduction circuit area of the invention.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of negative pressure charge pump feedback circuit.
Background technology
As shown in figure 1, being the schematic diagram of existing negative pressure charge pump feedback circuit；Clock signal Clock is connected to and door 102
An input, the input of negative pressure charge pump 101, the output end of negative pressure charge pump 101 are connected to the output end of door 102
Negative pressure Vneg is exported, feedback circuit is connected to the output end of negative pressure charge pump 101 and between another input of door 102,
Feedback circuit includes comparator 103, resistor voltage divider circuit 104 and positive-negative voltage conversion circuit 105.Electric resistance partial pressure electricity in Fig. 1
Road 104 is formed by multiple resistant series, by data signal Dac the control of switch can be adjusted the annexation of resistance so as to
Control the dividing ratios of resistor voltage divider circuit 104.It is negative pressure Vneg partial pressure due to what resistor voltage divider circuit 104 was exported, therefore goes back
It is malleation by partial pressure switch to need by positive-negative voltage conversion circuit 105.The positive partial pressure value that positive-negative voltage conversion circuit 105 is exported
Output feedback voltage i.e. clock is compared with reference voltage V ref and enables signal Clock_en, and clock enables signal Clock_en
Whether control clock signal Clock is supplied to the circuit of charge pump 101, so as to adjust the output voltage Vneg of charge pump 101 in advance
Time value.
Find out as shown in Figure 1, the resistor voltage divider circuit 104 in existing feedback circuit by multiple resistant series, can take compared with
Big area.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of negative pressure charge pump feedback circuit, can reduction circuit area.
In order to solve the above technical problems, the negative pressure charge pump feedback circuit that the present invention is provided includes：
Bleeder circuit, is connected by multiple MOS transistors and is formed, and the drain and gate of each MOS transistor is connected to one
Rise, the bleeder circuit is connected between the negative pressure of charge pump output and the first reference voltage, the bleeder circuit output is described
Negative pressure and the partial pressure of first reference voltage are used as feedback voltage.
First operational amplifier, the feedback voltage is connected to the first input end of first operational amplifier, described
Second input end grounding of the first operational amplifier, the output end of first operational amplifier exports the feedback voltage and ground
The poor amplified signal of current potential is simultaneously used as clock control signal using the amplified signal.
Clock signal is input to the input of the charge pump, the clock control signal input by clock control circuit
To the clock control circuit, the clock control signal adjusts the clock signal input to the amplitude of the charge pump, led to
The regulation to the amplitude of the clock signal is crossed to adjust the size of the negative pressure.
Further improve is that the bleeder circuit is connected by multiple nmos pass transistors and formed.
Further improve is that the size of each NMOS tube of the bleeder circuit is identical.
Further improve is that the bleeder circuit is connected by multiple PMOS transistors and formed.
Further improve is that the size of each PMOS of the bleeder circuit is identical.
Further improve is that the bleeder circuit is connected and formed by multiple PMOS transistors and multiple nmos pass transistors.
Further improve is that first reference voltage adjusts circuit output by reference voltage, passes through benchmark electricity
Voltage regulator circuit adjusts the size of first reference voltage.
Further improve is that the reference voltage regulation circuit includes the second operational amplifier and resistance string；Described
The output end of two operational amplifiers adjusts the output end of circuit as the reference voltage and exports first reference voltage；Institute
Resistance string is stated to be connected between first reference voltage and ground；The resistance string by first resistor and adjustable resistance series connection and
Into；The first input end of second operational amplifier connects the second reference voltage, and the second of second operational amplifier is defeated
Enter the connecting node that end is connected to the first resistor and the adjustable resistance, by the big minor adjustment for adjusting the adjustable resistance
The size of first reference voltage.
Further improve is that the clock control circuit includes the first phase inverter, the second phase inverter and the 3rd phase inverter.
The input of first phase inverter connects the clock signal, and the output end of first phase inverter is connected to institute
Charge pump is stated, the control end of first phase inverter connects the clock control signal.
The input of second phase inverter connects the clock signal, and the output end connection of second phase inverter is described
The input of 3rd phase inverter, the output end of the 3rd phase inverter connects the charge pump, the control of the 3rd phase inverter
The end connection clock control signal.
Further improve is that the output end of first operational amplifier is connected to the grid of the first NMOS tube, described
The source ground of first NMOS tube, the drain electrode of first NMOS tube exports the clock control signal.
Further improve be, the first capacitance connection first operational amplifier output end and the negative pressure it
Between.
The present invention has following advantageous effects：
1st, bleeder circuit of the invention is in series by MOS transistor, relative to the bleeder circuit of resistant series formation
Structure, the present invention can reduce the area of bleeder circuit.
2nd, the ratio and the quantity of MOS transistor of the size by adjusting MOS transistor of bleeder circuit of the invention
With regard to required partial pressure can be obtained；In addition, the present invention and bleeder circuit need not be could be adjusted to realize to clock signal
Control, but the amplified signal exported by operational amplifier is realized to clock signal to the adjustment of the amplitude of clock signal
Control, and then realize and adjusted to the size of the negative pressure of output, so the present invention in existing feedback circuit relative to needing by right
The big minor adjustment of the resistance of bleeder circuit is controlled, and bleeder circuit of the invention can be always maintained at less electric current, so
The present invention can reduce the electric current of bleeder circuit, so as to reduce the current loading of charge pump, and then can reduce the area of charge pump.
3rd, the present invention adjusts circuit by reference voltage can adjust the size of the first reference voltage, and the negative pressure exported is true
Size with the first reference voltage is proportional, so the present invention can be adjusted by the adjustment of the size to the first reference voltage
The size of the negative pressure of output, so the present invention can realize that output is adjustable.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the schematic diagram of existing negative pressure charge pump feedback circuit；
Fig. 2 is the schematic diagram of negative pressure charge pump feedback circuit of the embodiment of the present invention.
Embodiment
As shown in Fig. 2 being the schematic diagram of the feedback circuit of negative pressure VNEG of embodiment of the present invention charge pumps 202, the present invention is implemented
The feedback circuit of example negative pressure VNEG charge pumps 202 includes：
Bleeder circuit 201, is connected by multiple MOS transistors and is formed, and the drain and gate of each MOS transistor is connected to
Together, the bleeder circuit 201 is connected between the negative pressure VNEG and the first reference voltage V refo of the output of charge pump 202, described
Bleeder circuit 201 exports the negative pressure VNEG and the first reference voltage V refo partial pressure as feedback voltage FDBK.
First operational amplifier 205, it is first defeated that the feedback voltage FDBK is connected to first operational amplifier 205
Enter end, the second input end grounding of first operational amplifier 205, the output end output of first operational amplifier 205
The poor amplified signal of the feedback voltage FDBK and ground potential is simultaneously used as clock control signal using the amplified signal.
Clock signal Clock is input to the input of the charge pump 202, the clock by clock control circuit 203
Control signal is input to the clock control circuit 203, and the clock control signal adjusts the clock signal Clock and is input to
The amplitude of the charge pump 202, the big of the negative pressure VNEG is adjusted by the regulation of the amplitude to the clock signal Clock
It is small.
In the embodiment of the present invention, the bleeder circuit 201 is connected by multiple nmos pass transistors to be formed, the bleeder circuit
The size of 201 each NMOS tube is identical.In other embodiments, also can be that the bleeder circuit 201 is brilliant by multiple NMOS
Body pipe is connected to be formed, and the size of each NMOS tube of the bleeder circuit 201 is differed；Or, the bleeder circuit 201 by
Multiple PMOS transistors connect to be formed, the size of each PMOS of the bleeder circuit 201 it is identical or；The bleeder circuit
201 are formed by multiple PMOS transistors and multiple nmos pass transistor combined serials.
In embodiments of the present invention, the first reference voltage V refo is exported by reference voltage regulation circuit 204, is passed through
The reference voltage regulation circuit 204 adjusts the size of the first reference voltage V refo.
The reference voltage regulation circuit 204 includes the second operational amplifier 206 and resistance string；Second operation amplifier
The output end of device 206 adjusts the output end of circuit 204 as the reference voltage and exports the first reference voltage V refo；
The resistance string is connected between the first reference voltage V refo and ground；The resistance string is by first resistor R1 and adjustable electric
Resistance Rd is in series, and adjustable resistance Rd can be controlled by control signal CTRL；The first of second operational amplifier 206
Input connects the second reference voltage V ref, and the second input of second operational amplifier 206 is connected to first electricity
R1 and adjustable resistance Rd connecting node is hindered, by adjusting the first benchmark electricity described in the big minor adjustment of the adjustable resistance Rd
Press Vrefo size.
In embodiments of the present invention, the clock control circuit 203 includes the first phase inverter 207a, the second phase inverter 207b
With the 3rd phase inverter 207c.
The input of the first phase inverter 207a connects the clock signal Clock, the first phase inverter 207a's
Output end is connected to the charge pump 202, and the control end of the first phase inverter 207a connects the clock control signal.
The input of the second phase inverter 207b connects the clock signal Clock, the second phase inverter 207b's
Output end connects the input of the 3rd phase inverter 207c, and the output end of the 3rd phase inverter 207c connects the charge pump
202, the 3rd phase inverter 207c control end connect the clock control signal.
In the embodiment of the present invention, the output end of first operational amplifier 205 is connected to the first NMOS tube MN1 grid
Pole, the source ground of the first NMOS tube MN1, the drain electrode of the first NMOS tube MN1 exports the clock control signal.
The first operational amplifier 205 does not export the clock control signal directly i.e. described in the embodiment of the present invention, but will be described
The output signal of first operational amplifier 205 is being used as the clock control signal after amplifying by the first NMOS tube MN1
Output.
First electric capacity C1 is connected between the output end of first operational amplifier 205 and the negative pressure VNEG.
The embodiment of the present invention is described further with reference to formula：
The formula that reference voltage regulation circuit 204 produces adjustable first reference voltage V refo is：
Vrefo=Vref × (Rd+R1)/R1；
Wherein, R1 represents the first resistor, and Rd represents the adjustable resistance, and Vrefo represents the first reference voltage, Vref
Represent the second reference voltage.When the location swap of first resistor R1 and the adjustable resistance Rd described in Fig. 2, can be also realized
One reference voltage V refo's is adjustable, and Rd and R1 value at this moment in formula are exchanged.
The formula that the bleeder circuit 201 forms the feedback voltage FDBK is：
FDBK=Vrefo*n/ (n+1)+VNEG*1/ (n+1)；
Wherein, FDBK represents feedback voltage, and VNEG represents negative pressure, and therein 1 represents in Fig. 2 in the first reference voltage
The number of nmos pass transistor between Vrefo and feedback voltage FDBK is that 1, n is represented in Fig. 2 in negative pressure VNEG and feedback voltage
The number of nmos pass transistor between FDBK is n, and the size of each nmos pass transistor is identical.When the size and class of MOS transistor
When type and number change, feedback voltage FDBK formula can do corresponding adjustment.From the foregoing, it will be observed that the present invention is implemented shown in Fig. 2
In example, feedback voltage FDBK is related only to the number of nmos pass transistor.
In the embodiment of the present invention, feedback voltage FDBK is by first operational amplifier 205 and clock control electricity
Road 203 is realized after the regulation to the charge pump 202, can make feedback voltage FDBK=0；And it is updated to above-mentioned feedback electricity by 0
The formula of pressure can be obtained：
VNEG=-Vrefo × n=-vref × n* (Rd+R1)/R1.
It follows that the negative pressure VNEG of the embodiment of the present invention only with the first reference voltage V refo and the bleeder circuit 201
MOS transistor number it is related, it is not necessary to using resistance string come partial pressure, relative to resistance string, in semiconductor integrated circuit system
Make in field, the size of MOS transistor is greatly reduced, so the embodiment of the present invention can reduce the area of bleeder circuit.
Meanwhile, the ratio and MOS of the size by adjusting MOS transistor of bleeder circuit of the embodiment of the present invention 201 are brilliant
The quantity of body pipe just can obtain required partial pressure, when the present invention and need not could be adjusted to bleeder circuit 201 is realized pair
Clock signal Clock control, but the amplified signal exported by operational amplifier 205 is to clock signal Clock amplitude
Adjust to realize the control to clock signal Clock, and then realize the size adjustment to the negative pressure VNEG of output, so of the invention
Embodiment is of the invention relative to needing the big minor adjustment by the resistance to bleeder circuit to be controlled in existing feedback circuit
The bleeder circuit 201 of embodiment can be always maintained at less electric current, so the embodiment of the present invention can reduce the electricity of bleeder circuit 201
Stream, so as to reduce the current loading of charge pump, and then can reduce the area of charge pump.
Understand, the embodiment of the present invention realizes the reduction of bleeder circuit 201 and the area of charge pump 202 simultaneously, whole electricity
Road surface product is reduced.
In addition, the embodiment of the present invention adjusts circuit 204 by reference voltage can adjust the big of the first reference voltage V refo
It is small, and the negative pressure VNEG and the first reference voltage V refo size that export are proportional, so the embodiment of the present invention can be by right
The adjustment of first reference voltage V refo size adjusts negative pressure VNEG size, so the present invention, which can be realized, exports adjustable.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of negative pressure charge pump feedback circuit, it is characterised in that including：
Bleeder circuit, is connected by multiple MOS transistors and is formed, and the drain and gate of each MOS transistor links together, institute
Bleeder circuit is stated to be connected between the negative pressure of charge pump output and the first reference voltage, the bleeder circuit export the negative pressure and
The partial pressure of first reference voltage is used as feedback voltage；
First operational amplifier, the feedback voltage is connected to the first input end of first operational amplifier, described first
Second input end grounding of operational amplifier, the output end of first operational amplifier exports the feedback voltage and ground potential
Poor amplified signal and clock control signal is used as using the amplified signal；
Clock signal is input to the input of the charge pump by clock control circuit, and the clock control signal is input to institute
Clock control circuit is stated, the clock control signal adjusts the clock signal input to the amplitude of the charge pump, by right
The regulation of the amplitude of the clock signal adjusts the size of the negative pressure；
First reference voltage adjusts circuit output by reference voltage, and adjusting circuit by the reference voltage adjusts described the
The size of one reference voltage；
The clock control circuit includes the first phase inverter, the second phase inverter and the 3rd phase inverter；
The input of first phase inverter connects the clock signal, and the output end of first phase inverter is connected to the electricity
Lotus pump, the control end of first phase inverter connects the clock control signal；
The input of second phase inverter connects the clock signal, the output end connection the described 3rd of second phase inverter
The input of phase inverter, the output end of the 3rd phase inverter connects the charge pump, and the control end of the 3rd phase inverter connects
Connect the clock control signal；
The output end of first operational amplifier is connected to the grid of the first NMOS tube, and the source electrode of first NMOS tube connects
Ground, the drain electrode of first NMOS tube exports the clock control signal；
The bleeder circuit is connected by multiple nmos pass transistors and formed, the size phase of each NMOS tube of the bleeder circuit
Together；Or, the bleeder circuit is connected by multiple PMOS transistors and formed, the size of each PMOS of the bleeder circuit
It is identical；
The number of MOS transistor between the negative pressure and the feedback voltage and the first reference voltage and the feedback electricity
The ratio of the number of MOS transistor between pressure is n, and the size of the negative pressure is adjusted by adjusting n.
2. negative pressure charge pump feedback circuit as claimed in claim 1, it is characterised in that：The reference voltage regulation circuit includes
Second operational amplifier and resistance string；
The output end of second operational amplifier adjusts the output end of circuit as the reference voltage and exports described first
Reference voltage；
The resistance string is connected between first reference voltage and ground；The resistance string is by first resistor and adjustable resistance string
Connection is formed；
The first input end of second operational amplifier connects the second reference voltage, and the second of second operational amplifier is defeated
Enter the connecting node that end is connected to the first resistor and the adjustable resistance, by the big minor adjustment for adjusting the adjustable resistance
The size of first reference voltage.
3. negative pressure charge pump feedback circuit as claimed in claim 1, it is characterised in that：First capacitance connection is in the described first fortune
Between the output end and the negative pressure of calculating amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510977066.0A CN105468075B (en) | 2015-12-22 | 2015-12-22 | Negative pressure charge pump feedback circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510977066.0A CN105468075B (en) | 2015-12-22 | 2015-12-22 | Negative pressure charge pump feedback circuit |
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| CN105468075A CN105468075A (en) | 2016-04-06 |
| CN105468075B true CN105468075B (en) | 2017-10-24 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105843316B (en) * | 2016-05-31 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | Charge pump reference voltage adjusts circuit |
| CN106774600A (en) * | 2016-12-23 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of low power consumption power supply circuit |
| CN107276396B (en) * | 2017-05-27 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN107453599B (en) * | 2017-07-17 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | Multi-voltage output positive-voltage charge pump |
| CN107493012B (en) * | 2017-07-17 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump |
| CN109327133A (en) * | 2017-08-01 | 2019-02-12 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit |
| CN109164863B (en) * | 2018-08-28 | 2020-06-09 | 上海华虹宏力半导体制造有限公司 | SONOS grid terminal control voltage generation circuit |
| CN109164866A (en) * | 2018-08-31 | 2019-01-08 | 南方科技大学 | Low pressure difference linear voltage regulator and power management chip based on negative charge pump enhancing |
| CN109274261A (en) * | 2018-11-30 | 2019-01-25 | 中国电子科技集团公司第四十三研究所 | A kind of non-isolated negative pressure output control circuit and control method |
| CN113394968B (en) | 2020-03-12 | 2023-09-22 | 长鑫存储技术有限公司 | Charge pump circuit |
| CN113315369A (en) * | 2021-07-09 | 2021-08-27 | 北京紫光青藤微系统有限公司 | Charge pump circuit |
| CN114362528A (en) * | 2021-12-31 | 2022-04-15 | 广州赛隆增材制造有限责任公司 | Suspension power supply |
| CN115425844B (en) * | 2022-11-02 | 2023-02-28 | 无锡中感微电子股份有限公司 | Charge pump capable of modulating output voltage and battery protection circuit adopting same |
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|---|---|
| CN105468075A (en) | 2016-04-06 |
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