CN104407662B - A kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated - Google Patents

Abstract

The present invention discloses the low pressure difference linear voltage regulator that a kind of underloading transient state strengthens circuit and this circuit integrated, comprises dynamic bias voltage and generates circuit, load current trip switch, electric capacity of voltage regulation, rushes down electric discharge road and output circuit; Underloading transient state strengthens circuit and does not consume any quiescent current when underloading, when low pressure difference linear voltage regulator is switched to underloading from heavy duty, underloading transient state strengthens circuit provides the load current successively decreased gradually, what significantly reduce low pressure difference linear voltage regulator sets up the time, thus overcomes the problem setting up overlong time when existing low pressure difference linear voltage regulator is switched to underloading from heavy duty; Secondly, the present invention does not need too much extra auxiliary circuit, and structure is simple, it is possible to strengthen the transient response performance of low pressure difference linear voltage regulator underloading, it is possible to be applicable to the application of super low-power consumption medical electronics.

Description

A kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated

Technical field

The invention belongs to technical field of power management, more specifically say, it relates to a kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated.

Background technology

Low pressure difference linear voltage regulator, as the important component part of power-supply management system, owing to peripheral components is few, export the advantages such as noise is low, mapping is good, plays key player in all kinds of medical treatment electronic equipment. At present, on sheet, integrated low-voltage difference linear constant voltage regulator output capacitance scope is only 0��100pF, it is possible to be completely integrated in internal system, eliminates the outer electric capacity of outside sheet, saves the area of PCB pin, accelerate manufacturing processed, reduce system cost, be therefore extensively employed.

But, in super low-power consumption medical treatment electronic equipment, in the potentiostat of such as energy collecting system and passive type RFID label tag, the energy is a kind of quite rare resource, and therefore on sheet, the quiescent current of integrated low-voltage difference linear constant voltage regulator and minimum load electric current all must be minimized. in order to ensure to stablize, on sheet, integrated low-voltage difference linear constant voltage regulator minimum load current is generally 50 �� A to 1mA, such as document " Anoutput-capacitorlesslow-dropoutregulatorwithdirectvolt age-spikedetection " (IEEEJ.Solid-StateCircuits, 2010, 45 (2): 458 466) and " A6-�� Wchip-area-efficientoutput-capacitorlessLDOin90-nmCMOSte chnology " (IEEEJ.Solid-StateCircuits, 2010, 45 (9): 755 759), and in super low-power consumption medical treatment electronic equipment, minimum load electric current must be less than 0.5 �� A.

At document " AHighSlew-RatePush-PullOutputAmplifierforLow-QuiescentCu rrentLow-DropoutRegulatorsWithTransient-ResponseImprovem ent " (IEEETrans.CircuitsSyst.II, Exp.Briefs, vol.54, no.9,755-759, Sep.2007), in, it is proposed that a kind of low pressure difference linear voltage regulator, by two difference, grid mutual conductance amplifier, electric current summation circuit and voltage buffer form this kind of potentiostat altogether. The transistor mated is formed an electric current mirror by one by two mutual conductance amplifier units, then connect into cross-couplings formula and form a push pull output stage, thus increase the injection electric current of power Correctional tube grid when transient state responds and extract electric current, maximum output current no longer has the restriction of amplifier by constant caudal current source of tail current source as tradition. Although this kind of potentiostat improves the limited problem of power Correctional tube voltage Slew Rate to a certain extent, but its mutual conductance and unity gain bandwidth cannot respond load transient switching fast under Low-bias Current.

Summary of the invention

It is an object of the invention to overcome the deficiencies in the prior art, a kind of underloading transient state is provided to strengthen the low pressure difference linear voltage regulator of circuit and this circuit integrated, when low pressure difference linear voltage regulator is when underload, underloading transient state strengthens circuit and does not consume quiescent current, when low pressure difference linear voltage regulator is switched to underloading from heavy duty, underloading transient state strengthens circuit provides the load current that successively decreases gradually to make output voltage quickly recover to standard value.

For achieving the above object, a kind of underloading transient state of the present invention strengthens circuit, it is characterised in that, comprising:

One dynamic bias voltage generates circuit, comprises PMOS MP1 and NMOS tube MN1; The grid voltage of PMOS MP1 is the grid voltage VGP of low pressure difference linear voltage regulator Correctional tube MP, source electrode is connected respectively to input power VDD, PMOS MP1 drain electrode is connected with drain electrode, the grid of NMOS tube MN1, the source electrode of NMOS tube MN1 is connected ground connection, dynamic bias voltage generates the adaptive-biased voltage VBNA of circuit evolving NMOS tube, i.e. the grid voltage of NMOS tube MN1;

One load current trip switch, comprises PMOS MP2, PMOS MP3 and NMOS tube MN2; The source electrode of PMOS MP2 is connected and is linked into input power VDD, and the drain electrode that the grid of PMOS MP2 connects PMOS constant bias voltage VBP, PMOS MP2 is connected with the drain electrode of NMOS tube MN2 with the grid of PMOS MP3; The source electrode of PMOS MP3 is linked into adaptive-biased voltage VBNA, and drain electrode connects one end of electric capacity of voltage regulation C1; The grid of NMOS tube MN2 connects adaptive-biased voltage VBNA, source ground, and during underloading, VC voltage is voltage of supply, and PMOS MP3 turns off; During heavy duty, VC voltage is ground voltage, and PMOS MP3 opens;

One electric capacity of voltage regulation C1, electric capacity of voltage regulation C1 one end connects the drain electrode of PMOS MP3, and one end ground connection in addition, for setting the electric current lowering speed of output circuit;

One rushes down electric discharge road, comprises NMOS tube MN3; The source ground of NMOS tube MN3, grid connects the first constant bias voltage VBN1 of NMOS tube, and drain electrode connects the drain electrode of PMOS MP3; Rushing down electric discharge road, to ensure that underloading transient state strengthens the outward current of circuit when underloading works be 0, and coordinates electric capacity of voltage regulation C1 to arrange the electric current lowering speed of output circuit;

One output circuit, comprises NMOS tube MN4; The source ground of NMOS tube MN4, grid connects the drain electrode of PMOS MP3, and drain electrode connects the output voltage VO UT of low pressure difference linear voltage regulator; Output circuit provides the load current successively decreased gradually when low pressure difference linear voltage regulator is switched to underloading from heavy duty.

Further, integrated above-mentioned underloading transient state strengthens the low pressure difference linear voltage regulator of circuit, comprising: operational amplifier, Correctional tube, compensation electric capacity CC, constant bias voltage generate circuit, resistor voltage divider network, pull-up resistor R_LWith load electric capacity C_L;

Constant bias voltage generates constant bias voltage VBP, the first constant bias voltage VBN1 of NMOS tube and the 2nd constant bias voltage VBN2 of NMOS tube of circuit evolving PMOS; The reverse input terminus of operational amplifier connects external reference voltages VREF, and in-phase input end connects the feedback voltage V FB of low pressure difference linear voltage regulator, and output terminal connects the grid of Correctional tube MP; Resistor voltage divider network input terminus connects the output VOUT of low pressure difference linear voltage regulator, and output terminal connects low pressure difference linear voltage regulator feedback voltage V FB; The source electrode of Correctional tube MP meets input power VDD, and the drain electrode of Correctional tube MP connects the output VOUT of low pressure difference linear voltage regulator; Compensating the output VOUT that electric capacity CC one end connects low pressure difference linear voltage regulator, the other end is connected to the source electrode of the NMOS tube MN13 of operational amplifier; Pull-up resistor R_LWith load electric capacity C_LOne end connect the output VOUT of low pressure difference linear voltage regulator, the other end connects ground, and the output terminal that underloading transient state finally strengthens circuit again is connected to the output VOUT of low pressure difference linear voltage regulator.

Wherein, described operational amplifier is a single stage operational amplifier, comprising: PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source ground of NMOS tube MN5, grid connects the first constant bias voltage VBN1 of NMOS tube, for operational amplifier provides bias current; The grid of NMOS tube MN6 connects external reference voltages VREF, the grid of NMOS tube MN7 connects the feedback voltage V FB of low pressure difference linear voltage regulator, the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN7 are connected with the drain electrode of NMOS tube MN5, NMOS tube MN6 and NMOS tube MN7 jointly as the difference of operational amplifier to pipe;

PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13 form folded common source and common grid level, wherein, the source electrode NMOS tube MN10 of NMOS tube MN8, NMOS tube MN9, the source electrode of NMOS tube MN11 ground connection respectively, the source electrode of PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 receives voltage of supply VDD; Grid, the drain electrode of the drain electrode of NMOS tube MN6, the grid of PMOS MP4, PMOS MP6 are all connected; Grid, the drain electrode of the drain electrode of NMOS tube MN7, the grid of PMOS MP5, PMOS MP7 are all connected; The drain electrode of the drain electrode of NMOS tube MN8, the source electrode of NMOS tube MN12, PMOS MP4 is all connected; The drain electrode of the drain electrode of NMOS tube MN9, the source electrode of NMOS tube MN13, PMOS MP5, one end of compensation electric capacity CC are all connected; The grid of NMOS tube MN8, NMOS tube MN9 is all connected to the first constant bias voltage VBN1 of NMOS tube, and the other one end compensating electric capacity CC connects the output voltage VO UT of low pressure difference linear voltage regulator; The grid of NMOS tube MN12 and NMOS tube MN13 all connects the 2nd constant bias voltage VBN2 of NMOS tube; The drain electrode of NMOS tube MN12, the drain electrode of PMOS MP8, grid are all connected with the grid of PMOS MP9; Drain electrode, the grid of Correctional tube MP of PMOS MP9 are all connected with the drain electrode of NMOS tube MN13, and the grid of NMOS tube MN10 and MN11 is all connected to the adaptive-biased voltage VBNA of NMOS tube; The drain electrode of NMOS tube MN10 connects the drain electrode of NMOS tube MN8, and the drain electrode of NMOS tube MN11 connects the drain electrode of NMOS tube MN9.

Described resistor voltage divider network comprises: first point of compressive resistance RFB1 and the 2nd point of compressive resistance RFB2; One end of first point of compressive resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of 2nd point of compressive resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.

Described constant bias voltage generates circuit and comprises: PMOS MP10, PMOS MP11 and NMOS tube MN14, NMOS tube MN15;

The source electrode of PMOS MP10, PMOS MP11 receives voltage of supply VDD, the grid of PMOS MP10 is connected to outside constant-current bias source IB, the grid that outside constant-current bias source IB is PMOS MP10 provides the grid of constant bias voltage VBP, PMOS MP10, the drain electrode of PMOS MP10 to be all connected with the grid of PMOS MP11; The drain electrode of PMOS MP11 is connected to the drain and gate of NMOS tube MN14, and the grid voltage of MN14 is the 2nd constant bias voltage VBN2 of NMOS tube; The source electrode of NMOS tube MN14 is connected to the drain and gate of NMOS tube MN15, and the grid voltage of MN15 is the first constant bias voltage VBN1 of NMOS tube, the source ground of NMOS tube MN15.

The goal of the invention of the present invention is achieved in that

The present invention's a kind of underloading transient state strengthens the low pressure difference linear voltage regulator of circuit and this circuit integrated, comprises dynamic bias voltage and generates circuit, load current trip switch, electric capacity of voltage regulation, rushes down electric discharge road and output circuit; Underloading transient state strengthens circuit and does not consume any quiescent current when underloading, when low pressure difference linear voltage regulator is switched to underloading from heavy duty, underloading transient state strengthens circuit provides the load current successively decreased gradually, what significantly reduce low pressure difference linear voltage regulator sets up the time, thus overcomes the problem setting up overlong time when existing low pressure difference linear voltage regulator is switched to underloading from heavy duty; Secondly, the present invention does not need too much extra auxiliary circuit, and structure is simple, it is possible to strengthen the transient response performance of low pressure difference linear voltage regulator underloading, it is possible to be applicable to the application of super low-power consumption medical electronics.

Meanwhile, the low pressure difference linear voltage regulator of a kind of underloading of the present invention transient state enhancing circuit and this circuit integrated also has following useful effect:

(1), the underloading transient state of the present invention strengthens circuit and does not consume any quiescent current when underloading, it is not necessary to too much extra auxiliary circuit, has that structure is simple, the feature of good stability;

(2), low pressure difference linear voltage regulator is when being switched to underloading from heavy duty, and it is short that the low pressure difference linear voltage regulator of this circuit integrated sets up the time, and minimum load electric current is low, and quiescent current is low, is suitable for the application of super low-power consumption medical electronics.

Accompanying drawing explanation

Fig. 1 is a kind of implementing circuit figure that the present invention's a kind of underloading transient state strengthens circuit;

Fig. 2 is a kind of implementing circuit figure that integrated underloading transient state strengthens the low pressure difference linear voltage regulator of circuit;

Fig. 3 is a kind of structure iron that integrated underloading transient state strengthens the low pressure difference linear voltage regulator of circuit;

Fig. 4 is the checking result figure of low pressure difference linear voltage regulator under different frequency response that underloading transient state strengthens circuit and this circuit integrated;

Fig. 5 is underloading transient state when strengthening the low pressure difference linear voltage regulator of circuit and this circuit integrated electric capacity is 100pF outside, load transient response checking result figure;

Fig. 6 is integrated or the load transient response results contrast figure of the low pressure difference linear voltage regulator of this underloading transient state not integrated enhancing circuit.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that the technician of this area understands the present invention better. Requiring particular attention is that, in the following description, when perhaps the detailed description of known function and design can desalinate the main contents of the present invention, these descriptions will be ignored here.

Embodiment

In the present embodiment, as shown in Figure 1, a kind of underloading transient state of the present invention strengthens circuit, comprising: a dynamic bias voltage generates circuit 1, load current trip switch 2, electric capacity of voltage regulation 3, and rushes down electric discharge road 4 and an output circuit 5;

Dynamic bias voltage generates circuit 1, comprises PMOS MP1 and NMOS tube MN1; The grid voltage of PMOS MP1 is the grid voltage VGP of low pressure difference linear voltage regulator Correctional tube MP, source electrode is connected respectively to input power VDD, PMOS MP1 drain electrode is connected with drain electrode, the grid of NMOS tube MN1, the source electrode of NMOS tube MN1 is connected ground connection, dynamic bias voltage generates circuit 1 and generates the adaptive-biased voltage VBNA of NMOS tube, i.e. the grid voltage of NMOS tube MN1;

Load current trip switch 2, comprises PMOS MP2, PMOS MP3 and NMOS tube MN2; The source electrode of PMOS MP2 is connected and is linked into input power VDD, and the drain electrode that the grid of PMOS MP2 connects PMOS constant bias voltage VBP, PMOS MP2 is connected with the drain electrode of NMOS tube MN2 with the grid of PMOS MP3; The source electrode of PMOS MP3 is linked into adaptive-biased voltage VBNA, and drain electrode connects one end of electric capacity of voltage regulation C1; The grid of NMOS tube MN2 connects the source ground of adaptive-biased voltage VBNA, NMOS tube MN2; One end of electric capacity of voltage regulation 3C1 connects the drain electrode of PMOS MP3, and one end ground connection in addition, for setting the electric current lowering speed of output circuit;

PMOS MP2 can be equivalent to a constant current source, PMOS MP2 and NMOS tube MN2 forms an electric current comparer, and very low by the electric current of NMOS tube MN2 during underloading, PMOS is forced into dark linear section to maintain current balance type, VC voltage is that voltage of supply VDD, PMOS MP3 turn off; VC voltage is ground voltage, and PMOS MP3 opens, and enters dark linear section, and electric capacity of voltage regulation 3C1 is charged, and on electric capacity of voltage regulation 3C1, the grid voltage of terminal voltage and NMOS tube MN4 equals the grid voltage of NMOS tube MN1;

Rush down electric discharge road 4, comprise NMOS tube MN3; The source ground of NMOS tube MN3, grid connects the first constant bias voltage VBN1 of NMOS tube, and drain electrode connects the drain electrode of PMOS MP3; Output circuit 5, comprises NMOS tube MN4; The source ground of NMOS tube MN4, grid connects the drain electrode of PMOS MP3, and drain electrode connects the output voltage VO UT of low pressure difference linear voltage regulator;

During underloading, VC voltage is voltage of supply VDD, PMOS MP3 turns off, NMOS tube MN3 puts the electricity of electric capacity of voltage regulation 3C1 by thoroughly rushing down, the grid voltage of NMOS tube MN4 is ground voltage, therefore, rushing down electric discharge road 4, to ensure that underloading transient state strengthens the outward current of circuit when underloading works be 0, and coordinates electric capacity of voltage regulation 3C1 to arrange the electric current lowering speed of output circuit; During heavy duty, being increased by NMOS tube MN1 electric current, PMOS MP3 is completely open-minded simultaneously, and electric capacity of voltage regulation 3C1 is charged to VBNA, and output circuit 5 i.e. NMOS tube MN4 exports a certain amount of load current. When potentiostat is switched to underloading from heavy duty, VC is from ground voltage switching during heavy duty to voltage of supply, PMOS MP3 turns off, the electric current of electric capacity of voltage regulation 3C1 only can be rushed down electric discharge road 4 i.e. NMOS tube MN3 slow releasing, therefore NMOS tube MN4 exports a load current successively decreased gradually, makes potentiostat quickly recover to stationary value.

A kind of implementation of the low pressure difference linear voltage regulator that Fig. 2 the present invention proposes

As shown in Figure 2, in the present embodiment, low pressure difference linear voltage regulator, comprising: operational amplifier 1, Correctional tube 2, compensation electric capacity CC3, constant bias voltage generate circuit 4, resistor voltage divider network 5, pull-up resistor R_L6 and load electric capacity C_L7;

Operational amplifier 1 is a single stage operational amplifier, comprising: PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source ground of NMOS tube MN5, grid connects the first constant bias voltage VBN1 of NMOS tube, for operational amplifier provides bias current; The grid of NMOS tube MN6 connects external reference voltages VREF, the grid of NMOS tube MN7 connects the feedback voltage V FB of low pressure difference linear voltage regulator, the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN7 are connected with the drain electrode of NMOS tube MN5, NMOS tube MN6 and NMOS tube MN7 jointly as the difference of operational amplifier 1 to pipe;

PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13 form folded common source and common grid level;

Wherein, the source electrode NMOS tube MN10 of NMOS tube MN8, NMOS tube MN9, the source electrode of NMOS tube MN11 ground connection respectively, the source electrode of PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 receives voltage of supply VDD; Grid, the drain electrode of the drain electrode of NMOS tube MN6, the grid of PMOS MP4, PMOS MP6 are all connected; Grid, the drain electrode of the drain electrode of NMOS tube MN7, the grid of PMOS MP5, PMOS MP7 are all connected; The drain electrode of the drain electrode of NMOS tube MN8, the source electrode of NMOS tube MN12, PMOS MP4 is all connected; The drain electrode of the drain electrode of NMOS tube MN9, the source electrode of NMOS tube MN13, PMOS MP5, one end of compensation electric capacity CC3 are all connected; The grid of NMOS tube MN8, NMOS tube MN9 is all connected to the first constant bias voltage VBN1 of NMOS tube, and the other one end compensating electric capacity CC3 connects the output voltage VO UT of low pressure difference linear voltage regulator; The grid of NMOS tube MN12 and NMOS tube MN13 all connects the 2nd constant bias voltage VBN2 of NMOS tube; The drain electrode of NMOS tube MN12, the drain electrode of PMOS MP8, grid are all connected with the grid of PMOS MP9; Drain electrode, the grid of Correctional tube 2MP of PMOS MP9 are all connected with the drain electrode of NMOS tube MN13, and the grid of NMOS tube MN10 and MN11 is all connected to the adaptive-biased voltage VBNA of NMOS tube; The drain electrode of NMOS tube MN10 connects the drain electrode of NMOS tube MN8, and the drain electrode of NMOS tube MN11 connects the drain electrode of NMOS tube MN9;

Constant bias voltage generates circuit 4 and comprises PMOS MP10, PMOS MP11 and NMOS tube MN14, NMOS tube MN15;

The source electrode of PMOS MP10, PMOS MP11 receives voltage of supply VDD, the grid of PMOS MP10 is connected to outside constant-current bias source IB, the grid that outside constant-current bias source IB is PMOS MP10 provides the grid of constant bias voltage VBP, PMOS MP10, the drain electrode of PMOS MP10 to be all connected with the grid of PMOS MP11; The drain electrode of PMOS MP11 is connected to the drain and gate of NMOS tube MN14, and the grid voltage of MN14 is the 2nd constant bias voltage VBN2 of NMOS tube; The source electrode of NMOS tube MN14 is connected to the drain and gate of NMOS tube MN15, and the grid voltage of MN15 is the first constant bias voltage VBN1 of NMOS tube, the source ground of NMOS tube MN15;

Resistor voltage divider network 5 comprises: first point of compressive resistance RFB1 and the 2nd point of compressive resistance RFB2; One end of first point of compressive resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of 2nd point of compressive resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.

The reverse input terminus of operational amplifier 1 connects external reference voltages VREF, and in-phase input end connects the feedback voltage V FB of low pressure difference linear voltage regulator, and output terminal connects the grid of Correctional tube 2; The input terminus of resistor voltage divider network 5 connects the output VOUT of low pressure difference linear voltage regulator, and output terminal connects low pressure difference linear voltage regulator feedback voltage V FB; The source electrode of Correctional tube 2 connects outer power voltage VDD, and the drain electrode of Correctional tube 2 connects the output VOUT of low pressure difference linear voltage regulator; Compensating the output VOUT that electric capacity CC3 one end connects low pressure difference linear voltage regulator, the other end is connected to the source electrode of the NMOS tube MN13 of operational amplifier 1, forms active electric current rice like this and strangles feedback; Pull-up resistor R_L6 and load electric capacity C_LOne end of 7 connects the output VOUT of low pressure difference linear voltage regulator, and the other end connects the output VOUT that the last output terminal that underloading transient state strengthens circuit again in ground is connected to low pressure difference linear voltage regulator.

Fig. 3 is the low pressure difference linear voltage regulator structure iron that integrated underloading transient state strengthens circuit, wherein, and g_m1It is the mutual conductance of operational amplifier, R₁It is the output resistance of operational amplifier, C₁It is the stray capacitance that Correctional tube MP grid and operational amplifier export node, g_mpIt is the mutual conductance of Correctional tube MP, C_CIt is compensate electric capacity, g_mcIt is the mutual conductance of NMOS tube MN13, C_LBeing the output capacitance of a 100pF, it is used for simulating the maximum output capacitance of power division on sheet and the stray capacitance on some metal wires, R_LIt it is the overall output resistance of low pressure difference linear voltage regulator. Low pressure difference linear voltage regulator forms active electric current rice strangle feedback by compensating electric capacity CC, it is achieved that limit is separated, and its transport function can be drawn by the structure iron shown in Fig. 3, it is possible to represents and is:

$A_{v\left(s\right)}=\frac{g_{m1}{R}_1{g}_{mp}{R}_L(1+s\frac{C_C}{2g_{mc}})}{(1+{\mathrm{sg}}_{mp}{R}_L{R}_1{C}_C)(1+s\frac{C_L}{g_{mp}}\frac{C_1}{C_C}+s^2\frac{C_L}{g_{mp}}\frac{C_1}{g_{mc}})}---\left(1\right)$

The long-pending GBW of the gain bandwidth of low pressure difference linear voltage regulator can represent:

$GBW=\frac{g_{m1}}{C_C}---\left(2\right)$

The zero point Z of the right half-plane of low pressure difference linear voltage regulator₁Can represent and be:

$Z_1=\frac{2g_{mc}}{C_C}---\left(3\right)$

Due to Z₁Being amass beyond gain bandwidth far away, can't affect stable, in order to simple analysis, its effect is ignored.

The secondary limit P of the right half-plane of low pressure difference linear voltage regulator₂And P₃It is expressed as:

$p_2=\frac{g_{mp}}{C_L}\frac{C_C}{C_1}---\left(4\right)$

$p_3=\frac{g_{mc}}{C_C}---\left(5\right)$

When potentiostat is in underloading state, secondary limit P₂And P₃It is separation limit, and secondary limit P₃Frequency is much larger than secondary limit P₂Frequency, because of this limit P₃Analysis is not considered. In order to ensure that phase place nargin is greater than 60 ��, secondary limit P₂The twice that regulator gain bandwidth is long-pending should be greater than, present invention employs active electric current rice and strangle Feedback Design, secondary limit frequency is increased C_C/C₁Doubly, therefore Correctional tube MP mutual conductance g_mpValue can reduce greatly, and minimum load current value can also be reduced to 0.5 below �� A.

Secondary limit P₂Frequency increases with load current and increases, secondary limit P₂And P₃Forming conjugate pole pair gradually, frequency and the quality factor Q value of conjugate pole pair are expressed as:

$\left|p_{2,3}\right|=\sqrt{\frac{g_{mp}{g}_{mc}}{C_1{C}_L}}---\left(6\right)$

$Q=\sqrt{\frac{{C_C}^2{g}_{mp}}{C_1{C}_L{g}_{mc}}}---\left(7\right)$

Secondary limit P₂And P₃The conjugate pole formed is very high to frequency, but along with Correctional tube MP mutual conductance g_mpIncrease, it is possible to formation affects potentiostat and stablizes owing to Q value is excessive. Therefore the present invention introduces adaptive-biased, when heavy duty, is increased by the electric current of NMOS tube MN10, MN11, and NMOS tube MN13 also increases thereupon, g_mcAlso synchronously rise, according to formula (7), P₂And P₃Q value is also declined by the conjugate pole formed thereupon.

The present invention's a kind of underloading transient state strengthens low pressure difference linear voltage regulator checking under a kind of mixed signal 0.13 ��m of CMOS technology of circuit and this circuit integrated, and the threshold voltage of NMOS tube and PMOS is 0.3V.

The low pressure difference linear voltage regulator that a kind of underloading transient state strengthens circuit and this circuit integrated under different load conditions frequency response checking result as shown in Figure 4. Wherein RFB1 is that 0, RFB2 removes, and external reference voltages is 0.8V, and voltage of supply VDD is 1V. When load current IL is 0.5 �� A, potentiostat direct current gain is 52dB, and gain bandwidth is long-pending is 190kHz, and phase place nargin is 70 ��. When load current IL is 1mA, direct current gain is 34dB, and gain bandwidth is amassed as 250kHz, and phase place nargin is 90 ��.

It is load transient response during 100pF at load electric capacity CL that Fig. 5 shows the low pressure difference linear voltage regulator of a kind of underloading transient state enhancing circuit and this circuit integrated, and wherein RFB1 is that 0, RFB2 removes. Voltage of supply VDD is 1V, output voltage VO UT is 0.8V, and load current IL scope is 0.5 �� A to 1mA. Under underloading, the quiescent current of low pressure difference linear voltage regulator is only 2.2 �� A, and owing to introducing adaptive-biased voltage circuit, time fully loaded, low pressure difference linear voltage regulator quiescent current is increased to 49 �� A. When load current is switched to 1mA from 0.5 �� A, output voltage undershoot is 70mV, and the time of foundation is 2.2 �� s; When load current is switched to 0.5 �� A from 1mA, output voltage overshoot is 65mV, and the time of foundation is 1.8 �� s.

Fig. 6 shows a kind of underloading transient state and strengthens circuit and the low pressure difference linear voltage regulator of this circuit integrated and the low pressure difference linear voltage regulator load transient response results contrast figure of this circuit not integrated, and wherein, CL is 100pF, RFB1 is 0, RFB2, voltage of supply VDD are 1V, output voltage VO UT is 0.8V. Underloading transient state strengthens circuit when load current is 1mA as can be seen from Figure 5, export the load current of 22 �� A, when load current is switched to 0.5 �� A from 1mA, underloading transient state strengthens circuit and provides a load current IL successively decreased gradually, makes output voltage VO UT return to stationary value in 1.8 �� s. If not having underloading transient state to strengthen circuit, the time of foundation is about 12.5 �� s, and therefore, the underloading transient state adopting the present invention to propose strengthens circuit, and the time of setting up of potentiostat shortens to original 1/7.

Although above the embodiment of the present invention's explanation property being described; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various change is in appended scope and the spirit and scope of the present invention determined, these changes are apparent, and all utilize the innovation and creation of present inventive concept all at the row of protection.

Claims (5)

1. a underloading transient state strengthens circuit, it is characterised in that, comprising:

One dynamic bias voltage generates circuit, comprises PMOS MP1 and NMOS tube MN1; The grid voltage of PMOS MP1 is the grid voltage VGP of low pressure difference linear voltage regulator Correctional tube MP, source electrode is connected respectively to input power VDD, PMOS MP1 drain electrode is connected with drain electrode, the grid of NMOS tube MN1, the source electrode of NMOS tube MN1 is connected ground connection, dynamic bias voltage generates the adaptive-biased voltage VBNA of circuit evolving NMOS tube, i.e. the grid voltage of NMOS tube MN1;

One load current trip switch, comprises PMOS MP2, PMOS MP3 and NMOS tube MN2; The source electrode of PMOS MP2 is connected and is linked into input power VDD, and the drain electrode that the grid of PMOS MP2 connects PMOS constant bias voltage VBP, PMOS MP2 is connected with the drain electrode of NMOS tube MN2 with the grid of PMOS MP3; The source electrode of PMOS MP3 is linked into adaptive-biased voltage VBNA, and drain electrode connects one end of electric capacity of voltage regulation C1; The grid of NMOS tube MN2 connects adaptive-biased voltage VBNA, source ground, and during underloading, VC voltage is voltage of supply, and PMOS MP3 turns off; During heavy duty, VC voltage is ground voltage, and PMOS MP3 opens;

One electric capacity of voltage regulation C1, electric capacity of voltage regulation C1 one end connects the drain electrode of PMOS MP3, and one end ground connection in addition, for setting the electric current lowering speed of output circuit;

One rushes down electric discharge road, comprises NMOS tube MN3; The source ground of NMOS tube MN3, grid connects the first constant bias voltage VBN1 of NMOS tube, and drain electrode connects the drain electrode of PMOS MP3; Rushing down electric discharge road, to ensure that underloading transient state strengthens the outward current of circuit when underloading works be 0, and coordinates electric capacity of voltage regulation C1 to arrange the electric current lowering speed of output circuit;

One output circuit, comprises NMOS tube MN4; The source ground of NMOS tube MN4, grid connects the drain electrode of PMOS MP3, and drain electrode connects the output voltage VO UT of low pressure difference linear voltage regulator; Output circuit provides the load current successively decreased gradually when low pressure difference linear voltage regulator is switched to underloading from heavy duty.

2. the low pressure difference linear voltage regulator of an integrated underloading transient state according to claim 1 enhancing circuit, it is characterised in that, comprising: operational amplifier, Correctional tube, compensation electric capacity CC, constant bias voltage generate circuit, resistor voltage divider network, pull-up resistor R_LWith load electric capacity C_L;

Constant bias voltage generates constant bias voltage VBP, the first constant bias voltage VBN1 of NMOS tube and the 2nd constant bias voltage VBN2 of NMOS tube of circuit evolving PMOS; The reverse input terminus of operational amplifier connects external reference voltages VREF, and in-phase input end connects the feedback voltage V FB of low pressure difference linear voltage regulator, and output terminal connects the grid of Correctional tube MP; Resistor voltage divider network input terminus connects the output VOUT of low pressure difference linear voltage regulator, and output terminal connects low pressure difference linear voltage regulator feedback voltage V FB; The source electrode of Correctional tube MP meets input power VDD, and the drain electrode of Correctional tube MP connects the output VOUT of low pressure difference linear voltage regulator; Compensating the output VOUT that electric capacity CC one end connects low pressure difference linear voltage regulator, the other end is connected to the source electrode of the NMOS tube MN13 of operational amplifier; Pull-up resistor R_LWith load electric capacity C_LOne end connect the output VOUT of low pressure difference linear voltage regulator, the other end connects ground, and the output terminal that underloading transient state finally strengthens circuit again is connected to the output VOUT of low pressure difference linear voltage regulator.

3. low pressure difference linear voltage regulator according to claim 2, it is characterized in that, described operational amplifier is a single stage operational amplifier, comprises PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13;

The source ground of NMOS tube MN5, grid connects the first constant bias voltage VBN1 of NMOS tube, for operational amplifier provides bias current; The grid of NMOS tube MN6 connects external reference voltages VREF, the grid of NMOS tube MN7 connects the feedback voltage V FB of low pressure difference linear voltage regulator, the source electrode of NMOS tube MN6, the source electrode of NMOS tube MN7 are connected with the drain electrode of NMOS tube MN5, NMOS tube MN6 and NMOS tube MN7 jointly as the difference of operational amplifier to pipe;

PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 and NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13 form folded common source and common grid level, wherein, the source electrode of the source electrode of NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11 is ground connection respectively, and the source electrode of PMOS MP4, PMOS MP5, PMOS MP6, PMOS MP7, PMOS MP8, PMOS MP9 receives voltage of supply VDD; Grid, the drain electrode of the drain electrode of NMOS tube MN6, the grid of PMOS MP4, PMOS MP6 are all connected; Grid, the drain electrode of the drain electrode of NMOS tube MN7, the grid of PMOS MP5, PMOS MP7 are all connected; The drain electrode of the drain electrode of NMOS tube MN8, the source electrode of NMOS tube MN12, PMOS MP4 is all connected; The drain electrode of the drain electrode of NMOS tube MN9, the source electrode of NMOS tube MN13, PMOS MP5, one end of compensation electric capacity CC are all connected; The grid of NMOS tube MN8, NMOS tube MN9 is all connected to the first constant bias voltage VBN1 of NMOS tube, and the other one end compensating electric capacity CC connects the output voltage VO UT of low pressure difference linear voltage regulator; The grid of NMOS tube MN12 and NMOS tube MN13 all connects the 2nd constant bias voltage VBN2 of NMOS tube; The drain electrode of NMOS tube MN12, the drain electrode of PMOS MP8, grid are all connected with the grid of PMOS MP9; Drain electrode, the grid of Correctional tube MP of PMOS MP9 are all connected with the drain electrode of NMOS tube MN13, and the grid of NMOS tube MN10 and MN11 is all connected to the adaptive-biased voltage VBNA of NMOS tube; The drain electrode of NMOS tube MN10 connects the drain electrode of NMOS tube MN8, and the drain electrode of NMOS tube MN11 connects the drain electrode of NMOS tube MN9.

4. low pressure difference linear voltage regulator according to claim 2, it is characterised in that, described resistor voltage divider network comprises: first point of compressive resistance RFB1 and the 2nd point of compressive resistance RFB2; One end of first point of compressive resistance RFB1 is connected to low pressure difference linear voltage regulator and exports VOUT, and one end is connected to low pressure difference linear voltage regulator feedback voltage V FB in addition; One end of 2nd point of compressive resistance RFB2 is connected to low pressure difference linear voltage regulator feedback voltage V FB, and the other end is connected to ground.

5. low pressure difference linear voltage regulator according to claim 2, it is characterised in that, described constant bias voltage generates circuit and comprises PMOS MP10, PMOS MP11 and NMOS tube MN14, NMOS tube MN15;

The source electrode of PMOS MP10, PMOS MP11 receives voltage of supply VDD, the grid of PMOS MP10 is connected to outside constant-current bias source IB, the grid that outside constant-current bias source IB is PMOS MP10 provides the grid of constant bias voltage VBP, PMOS MP10, the drain electrode of PMOS MP10 to be all connected with the grid of PMOS MP11; The drain electrode of PMOS MP11 is connected to the drain and gate of NMOS tube MN14, and the grid voltage of MN14 is the 2nd constant bias voltage VBN2 of NMOS tube; The source electrode of NMOS tube MN14 is connected to the drain and gate of NMOS tube MN15, and the grid voltage of MN15 is the first constant bias voltage VBN1 of NMOS tube, the source ground of NMOS tube MN15.