CN115268554A - Low dropout regulator - Google Patents
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- CN115268554A CN115268554A CN202210689518.5A CN202210689518A CN115268554A CN 115268554 A CN115268554 A CN 115268554A CN 202210689518 A CN202210689518 A CN 202210689518A CN 115268554 A CN115268554 A CN 115268554A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention discloses a low dropout linear regulator, which comprises a band gap reference circuit, a regulator circuit and a transient enhancement circuit; the band-gap reference circuit is used for providing a reference voltage for the regulator circuit; the regulator circuit is used for converting the reference voltage into a stable voltage for output, and the transient enhancement circuit is used for providing a charging path or a discharging path when the voltage value output by the load output end of the regulator circuit changes, so that the voltage of the load output end is stable, and the transient response of the output end is stabilized. The linear voltage regulator provided by the invention has the advantages of quick transient response, low load regulation rate, low temperature coefficient, low power consumption and high stability.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a low dropout regulator.
Background
With the coming of the internet of things era, consumer electronics products such as intelligent trips, smart phones and intelligent wearable products are rapidly developed and permeate into the aspects of life of people. The intelligent power integrated circuit is the hardware core part of the novel electronic products, and the power supply part is a power management chip. In order to meet the requirements of different modules on power supply voltage, power supply management chips are divided into linear voltage regulators, switch-type power supply voltage regulators and charge pump-type power supply voltage regulators. The linear voltage stabilizer has the characteristics of small area, small ripple, high power supply noise rejection ratio, low power consumption and the like, so that the linear voltage stabilizer is widely applied to high-precision portable consumer electronic products.
A linear regulator integrated in a portable device is required not only to provide a high load current but also to minimize its no-load quiescent current as much as possible in order to maximize current efficiency. A good load should have small output voltage variations, including small transient response overshoots and undershoots, to prevent accidental switch-off at critical times. Therefore, it is important to provide a linear regulator with fast output transient response and low load regulation rate.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a low dropout linear regulator that overcomes or at least partially solves the above problems.
The invention provides a low dropout linear regulator, which comprises a band gap reference circuit, a regulator circuit and a transient enhancement circuit, wherein the band gap reference circuit is connected with the regulator circuit;
the band-gap reference circuit is used for providing a reference voltage for the regulator circuit;
the regulator circuit comprises a first operational amplifier, a buffer, an output power tube, a first feedback resistor, a second feedback resistor and an output capacitor; the positive input end of the first operational amplifier is connected with the reference voltage, the negative input end of the first operational amplifier is connected with a feedback voltage, the output end of the first operational amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the grid electrode of the output power tube, the source electrode of the output power tube is connected with a power supply voltage, the drain electrode of the output power tube is grounded through the series structure of the first feedback resistor and the second feedback resistor, and a load output end is provided between the drain electrode of the output power tube and the ground end; the feedback voltage is output by a series point of the first feedback resistor and the second feedback resistor, one end of the output capacitor is connected with the drain electrode of the output power tube, and the other end of the output capacitor is grounded;
the transient enhancement circuit is used for providing a charging path or a discharging path for the drain electrode of the output power tube when the voltage value output by the load output end changes, so that the voltage of the load output end is stable.
Optionally, the transient boost circuit is configured to:
when the voltage output by the load output end is increased, a discharge path is provided for the drain electrode of the output power tube, so that the voltage of the load output end is reduced;
and when the voltage output by the load output end is reduced, a charging path is provided for the drain electrode of the output power tube, so that the voltage of the load output end is increased.
Optionally, the transient enhancement circuit includes a discharge path formed by a second operational amplifier and a first switch tube;
the positive input end of the second operational amplifier is connected with a reference voltage, and the negative input end of the second operational amplifier is connected with a feedback voltage; the output end of the second operational amplifier is connected with the grid electrode of the first switch tube, the source electrode of the first switch tube is grounded, and the drain electrode of the first switch tube is connected with the load output end.
Optionally, the transient enhancement circuit includes a charging path formed by a third operational amplifier, an inverter and a second switching tube;
the positive input end of the third operational amplifier is connected with a reference voltage, the negative input end of the third operational amplifier is connected with a feedback voltage, the output end of the third operational amplifier is connected with the input end of the phase inverter, the output end of the phase inverter is connected with the grid electrode of the second switch tube, the source electrode of the second switch tube is grounded, and the drain electrode of the second switch tube is connected with the load output end.
Optionally, the first operational amplifier is a folded cascode operational amplifier.
Optionally, the buffer is a super follower with dynamic bias.
Optionally, the bandgap reference circuit includes an enable circuit and a bandgap reference sub-circuit, an input end of the enable circuit is connected to the power supply voltage, an output end of the enable circuit is connected to an input end of the bandgap reference sub-circuit, and an output end of the bandgap reference sub-circuit is used for outputting the reference voltage.
Optionally, the regulator circuit further includes a first miller compensation capacitor, a second miller compensation capacitor, and a compensation resistor;
one end of the first miller compensation capacitor is connected with the grid electrode of the output power tube, and the other end of the first miller compensation capacitor is connected with the load output end;
one end of the second miller compensation capacitor is connected with a series point of the first feedback resistor and the second feedback resistor, and the other end of the second miller compensation capacitor is grounded;
one end of the compensation resistor is connected with the load output end, and the other end of the compensation resistor is grounded.
Optionally, the first feedback resistor and the second feedback resistor are both polysilicon resistors.
Optionally, the power supply voltage is 1.8V, the reference voltage output by the bandgap reference circuit is 1.15V, and the load output end outputs a constant voltage of 1.5V.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
according to the low dropout regulator provided by the embodiment of the invention, the voltage of the load output end can be kept stable by arranging the transient enhancement circuit. When the voltage of the load output end changes due to the jump of the load connected with the load output end between a heavy load state and a light load state, an overshoot or undershoot phenomenon can be generated, so that the drain voltage of the output power tube changes. At this time, the transient enhancement circuit can provide a charging path or a discharging path for the drain electrode of the output power tube, so that the voltage of the output end of the load is recovered and stabilized, and the transient response of the output end is stabilized. The linear voltage regulator has the advantages of fast transient response, low load regulation, low temperature coefficient, low power consumption and high stability.
The above description is only an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description so as to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
In the drawings:
fig. 1 is a schematic circuit diagram of a linear voltage regulator according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a bandgap reference circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a regulator circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a transient enhancement circuit according to an embodiment of the present invention;
fig. 5 to 12 are schematic diagrams of simulation results provided by the embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be referred to by the same or similar reference numerals.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and examples of the present disclosure are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and examples of the present application may be combined with each other without conflict.
Fig. 1 is a schematic circuit diagram of a linear regulator according to an embodiment of the present invention, and as shown in fig. 1, the linear regulator 100 includes a bandgap reference circuit 110, a regulator circuit 120, and a transient enhancement circuit 130.
The bandgap reference circuit 110 is used to provide a reference voltage Vref for the regulator circuit 120;
the regulator circuit 120 includes a first operational amplifier OP1, a Buffer, an output power transistor PM0, a first feedback resistor R01, a second feedback resistor R02, and an output capacitor CL. The positive input end of the first operational amplifier OP1 is connected with the reference voltage Vref, the negative input end of the first operational amplifier OP1 is connected with the feedback voltage Vfb, the output end of the first operational amplifier OP1 is connected with the input end of the Buffer, and the output end of the Buffer is connected with the grid of the output power tube PM 0. The source electrode of the output power tube PM0 is connected with a power voltage Vin, the drain electrode of the output power tube PM0 is grounded through a series structure of a first feedback resistor R01 and a second feedback resistor R02, and a load output end Vout is provided between the drain electrode of the output power tube PM0 and the ground end. The series point of the first feedback resistor R01 and the second feedback resistor R02 outputs the feedback voltage Vfb. One end of the output capacitor CL is connected with the drain electrode of the output power tube PM0, and the other end of the output capacitor CL is grounded.
The transient enhancement circuit 130 is configured to provide a charging path or a discharging path for the drain of the output power transistor PM0 when the voltage value of the Vout output by the load output terminal changes, so as to stabilize the voltage of the Vout output by the load.
As shown in fig. 1, the first feedback resistor R01, the second feedback resistor R02 and the first operational amplifier OP1 form a negative feedback loop to control the gate voltage of the output power transistor PM 0. The linear regulator has a function that when the voltage Vout at the output end of the load changes, the first operational amplifier OP1 controls the gate voltage of the output power transistor PM0 in a feedback manner to maintain the output voltage Vout constant. When a load connected with the load output end jumps from a heavy load to a light load, because the current provided by the output power tube PM0 is far larger than the load requirement, the redundant current can be charged through the output capacitor CL, so that the voltage Vout at the load output end is increased (at the moment, the overshoot phenomenon occurs in the output end potential), the voltage at the Vfb point is increased, the output end of the first operational amplifier OP1 controls the grid voltage of the output power tube PM0 to be increased, and the current provided by the output power tube PM0 is reduced to the load current. On the contrary, when the load is changed from light load jump to heavy load, because the current provided by the output power tube PM0 cannot meet the load requirement, the load current is discharged and flows through the output capacitor CL, so that the voltage Vout at the output end of the load is reduced (at this time, undershoot occurs in the output end potential), the voltage at the Vfb point is reduced, the output end of the first operational amplifier OP1 controls the gate voltage of the output power tube PM0 to be reduced, and the current provided by the output power tube PM0 is increased to the load current.
The transient response of the linear voltage regulator characterizes the pulse size and the recovery time of the output voltage Vout when the load connected with the output end of the load suddenly changes. When the load current is in light-load jump and heavy-load, the current provided by the output power tube PM0 can not meet the load requirement, the output capacitor CL discharges to the load, the output voltage is rapidly reduced, and undershoot is generated. On the contrary, when the load current jumps from a heavy load to a light load, the current provided by the output power tube PM0 exceeds the load requirement, the output power tube PM0 charges the output capacitor CL, the output voltage rapidly rises, and overshoot is generated. Transient response is enhanced, namely, the overshoot voltage and the undershoot voltage are reduced by adopting a circuit technology.
Load adjustment rate: this indicator characterizes the ability of the output voltage to remain constant as the load current changes. A low load regulation rate causes the output voltage variation to be smaller.
Optionally, the first operational amplifier OP1 is a folded cascode operational amplifier, so that power consumption is low, gain is high, and decoupling input stage transconductance and output impedance can be separately adjusted.
Optionally, the buffer is a Super-Follower (Super-gm Follower) with dynamic bias. When the super-follower is used as a buffer, the transconductance of the follower can be increased due to the unique structure of the super-follower, so the super-follower is called as super-gm, wherein the gm is the transconductance. By dynamic biasing is meant that MP21 and MP18 of fig. 3 are dynamic biasing currents that can change the current of the buffer as well as the transconductance gm.
By using the follower structure of super-gm, the current of the output power tube PM0 can be detected while increasing the loop gain, and the equivalent gm can be adjusted to follow and adjust the gate voltage of the output power tube PM 0.
In this embodiment, the output power transistor PM0 is a P-channel fet, and when the gate voltage of the output power transistor PM0 increases, the drain voltage thereof decreases, and when the gate voltage of the output power transistor PM0 decreases, the drain voltage thereof increases.
Optionally, the first feedback resistor R01 and the second feedback resistor R02 are both polysilicon resistors, so that the accuracy is higher.
Optionally, as shown in fig. 1, the regulator circuit 120 further includes a first miller compensation capacitor C01, a second miller compensation capacitor C01, and a compensation resistor RL.
One end of the first miller compensation capacitor C01 is connected to the gate of the output power transistor PM0, and the other end of the first miller compensation capacitor C01 is connected to the load output terminal Vout.
One end of the second miller compensation capacitor C02 is connected with the series point of the first feedback resistor R01 and the second feedback resistor R02, and the other end of the second miller compensation capacitor C02 is grounded.
One end of the compensation resistor RL is connected with the load output end Vout, and the other end of the compensation resistor RL is grounded.
By arranging the first miller compensation capacitor C01 and the second miller compensation capacitor C02, the stability of the circuit can be ensured. By setting the compensation resistor RL, the load output terminal voltage Vout caused by circuit failure can be prevented from being too large.
Optionally, the transient boost circuit 130 is configured to:
when the voltage of the load output end Vout rises, a discharge path is provided for the drain electrode of the output power tube PM0, so that the voltage of the load output end Vout is reduced;
when the voltage of the load output terminal Vout decreases, a charging path is provided for the drain of the output power transistor PM0, so that the voltage of the load output terminal Vout increases.
Specifically, when the load jumps from a heavy load to a light load, the voltage Vout at the load output end rises, and at this time, a discharge path is provided for the drain of the output power transistor PM0, and an extra bleed path can be provided to bleed the heavy load current to the light load current, so that the voltage Vout at the load output end is reduced and stabilized. Conversely, when the load jumps from a light load to a heavy load, the voltage Vout of the load output end is reduced, and at this time, a charging path is provided for the drain of the output power tube PM0, so as to provide the load with the required current, and charge the light load current to the heavy load current, so that the voltage Vout of the load output end is raised and recovered to be stable.
Optionally, the transient enhancement circuit 130 includes a discharge path formed by the second operational amplifier OP2 and the first switching tube NM 1.
The positive input end of the second operational amplifier OP2 is connected to the reference voltage Vref, the negative input end of the second operational amplifier OP2 is connected to the feedback voltage Vfb, and the output end of the second operational amplifier OP2 is connected to the gate of the first switching tube NM 1. The source of the first switch tube NM1 is grounded, and the drain of the first switch tube NM1 is connected to the load output terminal Vout.
Optionally, the transient enhancement circuit 130 includes a charging path formed by a third operational amplifier OP3, an inverter INV, and a second switching tube PM 1.
The positive input end of the third operational amplifier OP3 is connected with the reference voltage Vref, the negative input end of the third operational amplifier OP3 is connected with the feedback voltage Vfb, the output end of the third operational amplifier OP3 is connected with the input end of the inverter INV, the output end of the inverter INV is connected with the grid of the second switch tube PM1, the source of the second switch tube PM1 is grounded, and the drain of the second switch tube PM1 is connected with the load output end Vout.
It should be noted that the charging path and the discharging path do not affect each other in the actual operation process (because the triggering conditions are different, at most one is triggered, i.e., charging or discharging, and neither charging nor discharging). When the charging path operates, the second operational amplifier OP2 outputs a low level, and the first switch NM1 is turned off. The third operational amplifier OP3 outputs a high level, which is a low level after passing through the inverter INV, and the second switch tube PM1 is turned on to provide a charging path for the load output terminal Vout. When the discharging path operates, the second operational amplifier OP2 outputs a high level, and the first switch NM1 is turned on to provide the discharging path for the load output terminal Vout. The third operational amplifier OP3 outputs a low level, which is a high level after passing through the inverter INV, and the second switch tube PM1 is turned off. When the load does not jump, the voltage Vout of the load output end is unchanged, and at the moment, the charge-discharge path is completely cut off: that is, the second operational amplifier OP2 outputs a high level, and the first switch tube NM1 is turned off. Meanwhile, the second operational amplifier OP3 outputs a low level, and the second switching tube PM1 is turned off.
In the embodiment of the present invention, the first operational amplifier OP2 and the second operational amplifier OP3 are both common five-transistor operational amplifiers.
Optionally, as shown in fig. 1, the BandGap reference circuit 110 includes an enable circuit EN and a BandGap reference sub-circuit BandGap. The input end of the enable circuit EN is connected with the power voltage Vin, the output end of the enable circuit EN is connected with the input end of the BandGap reference sub-circuit BandGap, and the output end of the BandGap reference sub-circuit BandGap is used for outputting the reference voltage Vref. The enabling circuit EN is adopted to further play a role in reducing power consumption.
In one implementation of the embodiment of the present disclosure, the power voltage Vin is 1.8V, the reference voltage Vref output by the bandgap reference circuit 110 is 1.15V, and the load output terminal Vout outputs a constant voltage of 1.5V.
Fig. 2 is a schematic structural diagram of a bandgap reference circuit according to an embodiment of the present invention, and as shown in fig. 2, the bandgap reference circuit 110 includes a plurality of transistors (Q1-Q3), a plurality of N-type enhanced MOS (Metal-Oxide-Semiconductor Field-Effect transistors) (MN 1-MN 5), a plurality of P-type enhanced MOS (MP 1-MP 10), and resistors (R1-R2).
Fig. 3 is a schematic structural diagram of a regulator circuit according to an embodiment of the present invention, and as shown in fig. 3, a plurality of N-type enhancement MOS transistors (MN 6 to MN 9) and a plurality of P-type enhancement MOS transistors (MP 11 to MP 15) in the regulator circuit 120 form a first operational amplifier OP1. The buffer Bffer is formed by a plurality of N-type enhanced MOS tubes (MN 10-MN 13) and a plurality of P-type enhanced MOS tubes (MP 16-MP 21).
Fig. 4 is a schematic structural diagram of a transient enhancement circuit according to an embodiment of the present invention, and as shown in fig. 4, a plurality of N-type enhancement MOS transistors (MN 14 to MN 15) and a plurality of P-type enhancement MOS transistors (MP 22 to MP 24) in the transient enhancement circuit 130 form a second operational amplifier OP2.
The transient enhancement circuit 130 includes a plurality of N-type enhancement MOS transistors (MN 16-MN 17) and a plurality of P-type enhancement MOS transistors (MP 25-MP 27) which form a third operational amplifier OP3.
The N-type enhancement MOS transistor MN18 and the P-type enhancement MOS transistor MP28 in the transient enhancement circuit 130 form an inverter INV.
The N-type enhancement MOS transistor MP29 in fig. 4 and the second switch PM1 in fig. 1 are the same transistor, and the N-type enhancement MOS transistor MN19 in fig. 4 and the first switch NM1 in fig. 1 are the same transistor.
It should be noted that, each resistor in the linear regulator provided in the embodiments of the present invention may be a well resistor, a poly resistor, or a passive resistor, which is not limited in the present invention.
The following is a simulation result of the cadence shunt of the low dropout regulator according to the embodiment of the present invention. Fig. 5 to 12 are schematic diagrams of simulation results provided by the embodiment of the present invention.
1. Simulation of temperature characteristics
Temperature characteristics of the design: when the load is no-load to 100mA, DC scanning at-40-150 ℃ is carried out on the temperature, the temperature simulation result of the band-gap reference circuit is shown in figure 5, and it can be seen that the Vref is 1.1516V at the highest, 1.15137V at the lowest, the difference is 0.23mV, and the temperature drift coefficient PPM expression is as follows:
T＝(Vmax-Vmin)/(Vmean(Tmax-Tmin))×10^6(ppm/℃)
the temperature drift coefficient of the bandgap reference circuit is as follows: 1.05 ppm/DEG C. Wherein Vmax =1.1516v, vmin =1.15137v, vmean =, tmax = -40 ℃, tmin =150 ℃.
2. Quiescent current simulation
The simulation mode is as follows: the current flowing through the supply voltage Vin is simulated transiently. (1) And under the no-load condition, the low dropout linear regulator works for quiescent current. As a result of the simulation, as shown in FIG. 6, when Vin (VDD) is 1.8V and EN is 0, the circuit operates and the quiescent current is 31.85 μ A. (2) And static current when the low dropout linear regulator is switched off. As shown in FIG. 7, when Vin is 1.8V and EN is 1.8V, the LDO is turned off, and the quiescent current is 630.65nA.
3. Stability simulation
And (3) performing stability simulation on the full load range and different process angles: the circuit is connected into a unit negative feedback mode through an Iprobe, and stb simulation is adopted. Simulation results as shown in the following figures, fig. 8 and 9 are simulation results with loads of 100uA and 100mA, respectively, and phase margins of 88deg and 87deg, respectively. It can be seen that the phase margin values in both of the above simulation results are high, and thus the circuit has good stability in the full load range.
4. Transient simulation
Simulation setting parameters: the power voltage Vin is connected with the voltage NEN of the enable end (when the circuit is designed, the circuit works when EN is in low level, so the circuit is connected with the NEN of EN in reverse direction), the jump is between 0 and 1.8V, and the rising and falling edge time is as follows: 1us. Transient simulation results are shown in fig. 10 to 11, where fig. 11 shows the simulation results after transient enhancement, with an overshoot of 62mV and an undershoot of 125mV, and it can be seen from comparison of fig. 10 and 11 that the transient characteristics are optimized.
5. Load regulation rate simulation
The load regulation rate is defined as the change amount Δ VI of the output voltage caused by the change of the load current under the condition that the input voltage Vin is kept unchangedOUTWith the amount of change Δ I of the load currentOUTThe ratio of (a) to (b). The load regulation rate reflects the influence of the load current on the output voltage, and the smaller the value, the better. The expression is as follows:
load regulation rate = (Δ V)OUT)/(ΔIOUT)
In the design, when Vin is 1.8V, DC scanning simulation is performed in a full load range (100 muA-100 mA), and the simulation result is shown in the following FIG. 12, it can be seen that the voltage of Vout at the load output end is 1.5V at the highest, 1.497V at the lowest, the difference is 3mV, and the load regulation rate is 0.03 (mV/mA).
From the simulation results, the low dropout regulator provided by the invention has a low load regulation rate of 0.03 (mV/mA); has an off quiescent current of 630nA and an operating quiescent current of 32 uA; a fast transient response with an overshoot of 62mV and an undershoot of 125 mV; and the phase margin in the full load range is more than 85deg, so that the stability is better. In conclusion, the low dropout regulator provided by the invention has the characteristics of quick transient response, low load regulation rate, low temperature coefficient, low power consumption, high stability and the like.
According to the low dropout linear regulator provided by the embodiment of the invention, the voltage at the output end of the load can be kept stable by arranging the transient enhancement circuit. When the voltage of the load output end changes due to the jump of the load connected with the load output end between a heavy load state and a light load state, an overshoot or undershoot phenomenon can be generated, so that the drain voltage of the output power tube changes. At this time, the transient enhancement circuit can provide a charging path or a discharging path for the drain of the output power tube, so that the voltage of the load output end is recovered and stabilized, and the transient response of the output end is stabilized. The linear voltage regulator has the advantages of fast transient response, low load regulation, low temperature coefficient, low power consumption and high stability.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (10)
1. A low dropout regulator comprises a band gap reference circuit, a regulator circuit and a transient enhancement circuit;
the band-gap reference circuit is used for providing a reference voltage for the regulator circuit;
the regulator circuit comprises a first operational amplifier, a buffer, an output power tube, a first feedback resistor, a second feedback resistor and an output capacitor; the positive input end of the first operational amplifier is connected with the reference voltage, the negative input end of the first operational amplifier is connected with a feedback voltage, the output end of the first operational amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the grid electrode of the output power tube, the source electrode of the output power tube is connected with a power supply voltage, the drain electrode of the output power tube is grounded after passing through the series structure of the first feedback resistor and the second feedback resistor, and a load output end is provided between the drain electrode of the output power tube and the ground end; the feedback voltage is output by a series point of the first feedback resistor and the second feedback resistor, one end of the output capacitor is connected with the drain electrode of the output power tube, and the other end of the output capacitor is grounded;
the transient enhancement circuit is used for providing a charging path or a discharging path for the drain electrode of the output power tube when the voltage value output by the load output end changes, so that the voltage of the load output end is stable.
2. The low dropout linear regulator of claim 1 wherein the transient enhancement circuit is configured to:
when the voltage of the load output end is increased, a discharge path is provided for the drain electrode of the output power tube, so that the voltage of the load output end is reduced;
and when the voltage of the load output end is reduced, a charging path is provided for the drain electrode of the output power tube, so that the voltage of the load output end is increased.
3. The low dropout regulator of claim 1 wherein the transient enhancement circuit comprises a discharge path formed by a second operational amplifier and a first switching transistor;
the positive input end of the second operational amplifier is connected with a reference voltage, and the negative input end of the second operational amplifier is connected with a feedback voltage; the output end of the second operational amplifier is connected with the grid electrode of the first switch tube, the source electrode of the first switch tube is grounded, and the drain electrode of the first switch tube is connected with the load output end.
4. The LDO of claim 1, wherein the transient enhancement circuit comprises a charging path consisting of a third operational amplifier, an inverter, and a second switching transistor;
the positive input end of the third operational amplifier is connected with a reference voltage, the negative input end of the third operational amplifier is connected with a feedback voltage, the output end of the third operational amplifier is connected with the input end of the phase inverter, the output end of the phase inverter is connected with the grid electrode of the second switch tube, the source electrode of the second switch tube is grounded, and the drain electrode of the second switch tube is connected with the load output end.
5. The low dropout regulator according to claim 1, wherein the first operational amplifier is a folded cascode operational amplifier.
6. The low dropout regulator of claim 1 wherein the buffer is a super follower with dynamic bias.
7. The low dropout regulator according to claim 1, wherein the bandgap reference circuit comprises an enable circuit and a bandgap reference sub-circuit, an input terminal of the enable circuit is connected to the power supply voltage, an output terminal of the enable circuit is connected to an input terminal of the bandgap reference sub-circuit, and an output terminal of the bandgap reference sub-circuit is used for outputting the reference voltage.
8. The low dropout linear regulator of claim 1 wherein the regulator circuit further comprises a first miller compensation capacitor, a second miller compensation capacitor, and a compensation resistor;
one end of the first Miller compensation capacitor is connected with the grid electrode of the output power tube, and the other end of the first Miller compensation capacitor is connected with the load output end;
one end of the second miller compensation capacitor is connected with a series point of the first feedback resistor and the second feedback resistor, and the other end of the second miller compensation capacitor is grounded;
one end of the compensation resistor is connected with the load output end, and the other end of the compensation resistor is grounded.
9. The low dropout regulator of claim 1 wherein the first feedback resistor and the second feedback resistor are polysilicon resistors.
10. The low dropout regulator according to claim 1, wherein the power supply voltage is 1.8V, the reference voltage outputted by the bandgap reference circuit is 1.15V, and the load output terminal outputs a constant voltage of 1.5V.
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| CN202210689518.5A CN115268554A (en) | 2022-06-16 | 2022-06-16 | Low dropout regulator |
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| CN116578152A (en) * | 2023-05-25 | 2023-08-11 | 西安电子科技大学 | Zero-setting resistor and active feedforward double-compensation non-output capacitor LDO circuit |
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