CN117826926B - Low-power consumption LDO circuit with double loop control - Google Patents
Low-power consumption LDO circuit with double loop control Download PDFInfo
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Abstract
The invention discloses a low-power consumption LDO circuit controlled by double loops, relates to a system for adjusting electric variables or magnetic variables, and provides a scheme for solving the problem of high static power consumption in the prior art. Sampling the grid node voltage of the power tube, enabling the heavy-load loop to work in an intervening manner when the grid node voltage is low, otherwise enabling the control output of the heavy-load loop to be saturated; and the input end of the light load loop utilizes a common gate PMOS tube to recycle and reuse the leakage current of the power tube. The low-power-consumption power supply circuit has the advantages that the common-gate PMOS tube is used as a light-load loop input stage to multiplex the leakage current of the power tube, and the static power consumption is lower than that of the traditional structure under the low load. The loop switching function is supported, the light-load loop and the heavy-load loop work are adaptively switched by detecting the magnitude of the load current, the ultra-low power consumption is ensured by the light-load loop work under the low load, and the requirement of low power consumption is met; and the heavy-duty loop works under high load, so that high voltage precision is ensured.
Description
Technical Field
The invention relates to a system for adjusting an electric variable or a magnetic variable, in particular to a low-power consumption LDO circuit with double loop control.
Background
A low dropout linear regulator (Low Dropout Regulator, LDO for short).
A Power Management IC (PMIC) is a basic module for providing a power supply voltage for the internet of things and mobile devices, and is mainly divided into a switching type and a linear voltage regulator. LDOs are widely used for supplying power to digital modules, memories and noise sensitive modules due to their high precision, low noise, small volume and relatively simple structure. For internet of things (IoT) electronic devices, because there is typically a long standby time to wait for messages from the cloud server, an energy efficient Power Management (PM) module needs to be embedded to extend the battery run time, which is determined by the quiescent current of the power management module in the standby state.
The LDO with off-chip capacitor is generally arranged at the output of the LDO due to the larger output capacitance. The load current is small under light load, the output impedance is large, the stability is easy to be ensured due to the fact that the main pole point is very low frequency, under heavy load, the main pole point moves to a high frequency position due to the fact that the output impedance is reduced, the main pole point and the secondary pole point are too close, the phase margin is poor, and therefore the worst stability condition occurs under high load.
In addition, since the power tube size is generally large to cope with a wide load current range, the leakage current of the power tube is in nA level under light load. The scheme adopted by most low-power designs at present is to use a dynamic bias technology, reduce current supply and even turn off a power consumption module under light load so as to realize low-power consumption requirements, but do not process leakage current of a power tube. For circuits at the nA level, this leakage current accounts for a large portion of the static power consumption.
Disclosure of Invention
The invention aims to provide a dual-loop controlled low-power consumption LDO circuit so as to solve the problems in the prior art.
The low-power consumption LDO circuit with double loop control comprises a light load loop and a heavy load loop;
Sampling the grid node voltage of the power tube, enabling the heavy-load loop to work in an intervening manner when the grid node voltage is low, otherwise enabling the control output of the heavy-load loop to be saturated; and the input end of the light load loop utilizes a common gate PMOS tube to recycle and reuse the leakage current of the power tube.
The non-inverting input end of the error amplifier is connected with the feedback voltage, the inverting input end of the error amplifier is connected with the first reference voltage, the output end of the error amplifier is connected with the first node, and the working current of the error amplifier is provided by the fourth current source;
the source electrode of the switching tube is connected with VDD, the drain electrode of the switching tube is connected with the first node, the grid electrode of the switching tube is connected with the output end of the hysteresis comparator;
The source electrode of the third MOS tube is connected with the second node, the drain electrode of the third MOS tube is connected with the drain electrode of the first MOS tube, and the grid electrode of the third MOS tube is connected with the first node;
The source electrode of the first MOS tube is connected with the output voltage, and the grid electrode of the first MOS tube is connected with the static voltage bias point;
The source electrode of the second MOS tube is connected with a second reference voltage, and the drain electrode and the grid electrode of the second MOS tube are grounded through a first current source after being at a static voltage bias point;
The source electrode of the sensing MOS tube is connected with VDD, the drain electrode of the sensing MOS tube is connected with the positive input end of the hysteresis comparator and is grounded through a sensing resistor, and the grid electrode of the sensing MOS tube is connected with a grid electrode node;
A third current source is connected in series between VDD and the gate node;
the source electrode of the power tube is connected with VDD, the drain electrode of the power tube is connected with output voltage, the grid electrode of the power tube is connected with the grid electrode node;
the second current source is connected in series between the second node and the ground;
The inverting input end of the hysteresis comparator is connected with a first reference voltage;
the source electrode of the fourth MOS tube is connected with the grid node, the drain electrode of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is connected with the second node;
one end of the first feedback resistor is connected with the output voltage after being connected in parallel with the feedback capacitor, the other end of the first feedback resistor is connected with the second feedback resistor in series and then grounded, and the voltage of the connection point of the first feedback resistor and the second feedback resistor is the feedback voltage;
the output capacitor is connected in series between the output voltage and ground.
The first MOS tube, the switch tube, the second MOS tube, the fourth MOS tube, the sensing MOS tube and the power tube are PMOS tubes; the third MOS tube is an NMOS tube.
The current magnitudes of the first current source, the second current source, the third current source and the fourth current source are respectively mirrored in the load current of the power tube in proportion; and the control signals of the third current source and the fourth current source are sampled at the static voltage bias point.
The low-power consumption LDO circuit with double loop control has the advantages that the common-gate PMOS tube is used as the light-load loop input stage to multiplex the leakage current of the power tube, so that the static power consumption is lower under the condition of low load than that of the traditional structure. The loop switching function is supported, the light-load loop and the heavy-load loop work are adaptively switched by detecting the magnitude of the load current, the ultra-low power consumption is ensured by the light-load loop work under the low load, and the requirement of low power consumption is met; and the heavy-duty loop works under high load, so that high voltage precision is ensured. The dynamic bias current technique is used to ensure stability over the full load range, maintaining high current efficiency over the entire load current range.
Drawings
Fig. 1 is a schematic diagram of a low power LDO circuit according to the present invention.
Fig. 2 is a schematic diagram of the structure of the error amplifier according to the present invention.
Fig. 3 is a schematic diagram of the structure of each current source in the present invention.
FIG. 4 is a schematic diagram of pole distribution of the LDO circuit with low power consumption under different loads.
Reference numerals:
M1 to M4: first to fourth MOS transistors;
msw-switch tube, mp-power tube, msen-sensing MOS tube;
U1-hysteresis comparator and EA-error amplifier;
rsen-sense resistor, rf 1-first feedback resistor, rf 2-second feedback resistor;
cf-feedback capacitance, CL-output capacitance;
vref 1-a first reference voltage, vref 2-a second reference voltage;
vo-output voltage, vfb-feedback voltage, vsen-sense voltage;
Vbp-static voltage bias point, va-first node, vb-second node, vg-gate node;
I1 to I4: first to fourth current sources.
Detailed Description
As shown in fig. 1, the specific structure of the low-power consumption LDO circuit controlled by the dual loop in the invention is as follows:
the non-inverting input terminal of the error amplifier EA is connected to the feedback voltage Vfb, the inverting input terminal of the error amplifier EA is connected to the first reference voltage Vref1, the output terminal of the error amplifier EA is connected to the first node Va, and the operating current of the error amplifier EA is provided by the fourth current source I4.
The source of the switching tube Msw is connected with VDD, the drain of the switching tube Msw is connected with the first node Va, and the gate of the switching tube Msw is connected with the output end of the hysteresis comparator U1.
The source electrode of the third MOS tube M3 is connected with the second node Vb, the drain electrode of the third MOS tube M3 is connected with the drain electrode of the first MOS tube M1, and the grid electrode of the third MOS tube M3 is connected with the first node Va.
The source electrode of the first MOS tube M1 is connected with the output voltage Vo, and the grid electrode of the first MOS tube M1 is connected with the static voltage bias point Vbp.
The source electrode of the second MOS tube M2 is connected with the second reference voltage Vref2, and the drain electrode and the grid electrode of the second MOS tube M2 are grounded through the first current source I1 after being at the same point at the static voltage bias point Vbp.
The source electrode of the sensing MOS tube Msen is connected with VDD, the drain electrode of the sensing MOS tube Msen is connected with the non-inverting input end of the hysteresis comparator U1 and grounded through a sensing resistor Rsen, and the gate electrode of the sensing MOS tube Msen is connected with a gate node Vg.
The third current source I3 is connected in series between VDD and the gate node Vg.
The source of the power tube Mp is connected with the VDD, the drain of the power tube Mp is connected with the output voltage Vo, and the grid of the power tube Mp is connected with the grid node Vg.
The second current source I2 is connected in series between the second node Vb and ground.
The inverting input terminal of the hysteresis comparator U1 is connected with the first reference voltage Vref1.
The source electrode of the fourth MOS tube M4 is connected with the grid node Vg, the drain electrode of the fourth MOS tube M4 is grounded, and the grid electrode of the fourth MOS tube M4 is connected with the second node Vb.
One end of the first feedback resistor Rf1 and the feedback capacitor Cf are connected in parallel and then connected with the output voltage Vo, the other end of the first feedback resistor Rf1 and the feedback capacitor Cf are connected with the second feedback resistor Rf2 in series and then grounded, and the voltage of the connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is feedback voltage Vfb.
The output capacitor CL is connected in series between the output voltage Vo and ground.
The first MOS tube M1, the switch tube Msw, the second MOS tube M2, the fourth MOS tube M4, the sensing MOS tube Msen and the power tube Mp are PMOS tubes; the third MOS tube M3 is an NMOS tube.
The fourth MOS transistor M4 forms a P buffer stage to improve the capability of driving the gate of the power transistor Mp, and pushes the pole of the gate node Vg to high frequency.
The third MOS tube M3 forms an N buffer stage to play a role in assisting loop switching.
The current sensing function module is composed of a sensing MOS tube Msen, a sensing resistor Rsen, a switching tube Msw and a hysteresis comparator U1. The sensing MOS tube Msen is a mirror image tube of the power tube Mp, and mirrors the magnitude of the load current by sharing the gate, scaling the size and the like. The mirror current is converted into a voltage signal on the sensing resistor Rsen, the voltage signal is compared with the first reference voltage Vref1 through the hysteresis comparator U1, and the output value is used for controlling the state of the switching tube Msw so as to realize the switching of the light-load loop and the heavy-load loop.
The first MOS tube M1 and the second MOS tube M2 form an auxiliary module, and the second MOS tube M2 provides static voltage of a static voltage bias point Vbp for the grid electrode of the first MOS tube M1. The first MOS tube M1 and the second MOS tube M2 form a common gate amplifier, so that the output voltage Vo is enabled to follow the second reference voltage Vref2 under the condition that only a light load loop is activated, and the voltage precision is ensured. Meanwhile, the common grid connection method can multiplex leakage current of the power tube Mp.
The circuit of the error amplifier EA is shown in fig. 2, and a cross-coupling method of the prior art is used to achieve high gain. By constructing a positive feedback loop to generate negative resistance effect, the impedance is increased to achieve the purpose of improving loop gain and realizing high voltage precision control.
The first current source I1 to the fourth current source I4 adopt dynamic current bias in the prior art, and the dynamic current bias technology is used for biasing each internal module so as to ensure high current efficiency. The circuit structure is as shown in fig. 3, and by scaling the common gate and the size, the magnitude of the mirror load current is mirrored and then the bias current is provided to each module inside through the corresponding current mirror.
The output voltage Vo is mainly modulated by two negative feedback loops: the heavy load loop is that the output voltage Vo reaches the power tube Mp through the error amplifier EA, the N buffer stage and the P buffer stage; the light load loop is that the output voltage Vo passes through the auxiliary module and the P buffer stage to reach the power tube Mp. Under light load, the load current is small, the voltage of a grid node Vg is higher, a switching tube Msw is conducted, the voltage of a first node Va node is VDD, the output saturation of an error amplifier EA does not play a modulation role, at the moment, a heavy load loop is equivalent to being closed, and the output voltage Vo is regulated and controlled through the light load loop. Under heavy load, the voltage of the gate node Vg is reduced, the switching tube Msw is disconnected, the error amplifier EA outputs a normal value, the heavy load loop is started, and the light load loop is disabled.
Frequency compensation:
Only the light load loop is activated and the heavy load loop is closed under low load, and the output impedance and the output capacitance CL are both larger, wherein the output capacitance cl=1uf, so that the primary pole is at very low frequency at the output end, and the secondary pole is at the second node Vb.
Under high load, the heavy-duty loop is activated, the light-duty loop gain is less than 0, and thus the overall loop characteristics depend on the heavy-duty loop. Since both the output impedance and the output capacitance CL are large, the dominant pole is still at the output and the minor pole is at the first node Va. The two feedback resistors are both larger and 800mΩ, and the feedback voltage Vfb and the parasitic capacitance of the error amplifier EA generate a low frequency pole, which affects the stability of the heavy-duty loop at about 10 Khz. Therefore, a feedback capacitor Cf is connected to the output end, and forms a pole-zero pair with the first feedback resistor Rf1 and the second feedback resistor Rf2, so that the stage point generated due to the reasons is eliminated.
In the present invention, pole distributions of the low-power consumption LDO circuit controlled by two loops are shown in fig. 4, where Pout, pa and Pb represent poles of the output terminal, the first node Va and the second node Vb, respectively.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.
Claims (3)
1. The low-power consumption LDO circuit controlled by double loops is characterized by comprising a light-load loop and a heavy-load loop;
sampling the voltage of a grid node (Vg) of a power tube (Mp), and enabling the heavy-load loop to work in an intervening manner when the voltage of the grid node (Vg) is low, otherwise enabling the control output of the heavy-load loop to be saturated; the input end of the light load loop utilizes a common gate PMOS tube to recycle and reuse the leakage current of the power tube;
the structure is as follows:
The non-inverting input end of the Error Amplifier (EA) is connected with the feedback voltage (Vfb), the inverting input end of the Error Amplifier (EA) is connected with the first reference voltage (Vref 1), the output end of the Error Amplifier (EA) is connected with the first node (Va), and the working current of the Error Amplifier (EA) is provided by the fourth current source (I4);
The source electrode of the switching tube (Msw) is connected with VDD, the drain electrode of the switching tube (Msw) is connected with the first node (Va), and the grid electrode of the switching tube (Msw) is connected with the output end of the hysteresis comparator (U1);
The source electrode of the third MOS tube (M3) is connected with the second node (Vb), the drain electrode of the third MOS tube (M3) is connected with the drain electrode of the first MOS tube (M1), and the grid electrode of the third MOS tube (M3) is connected with the first node (Va);
The source electrode of the first MOS tube (M1) is connected with the output voltage (Vo), and the grid electrode of the first MOS tube (M1) is connected with the static voltage bias point (Vbp);
the source electrode of the second MOS tube (M2) is connected with a second reference voltage (Vref 2), and the drain electrode and the grid electrode of the second MOS tube (M2) are grounded through a first current source (I1) after being at a static voltage bias point (Vbp);
The source electrode of the sensing MOS tube (Msen) is connected with VDD, the drain electrode of the sensing MOS tube (Msen) is connected with the non-inverting input end of the hysteresis comparator (U1) and grounded through a sensing resistor (Rsen), and the grid electrode of the sensing MOS tube (Msen) is connected with a grid node (Vg);
a third current source (I3) is connected in series between VDD and a gate node (Vg);
the source electrode of the power tube (Mp) is connected with VDD, the drain electrode of the power tube (Mp) is connected with output voltage (Vo), and the grid electrode of the power tube (Mp) is connected with grid electrode node (Vg);
the second current source (I2) is connected in series between the second node (Vb) and ground;
The inverting input end of the hysteresis comparator (U1) is connected with a first reference voltage (Vref 1);
the source electrode of the fourth MOS tube (M4) is connected with a grid node (Vg), the drain electrode of the fourth MOS tube (M4) is grounded, and the grid electrode of the fourth MOS tube (M4) is connected with a second node (Vb);
One end of the first feedback resistor (Rf 1) and the feedback capacitor (Cf) are connected in parallel and then connected with the output voltage (Vo), the other end of the first feedback resistor is connected with the second feedback resistor (Rf 2) in series and then grounded, and the voltage of the connection point of the first feedback resistor (Rf 1) and the second feedback resistor (Rf 2) is feedback voltage (Vfb);
the output Capacitor (CL) is connected in series between the output voltage (Vo) and ground.
2. The dual-loop controlled low-power consumption LDO circuit of claim 1, wherein the first MOS transistor (M1), the switching transistor (Msw), the second MOS transistor (M2), the fourth MOS transistor (M4), the sensing MOS transistor (Msen) and the power transistor (Mp) are PMOS transistors; the third MOS tube (M3) is an NMOS tube.
3. The dual loop controlled low power LDO circuit of claim 1, wherein the current levels of the first current source (I1), the second current source (I2), the third current source (I3) and the fourth current source (I4) are respectively proportional to the load current of the power transistor (Mp); and the control signals of the third current source (I3) and the fourth current source (I4) are sampled at a static voltage bias point (Vbp).
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