CN102981543A - Drive circuit of ultralow-power-consumption linear voltage stabilizer - Google Patents
Drive circuit of ultralow-power-consumption linear voltage stabilizer Download PDFInfo
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Abstract
The invention discloses a drive circuit of an ultralow-power-consumption linear voltage stabilizer, mainly aiming to solve the problem that the traditional drive circuit of the ultralow-power-consumption linear voltage stabilizer is not fast enough in transient response or static power consumption is increased while the transient response is improved. The drive circuit comprises a source follower circuit (1), a tail current source circuit (2) and a sampling circuit (3). The tail current source circuit (2) comprises a fixed current source (21) and a dynamic current source (22), the sampling circuit (3) is connected to the dynamic current source (22) and used for outputting sampled load current Ic, the tail current source circuit (2) is used for supplying tail current signals changing along with load current for the source follower circuit (1), and the source follower circuit (1) outputs a voltage drive signal PG. According to the invention, the dynamic current source (22) is added, so that loop compensation is facilitated, the advantages of reducing static power consumption of the linear voltage stabilizer during light load and accelerating the charge/discharge speed of a power tube grid capacitor during heavy load are achieved, the transient response speed of the linear voltage stabilizer is improved, and the drive circuit can be applied to an analogue integrated circuit.
Description
Technical field
The invention belongs to the electronic circuit technology field, particularly the linear voltage stabilizer driving circuit of super low-power consumption can be used for Analogous Integrated Electronic Circuits.
Technical background
One of the focal issue in electronic product field is that efficient is high.Linear voltage regulator is low with its output noise, cost is low, quiescent dissipation is low and output voltage stabilization and widespread use.Quiescent dissipation, output load capacity and transient response speed are the leading indicators of weighing a linear voltage regulator.Nowadays, just towards ultralow quiescent dissipation development, in the situation of not taking any measure, ultralow quiescent dissipation can inevitably be brought slower switching rate to linear voltage regulator, and this certainly will limit the transient response speed of linear voltage regulator.In actual application, the output current of linear voltage regulator may change to up to a hundred milliamperes fast from several microamperes, transient response speed can cause output voltage undershoot or upper punch amplitude excessive too slowly, back-end circuit or chip is made the mistake restart or the well damage because supply voltage is too large.
For improving the transient response speed of linear voltage regulator, it is particularly important that the driving circuit of power tube grid just seems.Existing power tube gate driver circuit mainly contains following two kinds of structures:
The output of error amplifier shown in Figure 1 directly drives linear voltage regulator power tube grid circuit.The output terminal of error amplifier directly links to each other with the power tube grid, can be with V
OUTVariation be reacted directly into the grid of power tube by error amplifier, the regulation output size of current makes V
OUTFast quick-recovery stationary value.But because the output impedance of error amplifier reaches 100,000,000 grades, and the grid stray capacitance of power tube reaches the pF level, can produce at the output terminal of error amplifier a low-frequency pole, and when the output termination underload of linear voltage regulator, i.e. R
LWhen very large, the output terminal of linear voltage regulator can produce a low-frequency pole, and two low-frequency pole in the circuit have increased the loop compensation difficulty greatly.
Source follower shown in Figure 2 drives linear voltage regulator power tube grid circuit.The grid of the NMOS pipe M1 of source follower and the voltage signal V that chip internal produces
DLink to each other, the source electrode of NMOS pipe M1 links to each other with the drain electrode of NMOS pipe M2, and the grid of NMOS pipe M2 links to each other with the voltage bias signal VBIAS that chip internal produces, and the grid of power tube P1 links to each other with the source electrode of NMOS pipe M1, the drain electrode of power tube P1 is as the output terminal of linear voltage regulator, output voltage signal V
OUT, this voltage signal V
OUTAfter divider resistance R1 and R2 dividing potential drop, obtain voltage feedback signal V
FB, this voltage feedback signal V
FBThe reference voltage V ref that produces with chip internal obtains stable output voltage signal after the error amplifier effect of chip internal.Work as V
OUTDuring increase, V
FBIncrease, the output voltage of error amplifier increases, and power tube current reduces, V
OUTReduce and return to steady-state value.This linear voltage regulator transient response speed is determined by the speed that discharges and recharges of power tube grid stray capacitance.The source follower tail current is larger, the grid stray capacitance to discharge and recharge speed faster, the transient response of linear voltage regulator is better, quiescent dissipation is larger.
Above-mentioned two kinds of super low-power consumption linear voltage regulator driving circuits if adopt the direct driving power tube grid of the output circuit of error amplifier, then cause the loop compensation difficulty; If adopt source follower driving power tube grid circuit, increased quiescent dissipation when then improving transient response, shortened the serviceable life of linear voltage regulator.
Summary of the invention
The object of the invention is to for the deficiencies in the prior art, a kind of super low-power consumption linear voltage regulator driving circuit is provided, with the transient response speed of raising linear voltage regulator when not increasing extra quiescent dissipation, and then the serviceable life of prolongation linear voltage regulator.
For achieving the above object, the present invention includes: source follower circuit 1 and tail current source circuit 2; Tail current source circuit 2 output tail current signals link to each other with source follower circuit 1; Source follower circuit 1 output voltage drives signal P
G, it is characterized in that: tail current source circuit (2) is connected with sample circuit (3), is used for output sampling load current signal Ic;
Described tail current source circuit 2, formed by fixed current source 21 and dynamic current source 22, the bias voltage VBIAS that input end G and the chip internal in this fixed current source 21 provide links to each other, and the output terminal H in this fixed current source 21 links to each other with source follower circuit 1 as the output terminal of tail current source circuit 2; The input end E in this dynamic current source 22 links to each other with the sample rate current signal Ic of sample circuit 3 inputs, and the output terminal F in this dynamic current source 22 links to each other with the output terminal H in fixed current source 21, output tail current signal;
The dynamic current source 22 of above-mentioned linear voltage regulator driving circuit comprises two NMOS pipes, i.e. the 4th NMOS pipe M4 and the 5th NMOS pipe M5;
Described the 4th NMOS pipe M4 and the 5th NMOS pipe M5, its grid links to each other and consists of current-mirror structure, and links to each other with the drain electrode of the 4th NMOS pipe M4; Its source electrode links to each other, and is connected to ground;
Described the 4th NMOS manages the drain electrode of M4 as input end E, and links to each other with the sample rate current signal Ic of sample circuit 3 inputs;
The drain electrode of described the 5th NMOS pipe M5 is connected to the output terminal H in fixed current source 21 as output terminal F.
The sample circuit 3 of above-mentioned linear voltage regulator driving circuit comprises a PMOS pipe, two NMOS pipes, i.e. the 3rd PMOS sampling pipe M3, the 2nd NMOS pipe M2, the 6th NMOS pipe M6 and a feedback resistance R1;
Described the 2nd NMOS pipe M2, its grid is as the first input end A of sample circuit 3, with the voltage signal V of chip internal generation
DLink to each other; Its drain electrode links to each other with the supply voltage Vin of chip input; Its source electrode links to each other with the drain electrode of the 6th NMOS pipe M6;
Described the 6th NMOS pipe M6, its grid is as the second input end B of sample circuit 3, and the bias voltage VBIAS that produces with chip internal links to each other; Its source electrode is connected to ground;
Described feedback resistance R1 is connected across between the source electrode of the supply voltage Vin of chip input and the 3rd PMOS sampling pipe M3, consists of band source negative feedback circuit, guarantees that sample rate current can be not excessive;
Described the 3rd PMOS sampling pipe M3, its grid links to each other with the source electrode of the 2nd NMOS pipe M2; Its drain electrode is connected to the input end E of dynamic current source circuit 22 as the output terminal C of sample circuit 3.
The source follower circuit 1 of above-mentioned linear voltage regulator driving circuit, M1 consists of by NMOS pipe; The grid of the one NMOS pipe M1 is as input end J, with the voltage signal V of chip internal generation
DLink to each other, its drain electrode links to each other with the supply voltage Vin of chip input, and its source electrode is as output terminal I, and output voltage drives signal P
G
The present invention compared with prior art has the following advantages:
Tail current source circuit of the present invention makes the tail current size change with the variation of load current owing to increased the dynamic current source, when load is zero load or underloading, has reduced the quiescent dissipation of linear voltage regulator, has prolonged the serviceable life of linear voltage regulator; When load is heavy duty, improved the transient response speed of linear voltage regulator.
The present invention is owing to adopt source follower to isolate output and the power tube grid of error amplifier, so can be by automatically adjusting the output impedance of source follower, guarantee that the grid limit is beyond bandwidth, avoid the large output impedance of error amplifier and the low-frequency pole that the large stray capacitance of grid produces, simplified the loop compensation of circuit.
Description of drawings
The output of the existing error amplifier of Fig. 1 directly drives linear voltage regulator power tube grid schematic diagram;
The existing source follower of Fig. 2 drives linear voltage regulator power tube grid schematic diagram;
The structured flowchart of Fig. 3 driving circuit of the present invention;
The circuit theory diagrams of Fig. 4 driving circuit of the present invention;
The application example figure of Fig. 5 driving circuit of the present invention.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment.
With reference to Fig. 3, super low-power consumption linear voltage regulator driving circuit of the present invention comprises: source follower circuit 1, tail current source circuit 2 and sample circuit 3; This tail current source circuit 2 comprises fixed current source 21 and dynamic current source 22, the bias voltage VBIAS that input end G and the chip internal in this fixed current source 21 provide links to each other, the output terminal H in this fixed current source 21 links to each other with source follower circuit 1 as the output terminal of tail current source circuit 2; The input end E in this dynamic current source 22 links to each other with the sample rate current signal Ic of sample circuit 3 inputs, and the output terminal F in this dynamic current source 22 links to each other with the output terminal H in fixed current source 21, output tail current signal; The voltage signal V that the first input end A of this sample circuit 3 and chip internal produce
DLink to each other, the bias voltage VBIAS that the second input end B and the chip internal of this sample circuit 3 provide links to each other, and the output terminal C of this sample circuit 3 exports sample rate current signal Ic, is connected to the input end E in dynamic current source (22); This source follower circuit 1 output voltage drives signal P
G
With reference to Fig. 4, dynamic current of the present invention source 22 is comprised of two NMOS pipes, and namely the 4th NMOS pipe M4 and the 5th NMOS manage M5, wherein:
The 4th NMOS pipe M4 and the 5th NMOS pipe M5, its grid links to each other and consists of current-mirror structure, and the 4th NMOS pipe M4 is mirrored to sample rate current signal Ic on the branch road of the 5th NMOS pipe M5, and its size of current is followed the variation of load current and is changed; Its source electrode links to each other, and is connected to ground; The 4th NMOS manages the drain electrode of M4 as input end E, and links to each other with the sample rate current signal Ic of sample circuit 3 inputs; The 5th NMOS manages the drain electrode of M5 as output terminal F, and links to each other with the drain electrode of the 7th NMOS pipe M7 that consists of fixed current source 21.
Described source follower circuit 1, M1 consists of by NMOS pipe; The grid of the one NMOS pipe M1 is as input end J, with the voltage signal V of chip internal generation
DLink to each other, adjust the branch current size of NMOS pipe M1, the drain electrode of NMOS pipe M1 links to each other with the supply voltage Vin of chip input, and the source electrode of NMOS pipe M1 is as output terminal I, and output voltage drives signal P
G
With reference to Fig. 5, sample circuit 3 of the present invention comprises the 3rd PMOS sampling pipe M3, and the 2nd NMOS manages M2, the 6th NMOS pipe M6 and feedback resistance R1, wherein:
The 2nd NMOS manages M2, and its grid is as the first input end A of sample circuit 3, with the voltage signal V of chip internal generation
DLink to each other, adjust the branch current size of the 2nd NMOS pipe M2, as the voltage signal V of chip internal generation
DWhen becoming large, drive voltage signal P
GGrid voltage P with the 3rd PMOS sampling pipe M3
GXBecome large, the load current signal Ic that then samples reduces, otherwise works as the voltage signal V that chip internal produces
DWhen diminishing, sampling load current signal Ic increases; Its drain electrode links to each other with the supply voltage Vin of chip input; Its source electrode links to each other with the drain electrode of the 6th NMOS pipe M6, and the 2nd NMOS pipe M2 is identical with the NMOS pipe M1 type that consists of source follower circuit 1, breadth length ratio is proportional, and grid voltage is all the voltage signal V that chip internal produces
D, to guarantee the source voltage P of the 2nd NMOS pipe M2
GXDrain voltage P with NMOS pipe M1
GChange consistent;
The 6th NMOS manages M6, and its grid is as the second input end B of sample circuit 3, and the bias voltage VBIAS that produces with chip internal links to each other, and produces fixing reference current signal; Its source electrode is connected to ground;
Feedback resistance R1 is connected across between the source electrode of the supply voltage Vin of chip input and the 3rd PMOS sampling pipe M3, consists of band source negative feedback circuit, guarantees the sample rate current size within the specific limits;
The 3rd PMOS sampling pipe M3, its grid links to each other with the source electrode of the 2nd NMOS pipe M2, and grid voltage P
GXSize is followed drive voltage signal P
GVariation and change; Its drain electrode is as the output terminal C of sample circuit 3 output sampling load current signal Ic, and links to each other with the drain electrode of the 4th NMOS pipe M4 in the dynamic current source circuit 22, and the PMOS power tube P of the 3rd PMOS sampling pipe M3 and its place chip internal
HType is identical, breadth length ratio is proportional, changes consistent with the sample rate current signal Ic that guarantees the 3rd PMOS sampling pipe M3 with the load current Iload of chip.
Specific works principle of the present invention is described below in conjunction with application example:
Driving circuit of the present invention is applied in the linear voltage regulator its structure such as Fig. 5.This linear voltage regulator comprises source follower circuit 1, tail current source circuit 2, sample circuit 3, error amplifier 4 and output and feedback circuit 5.The reverse input end of this error amplifier 4 links to each other with the reference voltage V ref of chip internal, the feedback voltage signal V of the positive input of this error amplifier 4 and output and feedback circuit 5 inputs
FBLink to each other, the voltage signal of the output terminal output of this error amplifier 4 respectively with source follower circuit 1 in the grid of NMOS pipe M1 link to each other with the grid of the 2nd NMOS pipe M2 in the sample circuit 3; The P type power tube P of this output and feedback circuit 5
HGrid as input end, with the drive voltage signal P of source follower circuit 1 output
GLink to each other, its source electrode links to each other with the supply voltage Vin of chip internal, and it drains as output terminal output voltage signal V
OUT, this voltage signal V
OUTAfter divider resistance R2 and R3 dividing potential drop, obtain feedback voltage signal V
FBPull-up resistor Rload and load capacitance C
OUTParallel connection is connected across voltage signal V
OUTAnd between the ground.
When the load of linear voltage regulator is underloading or zero load, drive voltage signal P
GHigher, load current Iload is less, because the grid voltage P of the 3rd PMOS sampling pipe M3
GXFollow drive voltage signal P
GVariation and change P then
GXHigher, load current Ic is almost nil in sampling, and this moment, tail current source circuit 2 was made of fixed current source 21, had reduced the quiescent dissipation of linear voltage regulator.
When the load of linear voltage regulator is heavy duty, drive voltage signal P
GLower, load current Iload is larger, the grid voltage P of the 3rd PMOS sampling pipe M3
GXLower, Ic is larger for the sampling load current, but because the retroactive effect of feedback resistance R1, sampling load current Ic limits within the specific limits, and this moment, tail current source circuit 2 was comprised of fixed current source 21 and dynamic current source 22.Therefore when the load of linear voltage regulator was heavy duty, linear voltage regulator output terminal limit was to high-frequency mobile, and it is large that bandwidth becomes, and the tail current change of source follower circuit 1 is large, output impedance diminishes power tube P
HThe grid limit rationally arranges the transistor size of linear voltage regulator driving circuit to high-frequency mobile more, and guaranteed output tube grid limit beyond bandwidth, is conducive to loop compensation all the time.
When the supply voltage Vin of linear voltage regulator uprises suddenly, power tube P in output and the feedback circuit 5
HSource voltage uprise, load current Iload increases, output voltage signal V
OUTUprise feedback voltage signal V
FBUprise, the output voltage of error amplifier 4 uprises, voltage drive signals P
GGrid voltage P with the 3rd PMOS sampling pipe M3
GXUprise, sampling load current Ic diminishes, and the tail current signal of tail current source circuit 2 outputs diminishes power tube P
HThe charging current of grid stray capacitance increases, drive voltage signal P
GRaise fast, load current Iload reduces fast, output voltage V
OUTDiminish, the linear transient response speed of linear voltage regulator uprises.
When the load of linear voltage regulator changes to heavy duty from underloading suddenly, output voltage V
OUTDiminish feedback voltage signal V
FBDiminish, the output voltage of error amplifier diminishes, drive voltage signal P
GDiminish, sampling load current Ic increases, and the tail current signal of tail current source circuit 2 outputs increases power tube P
HThe discharge current of grid stray capacitance increases, drive voltage signal P
GReduce sooner, load current Iload increases fast, output voltage V
OUTBecome large, the load transient response speed of linear voltage regulator uprises.
The super low-power consumption linear voltage regulator driving circuit that the present invention is designed, when load was underloading or zero load, tail current source circuit 2 mainly by 21 work of fixed current source, had reduced quiescent dissipation; When load is heavy duty, load current Iload increases, tail current source circuit 2 has been accelerated the speed that discharges and recharges of power tube grid capacitance by fixed current source 21 and dynamic current source 22 co-operation, has improved load transient response speed and the linear transient response speed of linear voltage regulator; When load variations, the output impedance of source follower circuit 1 is adjusted automatically, has guaranteed power tube P
HThe grid limit all the time beyond bandwidth, be conducive to loop compensation.
It below only is a preferred example of the present invention; do not consist of any limitation of the invention; obviously under design of the present invention; can carry out different changes and improvement to its circuit; for example change described N-type source follower into P type source follower or ambipolar source follower, but these are all at the row of protection of the present invention.Thereby the present invention is not limited in disclosed specific embodiment, and its scope should contain core of the present invention and the interior all changes of protection domain that appended claims limits.
Claims (6)
1. a super low-power consumption linear voltage regulator driving circuit comprises: source follower circuit (1) and tail current source circuit (2); Tail current source circuit (2) output tail current signal links to each other with source follower circuit (1); Source follower circuit (1) output voltage drives signal P
G, it is characterized in that: tail current source circuit (2) is connected with sample circuit (3), is used for output sampling load current signal Ic;
Described tail current source circuit (2), formed by fixed current source (21) and dynamic current source (22), the input end G in this fixed current source (21) links to each other with the bias voltage VBIAS that chip internal provides, the output terminal H in this fixed current source (21) links to each other with source follower circuit (1) as the output terminal of tail current source circuit (2); The input end E in this dynamic current source (22) links to each other with the sample rate current signal Ic of sample circuit (3) input, and the output terminal F in this dynamic current source (22) links to each other with the output terminal H of fixed current source (21), output tail current signal.
2. linear voltage regulator driving circuit according to claim 1 is characterized in that dynamic current source (22), comprises two NMOS pipes, i.e. the 4th NMOS pipe M4 and the 5th NMOS pipe M5;
Described the 4th NMOS pipe M4 and the 5th NMOS pipe M5, its grid links to each other and consists of current-mirror structure, and links to each other with the drain electrode of the 4th NMOS pipe M4; Its source electrode links to each other, and is connected to ground;
Described the 4th NMOS manages the drain electrode of M4 as input end E, and links to each other with the sample rate current signal Ic of sample circuit (3) input;
The drain electrode of described the 5th NMOS pipe M5 is connected to the output terminal H in fixed current source (21) as output terminal F.
3. linear voltage regulator driving circuit according to claim 1 is characterized in that sample circuit (3), comprises a PMOS pipe, two NMOS pipes, i.e. the 3rd PMOS sampling pipe M3, the 2nd NMOS pipe M2, the 6th NMOS pipe M6 and a feedback resistance R1;
Described the 2nd NMOS pipe M2, its grid is as the first input end A of sample circuit (3), with the voltage signal V of chip internal generation
DLink to each other; Its drain electrode links to each other with the supply voltage Vin of chip input; Its source electrode links to each other with the drain electrode of the 6th NMOS pipe M6;
Described the 6th NMOS pipe M6, its grid is as the second input end B of sample circuit (3), and the bias voltage VBIAS that produces with chip internal links to each other; Its source electrode is connected to ground;
Described feedback resistance R1 is connected across between the source electrode of the supply voltage Vin of chip input and the 3rd PMOS sampling pipe M3, consists of band source negative feedback circuit, guarantees that sample rate current can be not excessive;
Described the 3rd PMOS sampling pipe M3, its grid links to each other with the source electrode of the 2nd NMOS pipe M2; Its drain electrode is connected to the input end E of dynamic current source circuit (22) as the output terminal C of sample circuit (3).
4. linear voltage regulator driving circuit according to claim 1 is characterized in that source follower circuit (1), and M1 consists of by NMOS pipe; The grid of the one NMOS pipe M1 is as input end J, with the voltage signal V of chip internal generation
DLink to each other, its drain electrode links to each other with the supply voltage Vin of chip input, and its source electrode is as output terminal I, and output voltage drives signal P
G
5. according to claim 3 or 4 described linear voltage regulator driving circuits, it is characterized in that the 2nd NMOS pipe M2 in the sample circuit (3) is identical with the NMOS pipe M1 type that consists of source follower circuit (1), breadth length ratio is proportional, and grid voltage is all the voltage signal V of chip internal generation
D, to guarantee the source voltage P of the 2nd NMOS pipe M2
GXDrain voltage P with NMOS pipe M1
GChange consistent.
6. linear voltage regulator driving circuit according to claim 3 is characterized in that the 3rd PMOS sampling pipe M3 in the sample circuit (3) and the PMOS power tube P of its place chip internal
HType is identical, breadth length ratio is proportional, changes consistent with the sample rate current signal Ic that guarantees the 3rd PMOS sampling pipe M3 with the load current Iload of chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104704531A CN102981543A (en) | 2012-11-19 | 2012-11-19 | Drive circuit of ultralow-power-consumption linear voltage stabilizer |
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|---|---|---|---|
| CN2012104704531A CN102981543A (en) | 2012-11-19 | 2012-11-19 | Drive circuit of ultralow-power-consumption linear voltage stabilizer |
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| CN104317345A (en) * | 2014-10-28 | 2015-01-28 | 长沙景嘉微电子股份有限公司 | Low dropout regulator on basis of active feedback network |
| CN106896857A (en) * | 2017-03-16 | 2017-06-27 | 西安电子科技大学 | It is applied to the load transient response enhancing circuit of linear voltage regulator |
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Application publication date: 20130320 |