CN115268550B - Quick-response low-dropout linear voltage stabilizing circuit - Google Patents
Quick-response low-dropout linear voltage stabilizing circuit Download PDFInfo
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- CN115268550B CN115268550B CN202211205154.5A CN202211205154A CN115268550B CN 115268550 B CN115268550 B CN 115268550B CN 202211205154 A CN202211205154 A CN 202211205154A CN 115268550 B CN115268550 B CN 115268550B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a low dropout linear voltage stabilizing circuit with quick response, and belongs to the field of power supply circuits. The quick-response low-dropout linear voltage stabilizing circuit comprises an operational amplifier part, a super source follower part, a load current detection part and a voltage-controlled resistor part. Due to the introduction of the super source follower, the output driving capability of the circuit is greatly enhanced; the load current detection section may convert a change in the load current into a control amount to control the circuit. Converting the current change into a control voltage to control the voltage-controlled resistor; there are many ways to implement a voltage controlled resistor. The invention realizes the LDO design with low output ripple and high response speed, can quickly pull the output voltage back to the required value under the condition of wide-range load current change, and has small ripple.
Description
Technical Field
The invention relates to the technical field of power circuits, in particular to a low dropout linear voltage stabilizing circuit with quick response.
Background
The function of LDO (Low Dropout regulator) is to regulate the power supply voltage
Conversion to a lower reference voltage
And is used by the subsequent circuit. The key indicator of LDO is pressure difference
Noise, power supply voltage rejection ratio PSRR, quiescent current
. A good LDO design should meet the characteristics of low ripple, fast response speed, high power supply voltage rejection ratio, etc.
The conventional LDO design is shown in FIG. 1, and the operational amplifier of the circuit is connected in a unity gain negative feedback mode, so that the output voltage V is output out And an input reference voltage V ref Are equal. When the output voltage V is out When the change-over time is changed, the change-over time,the operational amplifier outputs a voltage V out And an input reference voltage V ref To change the grid voltage of the M1 tube, control the current of the M1 tube, further control the current flowing to the load, and output the voltage V out Pulling back to normal.
The LDO is usually used for supplying power to an on-chip low-voltage module, and needs a larger on-chip filter capacitor C L To stabilize the output voltage and make it meet certain ripple requirements. However, if the transient current of the small-scale digital circuit is large and the load with small average current is supplied, for example, the current jumps from 1mA to about 500mA within 1ns, the operational amplifier bandwidth is usually narrower and the loop cannot respond quickly, and the output impedance of the LDO is only about 1/g m1 For such large current variations, the output ripple jumps to several hundred millivolts, thus requiring a very large filter capacitor C L （>10 nF) to stabilize the output voltage, which is very large in area for the on-chip capacitance.
The loop of the circuit of fig. 1 has been marked with two poles, one at the gate of the M1 transistor, and an output voltage
Here, the two pole sizes are:
wherein
The resistance value is large, so that the dominant pole of the loop is P1, and the secondary pole of the loop is P2. Low ripple performance requirement load capacitance C L Very large, P2 will be small, and to meet the stability requirement, the dominant pole P1 needs to be reduced, and the required compensation capacitance
The size is large, a large circuit area is required, the bandwidth is narrow, and the response speed is slow.
Disclosure of Invention
The present invention is directed to a low dropout linear voltage regulator circuit with fast response, so as to solve the problems of the background art.
In order to solve the technical problem, the invention provides a low dropout linear voltage regulator circuit with quick response, which comprises an operational amplifier A1, an NMOS tube M4, an NMOS tube M5, a PMOS tube M2, a PMOS tube M3, a PMOS tube M6, a current source I1, a current source I2, a voltage-controlled resistor Rx, a load resistor RL, a capacitor Cx, a filter capacitor CL and a compensation capacitor Cc; the gate end of the NMOS tube M1 is connected with the output end of the operational amplifier A1, the source end is connected with the input end of a current source I2, and the drain end is connected with the output end of the current source I1; the grid end of the PMOS tube M2 is connected with the output end of a current source I1, the source end is connected with a power voltage VDD, and the drain end is connected with the source end of an NMOS tube M1; the grid end of the PMOS tube M3 is connected with the output end of a current source I1, the source end is connected with a power voltage VDD, and the drain end is connected with the drain end of an NMOS tube M4; the source end of the NMOS tube M4 is grounded, and the drain end and the gate end are both connected with the gate end of the NMOS tube M5; the source end of the NMOS tube M5 is grounded, and the drain end of the NMOS tube M6 is connected with the drain end of the PMOS tube; the source end of the PMOS tube M6 is connected with a power voltage VDD, and the drain end and the gate end are both connected with the control end of a voltage-controlled resistor Rx; the head end of the voltage-controlled resistor Rx is connected with a power supply voltage VDD, and the tail end of the voltage-controlled resistor Rx is connected with the grid end of the PMOS tube M2;
the positive input end of the operational amplifier A1 is connected with a reference voltage Vref, and the negative input end is connected with the source end of an NMOS tube M1; one end of the load resistor RL is connected with the source end of the NMOS tube M1, and the other end of the load resistor RL is grounded; one end of the filter capacitor CL is connected with the source end of the NMOS tube M1, and the other end of the filter capacitor CL is grounded.
Optionally, one end of the capacitor Cx is connected to the gate end of the PMOS transistor M2, and the other end is grounded.
Optionally, one end of the compensation capacitor Cc is connected to the gate end of the NMOS transistor M1, and the other end is grounded.
The low dropout linear voltage stabilizing circuit with quick response provided by the invention has the following beneficial effects:
(1) The LDO design with low output ripple and high response speed is realized, the output voltage can be quickly pulled back to the required value under the condition of wide-range load current change, and the ripple is very small;
(2) The area required by the circuit is small, and compared with the common LDO design, the area of the filter capacitor is greatly reduced;
(3) The structure is exquisite, and to LDO circuit, make innovative improvement, the new detection circuitry that adds has improved circuit stability through the extreme point of control loop.
Drawings
FIG. 1 is a schematic diagram of a conventional LDO circuit;
FIG. 2 is a schematic diagram of a low dropout linear voltage regulator circuit with fast response according to the present invention;
FIG. 3 is a schematic diagram of a Loop B structure;
fig. 4 is a schematic diagram of a Loop B structure with a current detection module and a voltage-controlled resistor Rx.
Detailed Description
The present invention provides a fast response low dropout linear voltage regulator circuit, which is described in further detail below with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a quick-response low-dropout linear voltage stabilizing circuit, the architecture of which is shown in figure 2 and comprises an operational amplifier, a Super Source Follower (SSF), a current detection module and a voltage-controlled resistor structure.
The first part is an operational amplifier part connected in a unit gain negative feedback mode to make the output voltage V out And an input reference voltage V ref The operational amplifier A1 provides high gain required by the circuit, the NMOS tube M1 plays the role of a source follower, and the grid-source voltage difference of the NMOS tube M1 is V GS Compensating capacitor C C The loop stability is improved.
The second part is super source follower part, and power tube PMOS pipe M2 has been increased to ordinary LDO structure relatively, and when the required electric current grow of load, PMOS pipe M2's electric current can increase, provides high driving force. In FIG. 2, ro1 and ro2 denote equivalent resistances viewed from the drains of the NMOS transistor M1 and the PMOS transistor M2, respectively, and are shown inAs a representative, no additional parallel resistor is present. Meanwhile, due to the introduction of the SSF, the changed load current can completely flow through the PMOS tube M2, and the current of the NMOS tube M1 is almost unchanged, so that the static working point of the output position of the operational amplifier cannot change along with the load current. Moreover, due to the output impedance of the SSF
Is one order of magnitude smaller (R) than a common Source Follower (SF) out =1/(g m1 ×g m2 ×r O1 ) Therefore, the loop bandwidth is usually much wider than the normal LDO loop bandwidth, and therefore the response speed is very fast for fast load current changes.
The third part is a current detection module and a voltage-controlled resistor structure, and a voltage-controlled resistor R is introduced X . The current detection module converts the load current into a control voltage by detecting the current change of the PMOS tube M2, so as to control the resistance value of the resistor, keep the pole at the position relatively unchanged, and improve the stability of a loop under different load currents.
The main loops that the whole circuit contains are marked in the figure, loop a and Loop B respectively.
When the load resistance R L At infinity, the current flowing through the PMOS transistor M2 is I M2_0 Current source I 1 A current source I for providing a static current for normal operation of the NMOS transistor M1 in a saturation region 2 =I 1 +I M2_0 . When the load resistance R L When the current is gradually reduced, the load current is V out /R L And gradually increases, and all the current flows through the PMOS pipe M2. If the load resistance R L The change is large, the current flowing through the PMOS transistor M2 also changes greatly, so the grid voltage V of the PMOS transistor M2 X Will change with the current of PMOS pipe M2, the larger the current of PMOS pipe M2 is, V X The smaller. The current flowing through the NMOS transistor M1 is unchanged and is still I 1 Therefore, the gate voltage V of the NMOS transistor M1 G The gain of the operational amplifier can be kept unchanged, and the operational amplifier can be ensured to maintain high gain. V X Will follow the load current V out /R L Becomes larger and lower, so long as V is guaranteed X -V out >V dsat1 ，V dsat1 The LDO can ensure higher output voltage precision and power supply rejection ratio for the over-drive voltage when the NMOS tube M1 is conducted. Due to V X =V DD -V GS2 （V GS2 The gate-source voltage of the PMOS transistor M2), V can be derived DD >V out +V th_M2 +V dsat1 +V dsat2 （V th_M2 Threshold voltage, V, for conduction of PMOS transistor M2 dsat1 And V dsat2 The overdrive voltages when M1 and M2 are turned on, respectively), so the LDO structure is more suitable for V DD Higher and V out In lower occasions.
For the Loop A Loop, the output voltage Vout is connected to the inverting input terminal of the operational amplifier and is of a unity gain negative feedback structure, V out =V ref . The loop has two poles due to the output resistance R of the operational amplifier out_AMP Is generally relatively large, so the dominant pole
At the gate of the NMOS transistor M1, the size is:
the secondary pole
At V out The size is:
when the next extreme is minimum, R L Infinite, this time the secondary pole:
since the output resistance of SSF is small, R out =1/(g m1 ×g m2 ×r O1 ) Wherein gm1 is transconductance of the NMOS transistor M1, gm2 is transconductance of the PMOS transistor M2, ro1 is an equivalent resistance seen from the drain terminal D of the NMOS transistor M1, and is a common general definition in the semiconductor field; p 2_loopB Will be larger and thus smaller compensation capacitor C C The stability requirement of the major and minor poles can be met.
When there is no current detection module and no voltage controlled resistance module, fig. 3 shows a schematic diagram of Loop B. For the Loop B Loop, two poles are also included, the first pole
At the gate of the PMOS transistor M2, i.e. the X position in the figure, the size is:
second pole
At V out The size is:
wherein R is y Is from V out The resistance seen into the source of the NMOS transistor M1 is:
wherein R is X Is a current source I 1 Has a large value of R y Very large, R L And R y Parallel value of (2) is about R L 。
Introduction of SSF so that V out The pole P is increased, which is favorable for quick response and outputs 2_loopB As a major pole, to a minor pole P 1_loopB The analysis is carried out, in order to meet the stability requirements, it is necessary to satisfy:
wherein GBW (Gain-bandwidth product) refers to the Gain-bandwidth product of the operational amplifier, specifically to the value obtained by the low-frequency Gain x-3 dB Gain bandwidth of the operational amplifier, i.e., -3dB bandwidth (main pole) behind the equal sign) X gain A DC ；A DC Is the DC gain of Loop B, and has a value of
And finishing to obtain:
through principle analysis, the load current caused by the load resistance change can be changed, and the load current can completely flow through the PMOS transistor M2, so that the transconductance g of the PMOS transistor M2 can be caused m2 Changing the source-drain current I flowing through the PMOS transistor M2 M2 When becoming large, g m2 Will also become larger, possibly let C be L And C X The ratio of (a) does not meet the stability requirement.
To solve this problem, as shown in fig. 4, a voltage-controlled resistor R is added to the gate of the PMOS transistor M2 X And a current detection module, wherein the left side of the current detection module is composed of PMOS tubes M3 and M6 and NMOS tubes M4 and M5, and generates a voltage V inversely proportional to the load current control For controlling Rx, rx and V control Is proportional, so when the load current is large, R is X Is small; when the load current is small, R X Is very large. At the same time, since R X Has a large resistance value, so that the current flows through R X The current of the NMOS transistor M1 is not greatly affected, and the current of the NMOS transistor M1 is still considered to be unchanged.
Introducing a resistance R X Then, the pole expression at the gate of PMOS transistor M2 becomes:
the poles also satisfy:
tab-in A DC It is possible to obtain:
finishing is as follows:
it can be seen that the resistor R is added X Then, it is equivalent to the pair g m2 The correction is made such that when the load current is small, R X Very large, the expression can be ignored; when the load current increases, the current flowing through the PMOS transistor M2 also increases, so g m2 Increase while R is X Will decrease and so the right side of the inequality remains almost unchanged. As long as 2 g is guaranteed m1 g m2 ·r O1 /（1+r O1 /R X ) The stability of Loop B can be ensured by keeping relatively constant in the load current change range, so that a compensation mode following the load current change is realized.
The invention provides a novel circuit structure, and realizes the design of a low-dropout linear voltage stabilizing circuit with low ripple and quick response. The circuit comprises an operational amplifier part, a super source follower part, a load current detection part and a voltage-controlled resistance part. Due to the introduction of the super source follower, the output driving capability of the circuit is greatly enhanced; the load current detection section may convert a change in the load current into a control amount to control the circuit. In this example, the current change is converted into a control voltage to control the voltage-controlled resistor; there are many ways to implement the voltage-controlled resistor, in this case the resistor Rx is used as a reference, and the claims are not limited to the voltage-controlled variable resistor Rx, and it is within the scope of the patent protection to implement the similar function.
In any case, the scope of the present invention is defined by the appended claims, and all changes and modifications that can be made by one of ordinary skill in the art based on the disclosure above are intended to be embraced therein.
Claims (3)
1. A quick-response low-dropout linear voltage stabilizing circuit is characterized by comprising an operational amplifier A1, an NMOS tube M4, an NMOS tube M5, a PMOS tube M2, a PMOS tube M3, a PMOS tube M6, a current source I1, a current source I2, a voltage-controlled resistor Rx, a load resistor RL, a capacitor Cx, a filter capacitor CL and a compensation capacitor Cc;
the gate end of the NMOS tube M1 is connected with the output end of the operational amplifier A1, the source end is connected with the input end of a current source I2, and the drain end is connected with the output end of the current source I1; the grid end of the PMOS tube M2 is connected with the output end of a current source I1, the source end is connected with a power voltage VDD, and the drain end is connected with the source end of an NMOS tube M1; the grid end of the PMOS tube M3 is connected with the output end of a current source I1, the source end is connected with a power voltage VDD, and the drain end is connected with the drain end of an NMOS tube M4; the source end of the NMOS tube M4 is grounded, and the drain end and the gate end are both connected with the gate end of the NMOS tube M5; the source end of the NMOS tube M5 is grounded, and the drain end of the NMOS tube M6 is connected with the drain end of the PMOS tube; the source end of the PMOS tube M6 is connected with a power voltage VDD, and the drain end and the gate end are both connected with the control end of a voltage-controlled resistor Rx; the head end of the voltage-controlled resistor Rx is connected with a power supply voltage VDD, and the tail end of the voltage-controlled resistor Rx is connected with the grid end of the PMOS tube M2;
the positive input end of the operational amplifier A1 is connected with a reference voltage Vref, and the negative input end is connected with the source end of an NMOS tube M1; one end of the load resistor RL is connected with the source end of the NMOS tube M1, and the other end of the load resistor RL is grounded; one end of the filter capacitor CL is connected with the source end of the NMOS tube M1, and the other end of the filter capacitor CL is grounded.
2. The fast response low dropout linear voltage regulator circuit of claim 1, wherein a terminal of said capacitor Cx is connected to the gate terminal of PMOS transistor M2, and the other terminal is grounded.
3. The fast response, low dropout linear voltage regulator circuit according to claim 1, wherein one terminal of said compensation capacitor Cc is connected to the gate terminal of the NMOS transistor M1, and the other terminal is connected to ground.
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| GB2557223A (en) * | 2016-11-30 | 2018-06-20 | Nordic Semiconductor Asa | Voltage regulator |
| US10775819B2 (en) * | 2019-01-16 | 2020-09-15 | Avago Technologies International Sales Pte. Limited | Multi-loop voltage regulator with load tracking compensation |
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| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
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| TW201245921A (en) * | 2011-05-11 | 2012-11-16 | Advanced Analog Technology Inc | Low-dropout regulator and pole compensation method for low-dropout regulator |
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