CN109101067B

CN109101067B - Low dropout linear regulator with dual power rails

Info

Publication number: CN109101067B
Application number: CN201810906125.9A
Authority: CN
Inventors: 明鑫; 胡晓冬; 辛杨立; 罗淞民; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2018-08-10
Filing date: 2018-08-10
Publication date: 2019-12-10
Anticipated expiration: 2038-08-10
Also published as: CN109101067A

Abstract

A low dropout linear regulator with dual power rails belongs to the technical field of power management. The low dropout linear regulator comprises an error amplification module, a first feedback resistor, a second feedback resistor and a power module, wherein the first feedback resistor and the second feedback resistor are connected in series and in parallel between the output end of the low dropout linear regulator and the ground, and the series point of the first feedback resistor and the second feedback resistor outputs feedback voltage; the power module comprises a first power tube and a second power tube which are different in power supply rail; the error amplification module comprises a first-stage differential input unit and a second-stage amplification unit, the second-stage amplification unit comprises a first branch and a second branch, a first input end of the first-stage differential input unit is connected with a reference voltage, and a second input end of the first-stage differential input unit is connected with a feedback voltage; and under the control of an enable signal, the first branch circuit or the second branch circuit controls the first power tube or the second power tube to generate an output signal of the low-dropout linear regulator according to the output signal of the first-stage differential input unit. The invention improves the energy conversion efficiency and the circuit reliability of the LDO.

Description

Low dropout linear regulator with dual power rails

Technical Field

The invention belongs to the technical field of power management, and particularly relates to a design of a Low Dropout Regulator (LDO).

Background

the BUCK DC-DC converter is also called a BUCK converter, and can convert a higher power supply voltage into an output lower than the power supply voltage. The BUCK converter has a great characteristic of high energy conversion efficiency, which can reach more than 90% in general. The circuit schematic diagram of the conventional synchronous rectification BUCK chip is shown in fig. 1, where VIN represents the input voltage of the chip, and VOUT represents the output voltage of the chip, and its main components include a loop control circuit, a driving circuit, an upper power tube S1, a lower power tube S2, an energy storage inductor L, a filter capacitor COUT, a load resistor RL, and voltage dividing resistors R and R'. Two input ends of the loop control circuit are respectively a feedback voltage Vf and a reference voltage VREF, the control circuit outputs a control signal by comparing the voltage difference between the two input ends, and the control signal outputs driving signals of an upper power tube S1 and a lower power tube S2 through the driving circuit to control the two power tubes to be switched on and switched off, so that the output voltage VOUT is stabilized.

_LOAD _LOAD _ESRThe LDO is generally used as a circuit submodule applied to a BUCK chip and mainly used for supplying power to a loop control circuit, as shown in FIG. 1, the VCC voltage of the loop control circuit is the output voltage inside the BUCK chip.

the energy conversion efficiency η of the LDO can be calculated by the following equation:

the output energy P _OUT is the product of the LDO output voltage VCC and the load current I _LOAD, and the input energy P _IN is the product of the LDO input voltage VIN and the input current I _IN, wherein the input current I _IN includes the load current I _LOAD and the quiescent current Iq of the error amplifier, the bandgap reference, the feedback network, etc. in the LDO, as follows:

I_IN＝I_LOAD+I_q

Thus, LDO energy conversion efficiency can be expressed as:

Here, the voltage conversion efficiency η _V and the current conversion efficiency η _I are respectively expressed as follows:

Therefore, the energy conversion efficiency of the LDO is closely related to the difference of the input and output voltages and the system quiescent current. Under heavy load conditions, the system quiescent current is often negligible, and thus the energy conversion efficiency is only related to the input-output voltage difference. However, in many applications, the input voltage of the BUCK chip is high and the supply voltage of the loop control circuit is low, that is, the difference between the input voltage and the output voltage of the LDO inside the chip is large, which causes the energy loss of the whole BUCK chip.

disclosure of Invention

Aiming at the problem of energy loss of the traditional LDO, the invention provides the low-dropout linear regulator with the double power rails, which can be applied to a BUCK converter chip, solves the problem of low energy conversion efficiency of the LDO in the BUCK converter chip, and improves the power supply efficiency of the BUCK converter chip.

The technical scheme of the invention is as follows:

a dual-power-rail low dropout linear regulator comprises an error amplification module, a first feedback resistor RF1, a second feedback resistor RF2 and a power module, wherein the first feedback resistor RF1 and the second feedback resistor RF2 are connected in series and in parallel between the output end of the low dropout linear regulator and the ground, and the series point of the first feedback resistor RF1 and the second feedback resistor RF2 outputs a feedback voltage VFB;

The power module comprises a first power tube and a second power tube which are different in power supply rail;

The error amplification module comprises a first-stage differential input unit and a second-stage amplification unit, wherein a first input end of the first-stage differential input unit is connected with a reference voltage VREF, a second input end of the first-stage differential input unit is connected with the feedback voltage VFB, and the second-stage amplification unit comprises a first branch circuit and a second branch circuit;

And under the control of an enable signal, the first branch circuit controls the first power tube to generate an output signal of the low dropout regulator according to the output signal of the first-stage differential input unit, or the second branch circuit controls the second power tube to generate an output signal of the low dropout regulator according to the output signal of the first-stage differential input unit.

Specifically, the first stage differential input unit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first capacitor C01,

the gate of the first PMOS transistor MP1 is used as the first input terminal of the first stage differential input unit, the source thereof is connected to the source of the second PMOS transistor MP2 and connected to the bias current source I _BIAS1, and the drain thereof is connected to the gate and the drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN 2;

The grid electrode of a second PMOS pipe MP2 is used as a second input end of the first-stage differential input unit, and the drain electrode of the second PMOS pipe MP2 is connected with the drain electrode of a second NMOS pipe MN2 and generates an output signal of the first-stage differential input unit;

The first capacitor C01 is connected between the drain of the second PMOS transistor MP2 and ground;

The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded.

Specifically, the first power transistor is a seventh PMOS transistor MP, a gate of the seventh PMOS transistor MP is used as a control end of the first power transistor, a source of the seventh PMOS transistor MP is connected to a first power supply rail, and a drain of the seventh PMOS transistor MP outputs an output signal of the low dropout linear regulator.

specifically, the first branch circuit comprises a second resistor R2, a fourth resistor R4, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6,

The grid electrode of a fifth NMOS transistor MN5 is used as the input end of the first branch circuit and is connected with the output signal of the first-stage differential input unit, the drain electrode of the fifth NMOS transistor MN5 is connected with the source electrode of a fourth NMOS transistor MN4, and the source electrode of the fifth NMOS transistor MN 3578 is connected with the drain electrode of a sixth NMOS transistor MN6 after passing through a second resistor R2;

the gate of the sixth NMOS transistor MN6 is connected to the first enable signal EN1, and the source thereof is grounded;

The gate of the fourth NMOS transistor MN4 is connected to the power supply voltage VDD, and the drain thereof is connected to the gate and the drain of the fourth PMOS transistor MP4 and the gate of the seventh PMOS transistor MP, and is connected to the source of the fourth PMOS transistor MP4 and the first power rail through the fourth resistor R4.

Specifically, the low dropout regulator further comprises a first resistor R1, a third NMOS transistor MN3 and a third PMOS transistor MP3,

the grid electrode of the third NMOS transistor MN3 is connected with the source electrode of the third PMOS transistor MP3 and is grounded after passing through the first resistor R1, the drain electrode of the third NMOS transistor MN3 is connected with the input end of the first branch circuit, and the source electrode of the third NMOS transistor MN3 is grounded;

the gate of the third PMOS transistor MP3 is connected to the control terminal of the first power transistor, and the source thereof is connected to the first power rail.

Specifically, the second power transistor is a second NPN-type triode QN, a base stage of the second NPN-type triode QN serves as a control end of the second power transistor, a collector of the second NPN-type triode QN is connected to a second power rail, and an emitter of the second NPN-type triode QN outputs an output signal of the low dropout regulator.

specifically, the second branch comprises a third resistor R3, a fifth resistor R5, a first NPN type triode QN1, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9,

the gate of the eighth NMOS transistor MN8 is used as the input end of the second branch circuit and is connected to the output signal of the first-stage differential input unit, the source thereof is connected to the drain of the ninth NMOS transistor MN9 through the third resistor R3, and the drain thereof is connected to the source of the seventh NMOS transistor MN 7;

The grid electrode of the seventh NMOS transistor MN7 is connected with a power supply voltage VDD, and the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and the drain electrode of the fifth PMOS transistor MP5 and the grid electrode of the sixth PMOS transistor MP6 and is connected with the source electrode of the sixth PMOS transistor MP6 through a fifth resistor R5;

The sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected with the first power supply rail;

The base and the collector of the first NPN transistor QN1 are interconnected and connected to the drain of the sixth PMOS transistor MP6 and the base of the second NPN transistor QN, and the emitter thereof is connected to the emitter of the second NPN transistor QN.

Specifically, the low dropout regulator further includes a first PNP transistor QP1, a base of the first PNP transistor QP1 is connected to a collector of the second NPN transistor QN, a collector of the first PNP transistor QP1 is connected to a source of the eighth NMOS transistor MN8, and an emitter of the first PNP transistor QP1 is connected to a base of the second NPN transistor QN.

The invention has the beneficial effects that: according to the invention, the first branch or the second branch is controlled to be conducted according to the enabling signal, so that power tubes of different power rails are connected into the LDO, the energy conversion efficiency of the LDO is improved, and the power supply efficiency of the BUCK converter is further improved; meanwhile, the overcurrent limiting structure can effectively improve the reliability of the whole circuit.

drawings

Fig. 1 is a circuit schematic diagram of a conventional synchronous rectification BUCK converter chip.

FIG. 2 is a schematic diagram of a conventional LDO circuit for an off-chip capacitor.

fig. 3 is a schematic circuit diagram of a dual-rail low dropout linear regulator according to the present invention.

fig. 4 is a circuit diagram of a dual-rail low dropout linear regulator according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a small-signal equivalent model of a dual-power-rail low dropout linear regulator according to the present invention.

FIG. 6 is a circuit diagram of a voltage comparator for generating an enable signal to determine a power rail in the present invention.

Detailed Description

The invention is further illustrated with reference to the figures and the specific examples.

_BIAS1The invention provides a dual-power-rail low-dropout linear regulator, which comprises an error amplification module, a first feedback resistor RF1, a second feedback resistor RF2 and a power module, wherein the power module comprises a first power tube and a second power tube of different power rails, the first feedback resistor RF1 and the second feedback resistor RF2 are connected in series and in parallel between the output end of the low-dropout linear regulator and the ground, and output a feedback voltage VFB at the series point, the error amplification module comprises a first-stage differential input unit and a second-stage amplification unit, the first input end of the first-stage differential input unit is connected with a reference voltage VREF, the second input end of the first-stage differential input unit is connected with the feedback voltage VFB, as shown in FIG. 4, a circuit implementation form of the first-stage differential input unit is provided and comprises a first-stage PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2 and a first capacitor C48, the grid of the first PMOS tube 39 1 is used as the first input end of the first-stage input unit, the source of the first-stage PMOS tube MP 6329 is connected with a second NMOS transistor MN 3527, the drain electrode of the second-NMOS transistor MN 6329, the second-stage differential input unit is connected with a drain electrode of a second-NMOS transistor MN transistor, and a drain electrode transistor NMOS, and a drain electrode 3527, and a drain electrode of a transistor NMOS transistor:

A_V＝g_m,MP1(r_ds,MP2||r_ds,MN2)

Wherein r _ds,MN2 and r _ds,MP2 are drain-source resistances of the second NMOS transistor MN2 and the second PMOS transistor MP2, respectively, and g _m,MP1 represents a transconductance of the first PMOS transistor MP 1.

The first capacitor C01 is used for adjusting the pole position of the first stage differential input unit of the error amplification module and maintaining the stability of the loop.

The second-stage amplification unit comprises a first branch and a second branch which are respectively used for controlling the first power tube and the second power tube, in actual work, the first branch and the second branch in the second-stage amplification unit share the first-stage differential input unit, the first branch or the second branch is selected to be communicated with the first-stage differential input unit through an enabling signal to form an error amplifier, and a corresponding control signal is generated to control the first power tube or the second power tube to generate an output signal VCC of the low dropout linear regulator.

Since the first power tube and the second power tube have different power rails, when the invention is applied to the BUCK converter, the input voltage VIN of the BUCK converter can be used as the power rail of the first power tube, and the output voltage VOUT of the BUCK converter can be used as the power rail of the second power tube. The output voltage VOUT of the BUCK converter is smaller than the input voltage VIN of the BUCK converter, so when the second power tube with the power supply rail being the output voltage VOUT of the BUCK converter is used for generating the output signal VCC of the low dropout linear regulator, the energy conversion efficiency of the low dropout linear regulator LDO is significantly improved compared to when the first power tube with the power supply rail being the input voltage VIN of the BUCK converter is used for generating the output signal VCC of the low dropout linear regulator. Based on the voltage threshold, when the output voltage VOUT of the BUCK converter is properly higher than the target value VCC of the output voltage of the LDO, the input power supply rail of the LDO is switched from VIN to VOUT, and therefore the power supply efficiency can be effectively improved. As shown in fig. 3, the first enable signal EN1 and the second enable signal EN2 are used as enable signals for controlling the switching of the power supply rail, and are respectively used for controlling the first branch circuit and the second branch circuit, so as to control the first power tube with the input voltage VIN of the BUCK converter as the power supply rail or the second power tube with the output voltage VOUT of the BUCK converter as the power supply rail to operate.

The first power tube and the second power tube may use the same type of power tube, or different types of power tubes, and the structure of the first branch or the second branch in the corresponding second-stage amplification unit is selected according to the type of the first power tube and the second power tube, in this embodiment, the working process and the working principle of the PMOS tube as the power tube are described in detail by taking the PMOS tube as the first power tube as an example, as shown in fig. 4, the first power tube is a seventh PMOS tube MP, a gate of the seventh PMOS tube MP is used as a control end of the first power tube, a source thereof is connected to the input voltage VIN of the BUCK converter, and a drain thereof outputs an output signal of the low dropout linear regulator.

as shown in fig. 4, the structure of the PMOS transistor serving as the power transistor and the corresponding first branch thereof includes a second resistor R2, a fourth resistor R4, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6, a gate of the fifth NMOS transistor MN5 serving as an input end of the first branch is connected to an output signal of the first-stage differential input unit, a drain thereof is connected to a source of the fourth NMOS transistor MN4, and a source thereof is connected to a drain of the sixth NMOS transistor MN6 through the second resistor R2; the gate of the sixth NMOS transistor MN6 is connected to the first enable signal EN1, and the source thereof is grounded; the gate of the fourth NMOS transistor MN4 is connected to the power supply voltage VDD, and the drain thereof is connected to the gate and the drain of the fourth PMOS transistor MP4 and the gate of the seventh PMOS transistor MP, and is connected to the source of the fourth PMOS transistor MP4 and the input voltage VIN of the BUCK converter through the fourth resistor R4.

in consideration of the fact that the input voltage VIN of the BUCK converter is high in most cases, it is preferable to use voltage-withstanding MOS transistors for the seventh PMOS transistor MP, the fourth PMOS transistor MP4, and the fourth NMOS transistor MN 4. The second resistor R2 acts as a source degeneration resistor and may act to adjust the loop gain. The fourth resistor R4 serves as an initialization resistor to provide a bleed path for the charge accumulated at the gate of the seventh PMOS transistor MP when the input voltage VIN of the BUCK converter stops supplying power. Meanwhile, the seventh PMOS transistor MP and the fourth PMOS transistor MP4 are connected in a mirror image manner, which is beneficial to improving the power supply rejection ratio of the LDO.

since a large current flows through the seventh PMOS transistor MP during the process of establishing the output signal VCC of the low dropout regulator, in consideration of reliability, an over-current limit structure may be added to the branch corresponding to the seventh PMOS transistor MP that takes the input voltage VIN of the BUCK converter as the power supply rail in this embodiment. As shown in fig. 4, the over-current limiting structure includes a first resistor R1, a third NMOS transistor MN3, and a third PMOS transistor MP3, wherein a gate of the third NMOS transistor MN3 is connected to a source of the third PMOS transistor MP3 and grounded through a first resistor R1, a drain of the third NMOS transistor MN3 is connected to an input terminal of the first branch, and a source of the third NMOS transistor MN3 is grounded; the gate of the third PMOS transistor MP3 is connected to the control terminal of the first power transistor, and the source thereof is connected to the input voltage VIN of the BUCK converter.

Considering that the input voltage VIN of the BUCK converter is generally high, the third PMOS transistor MP3 is preferably a voltage-withstanding transistor. The operating principle of the over-current limit structure is as follows: the current flowing through the seventh PMOS transistor MP flows through the third PMOS transistor MP3 in proportion, and generates a voltage drop V1 across the first resistor R1. Under the normal condition, V1 is lower than the threshold voltage of the third NMOS transistor MN3, and the third NMOS transistor MN3 is in a cut-off state; when overcurrent occurs, the voltage V1 is higher than the threshold voltage of the third NMOS transistor MN3, so that the third NMOS transistor MN3 is turned on, thereby reducing the gate voltage of the fifth NMOS transistor MN5, and finally, the current flowing through the seventh PMOS transistor MP is maintained at a constant value through the regulation of the feedback loop of the LDO, where the constant value is the overcurrent limit of the LDO. The overcurrent limit can be determined through two aspects, namely the overcurrent capacity of the transistor and the power-on time of an output signal VCC of the low dropout linear regulator. The former can be determined according to the process used and the latter can be determined according to the following formula:

du/dt represents the voltage change rate of the output signal VCC of the low dropout linear regulator along with time when the output signal VCC is electrified, the value determines the electrifying time of the output signal VCC of the low dropout linear regulator, i represents the value of the overcurrent limit, and C _LOAD is the capacitance of the output end.

In this embodiment, the second power transistor takes an NPN-type transistor as an example to explain the working process and the working principle of the NPN-type transistor as the power transistor in detail, as shown in fig. 4, the second power transistor is a second NPN-type transistor QN, a base stage of the second NPN-type transistor QN is used as a control end of the second power transistor, a collector of the second NPN-type transistor QN is connected to the output voltage VOUT of the BUCK converter, and an emitter of the second NPN-type transistor QN outputs an output signal of the low dropout regulator.

as shown in fig. 4, the NPN-type triode serving as the second branch corresponding to the power transistor includes a third resistor R3, a fifth resistor R5, a first NPN-type triode QN1, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9, a gate of the eighth NMOS transistor MN8 serving as an input end of the second branch is connected to an output signal of the first-stage differential input unit, a source of the eighth NMOS transistor MN8 is connected to a drain of the ninth NMOS transistor MN9 through a third resistor R3, and a drain of the eighth NMOS transistor MN7 is connected to a source of the seventh NMOS transistor MN 7; the grid electrode of the seventh NMOS transistor MN7 is connected with a power supply voltage VDD, and the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and the drain electrode of the fifth PMOS transistor MP5 and the grid electrode of the sixth PMOS transistor MP6 and is connected with the source electrode of the sixth PMOS transistor MP6 through a fifth resistor R5; the sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the input voltage VIN of the BUCK converter; the base and the collector of the first NPN transistor QN1 are interconnected and connected to the drain of the sixth PMOS transistor MP6 and the base of the second NPN transistor QN, and the emitter thereof is connected to the emitter of the second NPN transistor QN.

unlike the PMOS type selected for the first power transistor with the power rail being the input voltage VIN of the BUCK converter, the second power transistor in this embodiment is of a transistor type, which has an advantage of larger driving capability compared to the MOS transistor. The LDO needs to supply power for a loop control circuit of the BUCK converter chip, namely the load current of the LDO is large, so that the area of the chip can be effectively saved by adopting a triode design. Note that when the transistor operates in a deep saturation region, the response speed of the system may be slowed, and the reliability may be degraded, so that a deep saturation resistant structure may be designed to avoid the problem by using the transistor as a power transistor, as shown in fig. 4, in this embodiment, the deep saturation resistant structure includes a first PNP transistor QP1, a base of the first PNP transistor QP1 is connected to a collector of a second NPN transistor QN, a collector of the first PNP transistor QP1 is connected to a source of an eighth NMOS transistor MN8, and an emitter of the first PNP transistor QP is connected to a base of the second NPN transistor QN. Under normal conditions, the second NPN type triode QN works in an amplification region, the emitter junction voltage Vbe is greater than 0, and the collector junction voltage Vbc is less than 0; the base current Ib is small, the collector current Ic is equal to β Ib, and the emitter current Ie is equal to (1+ β) Ib, where β is the triode current amplification factor. When the base current is large and the current of a collector and an emitter cannot be controlled, the second NPN type triode QN enters a deep saturation state, the voltage Vbe of an emitter junction is larger than 0, the voltage Vbc of a collector junction is larger than 0, after the forward bias of the collector junction reaches the starting voltage of the first PNP type triode QP1, the first PNP type triode QP1 is started, and then a current is extracted from the base of the second NPN type triode QN to reduce Ib, so that the second NPN type triode QN exits from the deep saturation region.

The first enable signal EN1 and the second enable signal EN2 are mutually inverse signals and are used for controlling one of the first branch circuit or the second branch circuit to work, when the first enable signal EN1 is at a high level, the sixth NMOS transistor MN6 is turned on, and the first branch circuit works; when the voltage level is low, the sixth NMOS transistor MN6 is switched off, and the first branch stops working; when the second enable signal EN2 is at a high level, the ninth NMOS transistor MN9 is turned on, and the second branch operates; when the voltage level is low, the ninth NMOS transistor MN9 is turned off, and the second branch stops working.

Fig. 5 shows a small-signal equivalent model of the low dropout regulator LDO in this embodiment, which can be used to analyze the loop stability of the LDO. Because the first branch and the second branch multiplex the first-stage differential input unit of the error amplification module, and the two branches of the second-stage amplification unit of the error amplifier have similar structures, the equivalent models of the two branches are the same, and the first branch is taken as an example for analysis. Because the current limiting loop only works under the abnormal conditions of the power-on process of the LDO or output short circuit and the like, the influence of the current limiting loop is eliminated during small signal analysis. As shown in fig. 5, Gm1, Gm2, and Gmp represent the transconductance of the first stage, the second stage, and the power transistor of the error amplifying module, respectively. As shown in fig. 4, the expression is:

G_m1＝g_m,MP1

where g _m,MN5 is the transconductance of the fifth NMOS transistor MN 5.

R _EA1, R _EA2, R _OUT represent the impedance of the first stage, the second stage, and the output of the error amplifier, respectively, as shown in FIG. 4, the expression is:

R_EA1＝r_ds,MP2||r_ds,MN2

R_OUT＝(R_F1+R_F2)||R_L

Wherein, R _L represents the LDO load impedance, g _m,MP4 is the transconductance of the fourth PMOS transistor MP4, Cg represents the parasitic capacitance at the gate of the power transistor, and β represents the feedback coefficient.

because the parasitic capacitance at the grid of the power tube is small, the grid of the power tube is in a high-frequency area outside the gain bandwidth product GBW, and the stability of the LDO loop cannot be influenced. In the present invention, the secondary point expression is:

in order to ensure the stability of the loop, a single-pole system is achieved within the gain bandwidth product GBW as much as possible, the first-stage output impedance and the corresponding capacitance value of the error amplification module need to be set, and the loop secondary point is pushed to the position outside the GBW or near the GBW.

the voltage comparator circuit for generating a first enable signal EN1 and a second enable signal EN2 to control the selection of power rails in the present invention is shown in FIG. 6, VDD represents a fixed level, and power is supplied to the voltage comparator; VREF represents a reference voltage and has a voltage division relation with the output voltage VOUT of the BUCK converter; VOUT represents the output voltage of the BUCK converter chip; the first enable signal EN1 and the second enable signal EN2 output by the voltage comparator are used for controlling the power rail switching of the LDO. The structure comprises a bias current source IBIAS2, PMOS transistors MP7 and MP8, NMOS transistors MN10, MN11 and MN12, resistors R6, R7 and R8 and an inverter INV. The output voltage VOUT of the BUCK converter is subjected to resistance voltage division and then is input to one end of the comparator to be compared with the reference voltage VREF, when the output voltage VOUT of the BUCK converter is low, the first enabling signal EN1 outputs high level, the second enabling signal EN2 outputs low level, and the LDO is input into a first power tube which adopts an input power VIN of the BUCK converter as a power rail; when the output power VOUT of the BUCK converter is high, the first enable signal EN1 outputs low level, the second enable signal EN2 outputs high level, and the LDO input adopts the output voltage VOUT of the BUCK converter as a second power tube of the power supply rail. The transistor MN10 and the resistor R8 form a hysteresis structure, so that the system instability caused by frequent switching of an enable signal when the output voltage VOUT of the BUCK converter is near a turning point is avoided.

It should be noted that, in the present embodiment, when the low dropout regulator is applied to the BUCK converter, the output voltage of the BUCK converter is lower than the input voltage, and the power conversion efficiency is high, so that the low dropout regulator can be used in both circuits having the two characteristics.

those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A dual-power-rail low dropout linear regulator comprises an error amplification module, a first feedback resistor (RF1), a second feedback resistor (RF2) and a power module, wherein the first feedback resistor (RF1) and the second feedback resistor (RF2) are connected in series and are connected between the output end of the low dropout linear regulator and the ground, and the series point of the first feedback resistor (RF1) and the second feedback resistor (RF2) outputs a feedback Voltage (VFB);

the power module is characterized by comprising a first power tube and a second power tube which are different in power supply rail;

the low-dropout linear regulator is applied to a BUCK converter, and power supply rails of the first power tube and the second power tube are respectively input voltage and output voltage of the BUCK converter;

the first power tube is a PMOS tube or an NPN type triode, and the second power tube is a PMOS tube or an NPN type triode;

The error amplification module comprises a first-stage differential input unit and a second-stage amplification unit, wherein a first input end of the first-stage differential input unit is connected with a reference Voltage (VREF), a second input end of the first-stage differential input unit is connected with the feedback Voltage (VFB), and the second-stage amplification unit comprises a first branch circuit and a second branch circuit;

2. The dual-supply-rail low dropout linear regulator of claim 1, wherein the first stage differential input unit comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a first capacitor (C01),

The grid electrode of a first PMOS tube (MP1) is used as a first input end of the first-stage differential input unit, the source electrode of the first PMOS tube is connected with the source electrode of a second PMOS tube (MP2) and connected with a bias current source (I _BIAS1), and the drain electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of a first NMOS tube (MN1) and the grid electrode of a second NMOS tube (MN 2);

the grid electrode of a second PMOS pipe (MP2) is used as a second input end of the first-stage differential input unit, and the drain electrode of the second PMOS pipe is connected with the drain electrode of a second NMOS pipe (MN2) and generates an output signal of the first-stage differential input unit;

The first capacitor (C01) is connected between the drain of the second PMOS tube (MP2) and the ground;

the sources of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are grounded.

3. The dual-power-rail low dropout regulator of claim 1, wherein the first power transistor is a seventh PMOS transistor (MP), a gate of the seventh PMOS transistor (MP) is used as a control terminal of the first power transistor, a source thereof is connected to the first power rail, and a drain thereof outputs an output signal of the low dropout regulator.

4. The dual-supply-rail low dropout regulator of claim 3, wherein the first branch comprises a second resistor (R2), a fourth resistor (R4), a fourth PMOS transistor (MP4), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5) and a sixth NMOS transistor (MN6),

the grid electrode of a fifth NMOS tube (MN5) is used as the input end of the first branch circuit and is connected with the output signal of the first-stage differential input unit, the drain electrode of the fifth NMOS tube is connected with the source electrode of a fourth NMOS tube (MN4), and the source electrode of the fifth NMOS tube is connected with the drain electrode of a sixth NMOS tube (MN6) after passing through a second resistor (R2);

The gate of the sixth NMOS transistor (MN6) is connected with the first enable signal (EN1), and the source of the sixth NMOS transistor is grounded;

The grid electrode of the fourth NMOS tube (MN4) is connected with a power supply Voltage (VDD), the drain electrode of the fourth NMOS tube is connected with the grid electrode and the drain electrode of the fourth PMOS tube (MP4) and the grid electrode of the seventh PMOS tube (MP), and the fourth NMOS tube is connected with the source electrode of the fourth PMOS tube (MP4) and the first power supply rail through a fourth resistor (R4).

5. The dual-supply-rail low dropout regulator of claim 4, further comprising a first resistor (R1), a third NMOS transistor (MN3), and a third PMOS transistor (MP3),

the grid electrode of the third NMOS tube (MN3) is connected with the source electrode of the third PMOS tube (MP3) and is grounded after passing through the first resistor (R1), the drain electrode of the third NMOS tube is connected with the input end of the first branch circuit, and the source electrode of the third NMOS tube is grounded;

the grid electrode of the third PMOS tube (MP3) is connected with the control end of the first power tube, and the source electrode of the third PMOS tube is connected with the first power supply rail.

6. the dual-power-rail low dropout linear regulator of claim 1, wherein the second power transistor is a second NPN transistor (QN), a base of the second NPN transistor (QN) is used as a control terminal of the second power transistor, a collector of the second NPN transistor is connected to the second power rail, and an emitter of the second NPN transistor outputs the output signal of the low dropout linear regulator.

7. the dual-supply-rail low dropout regulator of claim 6, wherein the second branch comprises a third resistor (R3), a fifth resistor (R5), a first NPN transistor (QN1), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8) and a ninth NMOS transistor (MN9),

the grid electrode of an eighth NMOS tube (MN8) is used as the input end of the second branch circuit and is connected with the output signal of the first-stage differential input unit, the source electrode of the eighth NMOS tube is connected with the drain electrode of a ninth NMOS tube (MN9) after passing through a third resistor (R3), and the drain electrode of the eighth NMOS tube is connected with the source electrode of a seventh NMOS tube (MN 7);

the grid electrode of the seventh NMOS tube (MN7) is connected with a power supply Voltage (VDD), the drain electrode of the seventh NMOS tube is connected with the grid electrode and the drain electrode of the fifth PMOS tube (MP5) and the grid electrode of the sixth PMOS tube (MP6), and the seventh NMOS tube is connected with the source electrode of the sixth PMOS tube (MP6) through a fifth resistor (R5);

The sources of the fifth PMOS tube (MP5) and the sixth PMOS tube (MP6) are connected with the first power supply rail;

The base electrode and the collector electrode of the first NPN type triode (QN1) are interconnected and connected with the drain electrode of the sixth PMOS pipe (MP6) and the base electrode of the second NPN type triode (QN), and the emitter electrode of the first NPN type triode is connected with the emitter electrode of the second NPN type triode (QN).

8. The dual-rail low dropout regulator of claim 7, further comprising a first PNP transistor (QP1), wherein the base of the first PNP transistor (QP1) is connected to the collector of the second NPN transistor (QN), the collector of the first PNP transistor is connected to the source of the eighth NMOS transistor (MN8), and the emitter of the first PNP transistor is connected to the base of the second NPN transistor (QN).