CN115173673A - Power supply device and power supply system - Google Patents
Power supply device and power supply system Download PDFInfo
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- CN115173673A CN115173673A CN202210975589.1A CN202210975589A CN115173673A CN 115173673 A CN115173673 A CN 115173673A CN 202210975589 A CN202210975589 A CN 202210975589A CN 115173673 A CN115173673 A CN 115173673A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
Abstract
The present disclosure provides a power supply device and a power supply system. The power supply device comprises a switching step-down transformer, a controller and a linear voltage regulator. The switching buck is configured to buck an input voltage to a first output voltage. The controller is configured to generate a set of control signals based on the first output voltage of the switching buck. The linear regulator is configured to generate a second output voltage based on the input voltage for a first period based on the set of control signals, and to generate the second output voltage based on the first output voltage for a second period after the first period. By generating the second output voltage based on the first output voltage in the second period, the power consumption of the power supply apparatus can be reduced.
Description
Technical Field
The present disclosure relates to electronic circuits, and more particularly, to power supply devices and power supply systems.
Background
The buck power management chip is widely applied to power supply applications of various electronic devices. The buck power management chip operates a load normally by stepping down an input voltage supplied from a power supply device (such as a battery or an adapter) on an input side to an output voltage suitable for operation of the load on an output side.
According to an implementation mode, the buck power management chip is mainly divided into a continuous working buck converter and a switching buck converter. One type of continuous-operation voltage dropper is the linear regulator (LDO). The output power tube of the LDO is in a long pass mode, so the output voltage ripple is small and the circuit structure is simple, but the energy conversion efficiency is low. A BUCK switching BUCK is a BUCK BUCK. The BUCK-booster has high energy conversion efficiency, but has large ripple and a complicated circuit. However, there are deficiencies with either type of buck power management chip.
Disclosure of Invention
In view of the above, the present disclosure provides a power supply apparatus and a power supply system.
In a first aspect of the present disclosure, a power supply device is provided. The power supply device comprises a switching step-down transformer, a controller and a linear voltage regulator. The switching dropper is configured to drop an input voltage to a first output voltage. The controller is configured to generate a set of control signals based on the first output voltage of the switching buck. The linear regulator is configured to generate a second output voltage based on the input voltage for a first period based on the set of control signals; and generating a second output voltage based on the first output voltage for a second period of time after the first period of time.
In a second aspect of the present disclosure, a power supply system is provided. The power supply system comprises a power supply and a power supply device according to the first aspect, the power supply device being provided with an input voltage by the power supply.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Drawings
The above and other objects, structures and features of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown by way of example and not limitation. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
Fig. 1 shows a schematic diagram of a power supply system in which a power supply apparatus according to an embodiment of the present disclosure may be implemented.
Fig. 2 shows a schematic block diagram of a power supply device according to one embodiment of the present disclosure.
Fig. 3 shows a schematic block diagram of a power supply device according to another embodiment of the present disclosure.
Fig. 4 shows a schematic circuit diagram of a controller and a linear regulator in a power supply apparatus according to one embodiment of the present disclosure.
Fig. 5 shows a schematic circuit diagram of a controller and a linear regulator in a power supply apparatus according to another embodiment of the present disclosure.
Fig. 6 shows a schematic waveform timing diagram of respective signals of a power supply device according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure. In some or all cases it may be evident that any of the embodiments described below may be practiced without employing the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.
In the description of the embodiments of the present disclosure, the words "comprise" and variations such as "comprises" and "comprising" should be understood to be open-ended, i.e., "including but not limited to. The expression "based on" should be understood as "based at least in part on". The expression "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The expressions "first", "second" etc. may refer to different or the same objects. Other explicit and implicit definitions are also possible below.
The buck power management chip is continuously developed towards higher efficiency and higher integration level. For example, in some related schemes, by integrating LDOs capable of independent operation inside the switching step-down device to form an integrated switching step-down device, various stable voltages can be provided for the outside at the same time. This can enrich the chip functions and improve the integration of the power supply module.
However, in some integrated switching step-down converters, the LDO may cause large power consumption, thereby reducing the energy conversion efficiency of the entire switching step-down converter. In addition, the heat dissipation problem of the chip is brought, and the service life of the chip is influenced.
In some related technical solutions of the integrated switching buck converter integrated with the LDO, an input end of the LDO is connected to an input end of the switching buck converter, and an input voltage of the LDO is an input voltage V of the switching buck converter IN . The output voltage of LDO is V OUT And the current flowing through the LDO under the condition that the output load is fixed is I LOAD . In this case, the power consumption of the LDO is the product of the voltage difference between the input and the output of the LDO and the current flowing through the LDO, i.e., (V) IN -V OUT )*I LOAD . Typically, this results in a large LDO power consumption, resulting in a reduction in the energy conversion efficiency of the overall integrated switching buck converter. In addition, this can also make the heat dissipation problem of the chip serious, and even affect the service life of the chip.
In an embodiment of the present disclosure, an improved power supply apparatus is provided that provides an improved controller and LDO. The LDO is capable of taking an input voltage (e.g., a power supply voltage) of the switching dropper as an input voltage of the LDO before the output voltage of the switching dropper stabilizes, and taking the output voltage of the switching dropper as the input voltage of the LDO after the output voltage of the switching dropper stabilizes. This can reduce the input-output voltage difference of the LDO, thereby reducing the power consumption introduced by the LDO.
Fig. 1 shows a schematic diagram of a power supply system 1 in which a power supply apparatus 10 according to an embodiment of the present disclosure may be implemented. The power supply system 1 includes a power supply 2 and a power supply device 10. In one embodiment, the power supply is 2-wayThe power supply device 10 provides an input voltage V IN . The power supply 2 may be, for example, a battery or an adapter. In one embodiment, the input voltage V IN For example, a substantially constant voltage, but this is merely illustrative and not limiting of the scope of the disclosure. Alternatively, the input voltage V IN May vary within certain limits. The power supply device 10 may be configured to supply an output voltage V to a load 4 such as an in-vehicle component, an industrial component, or the like OUT . Input voltage V IN Is stepped down to an output voltage V by a power supply device 10 OUT For supply to the load 4.
Fig. 2 shows a schematic block diagram of a power supply device 10 according to one embodiment of the present disclosure. The power supply apparatus 10 includes a switching step-down 12, a controller 14, and a linear regulator 16. In one embodiment, the switching BUCK 12 may be, for example, a BUCK, and is configured to convert the input voltage V IN Is converted into a first output voltage V OUT1 . The controller 14 is coupled to the switching step-down transformer 12 and the linear regulator 16. The controller 14 is configured to base the first output voltage V of the switching step-down transformer 12 on OUT1 A set of control signals (not shown in the figure) is generated. The set of control signals includes at least one control signal to control the operation of the linear regulator 16 during different time periods, as described in detail below.
In one embodiment, linear regulator 16 includes an input terminal and an Enable (EN) terminal, and is configured to generate a second output voltage V based on different input terminal voltages at different time periods when the enable terminal is active and linear regulator 16 is operating normally OUT2 . For example, linear regulator 16 operates for a first time period T 1 Based on input voltage V IN Generating a second output voltage V OUT2 During a first period T 1 Followed by a second period of time T 2 First output voltage V based on switching step-down transformer 12 OUT1 Generating a second output voltage V OUT2 . In other words, the linear regulator 16 generates the second output voltage V based on the different voltages received at different time periods OUT2 。
Fig. 3 shows a schematic block diagram of a power supply apparatus 10 according to another embodiment of the present disclosure. In the embodiment of FIG. 3, the controller 14 includes a first control circuit 141 and a second control circuit 142, and the linear regulator 16 includes a first linear regulation circuit 161 and a second linear regulation circuit 162. In one embodiment, the first linear voltage regulator circuit 161 can be a medium-high voltage linear voltage regulator circuit, and the second linear voltage regulator circuit 162 can be a low-voltage linear voltage regulator circuit.
In this embodiment, the second control circuit 142 is coupled to the output of the switching step-down transformer 12, the first control circuit 141, and the second linear voltage stabilizing circuit 162. The second control circuit 142 is based on the first output voltage V of the switching step-down transformer 12 OUT1 Generating a first intermediate signal PG and a second control signal V ctrl2 . The first control circuit 141 is coupled to the second control circuit 142 and the first linear voltage regulating circuit 161. The first control circuit 141 generates the first control signal V based on the first intermediate signal PG generated by the second control circuit 142 ctrl1 。
A first control signal V ctrl1 The first linear regulator circuit 161 is controlled such that the first linear regulator circuit 161 is based on the input voltage V during a first period of time IN Generating a second output voltage V of the linear regulator 16 OUT2 . In one embodiment, the first period is a first output voltage V from the start of the switching dropper 12 to the switching dropper 12 OUT1 A period of time to reach a steady state reference voltage value. During the first period, the first linear voltage stabilizing circuit 161 is enabled and the second linear voltage stabilizing circuit 162 is disabled. Second control signal V ctrl2 The second linear voltage stabilizing circuit 162 is controlled such that the second linear voltage stabilizing circuit 12 is based on the first output voltage V in the second period OUT1 Generating a second output voltage V of the linear regulator 16 OUT2 . In one embodiment, the second period follows the first period, and during the second period, the second linear regulation circuit 162 is enabled while the first linear regulation circuit 161 is disabled.
Fig. 4 shows a schematic circuit diagram of the controller 14 and the linear regulator 16 in the power supply apparatus 10 according to one embodiment of the present disclosure. The example circuit shown in fig. 4 may be one example implementation of the controller 14 and the linear regulator 16 of the power supply apparatus 10 shown in fig. 2 or 3. The controller 14 includes a first control circuit 141 and a second control circuit 142.
The second control circuit 142 includes a first comparator 1420 and a third transistor Q3. The first comparator 1420 is based on a first reference voltage V REF1 And a first output voltage V of the switching step-down transformer 12 OUT1 Generating the first intermediate signal PG. In one embodiment, the first reference voltage V REF1 The first output voltage V is input to the inverting terminal of the first comparator 1420 OUT1 To the non-inverting terminal of the first comparator 1420. The third transistor Q3 is coupled between the power supply voltage VDD and the linear regulator 16. The third transistor Q3 is turned on in response to the first intermediate signal PG being a first value. In one embodiment, the first value is low and the third transistor Q3 is a P-type metal oxide semiconductor (PMOS) transistor, such as a high voltage tolerant PMOS. In addition, although a PMOS transistor is schematically illustrated herein, it is understood that an N-type metal oxide semiconductor (NMOS) transistor may be used to implement the third transistor Q3. Accordingly, signals received by the non-inverting terminal and the inverting terminal of the first comparator 1420 may be interchanged with the situation shown in fig. 3.
In one embodiment, the first reference voltage V REF1 It may indicate whether the output voltage of the switching dropper 12 has reached a steady state. A first reference voltage V REF1 Can be set to the final steady-state output voltage V at the switching buck 12 OUT1 In a range of ratios, for example, 85% to 100%. As an example, the first reference voltage V REF1 Can be set to the final steady-state output voltage V OUT1 95% of the total.
The first control circuit 141 includes a delay circuit 1410, a first transistor Q1, and a second transistor Q2. The delay circuit 1410 delays the first intermediate signal PG generated by the second control circuit 142 into the delay signal PG d . Although the delay circuit 1410 is shown here as part of the first control circuit 141, this is merely illustrative and not limiting on the scope of the disclosure. In some embodiments, the delay circuit 1410 may be part of the second control circuit 142.
A first transistor Q1 is coupled between a first end of the first resistor R0 and groundAnd in response to a delayed signal PG d And is turned on for the second value. In one embodiment, the second value is high and the first transistor Q1 is an N-type metal oxide semiconductor (NMOS) transistor, such as a high voltage tolerant NMOS transistor. The second transistor Q2 is coupled between the second terminal of the first resistor R0 and the linear regulator 16, and is turned on in response to the first transistor Q1 being turned on. The second transistor Q2 may be a PMOS transistor. Although the first transistor Q1 and the second transistor Q2 are illustrated herein using NMOS transistors and PMOS transistors, respectively, this is merely illustrative and not a limitation on the scope of the present disclosure. In some embodiments, the first transistor Q1 may use a PMOS transistor, for example. In this case, the signal PG is delayed d May be provided to the first transistor after inversion by the inverter. Similarly, an inverter may be disposed between the first transistor Q1 and the second transistor Q2 to adapt the second transistor Q2 implemented with an NMOS transistor.
Continuing with FIG. 4, the linear regulator 16 includes a first linear voltage regulating circuit 161 and a second linear voltage regulating circuit 162. The first linear voltage stabilizing circuit 161 and the second linear voltage stabilizing circuit 162 include a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a third voltage dividing resistor R3 connected in series between a second output node outputting a second output voltage V and a ground GND OUT2 . In other words, the first linear voltage stabilizing circuit 161 and the second linear voltage stabilizing circuit 162 share the first voltage dividing resistor R1, the second voltage dividing resistor R2, and the third voltage dividing resistor R3. It should be understood that the present disclosure is not so limited and may include further implementations of voltage divider circuits.
The first linear voltage stabilizing circuit 161 includes a second comparator 1610 and a seventh transistor Q7. The second comparator 1610 is based on the first sampling voltage V between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 HV And a second reference voltage V REF2 Generating a first control signal V ctrl1 . In one embodiment, the second reference voltage V REF2 The first sampled voltage V is input to the inverting terminal of the second comparator 1610 HV To the non-inverting terminal of the second comparator 1610. In case the second transistor Q2 is turned offIn form, the seventh transistor Q7 is responsive to the first control signal V ctrl1 Based on the input voltage V IN Generating a second output voltage V OUT2 . In one embodiment, the seventh transistor Q7 is a PMOS transistor, such as a high voltage tolerant PMOS transistor. It is to be understood that NMOS is also applicable here to the seventh transistor Q7 by simple circuit conversion.
The second linear voltage stabilizing circuit 162 includes a third comparator 1612 and an eighth transistor Q8. The third comparator 1612 is based on the second sampling voltage V between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 LV And a second reference voltage V REF2 Generating a second control signal V ctrl2 . In one embodiment, the second reference voltage V REF2 The second sampled voltage V is input to the inverting terminal of the third comparator 1612 LV To the non-inverting terminal of the third comparator 1612. The eighth transistor Q8 is responsive to the second control signal V in the case where the third transistor Q3 is turned off ctrl2 Based on the first output voltage V OUT1 Generating a second output voltage V OUT2 . In one embodiment, the eighth transistor Q8 is a PMOS transistor, such as a high voltage tolerant PMOS transistor. It is to be understood that NMOS is also applicable here to the eighth transistor Q8 by simple circuit conversion.
The operation of the schematic circuit shown in fig. 4 is described in detail below. Specifically, in this embodiment, the first comparator 1420 compares the first reference voltage V REF1 And a first output voltage V OUT1 A comparison is made. If the first output voltage V OUT1 Lower than the first reference voltage V REF1 This indicates that the output voltage of the switching dropper 12 has not yet reached the final steady-state output voltage V O The first intermediate signal PG generated by the first comparator 1420 is low level. The third transistor Q3 is turned on in response to the first intermediate signal PG being at a low level, thereby turning on the second control signal V ctrl2 And (5) drawing high. In response to a second control signal V ctrl2 Is pulled high and the eighth transistor Q8 is turned off, thereby disabling the second linear voltage regulating circuit 162. At this time, since the first intermediate signal PG is low, the delay circuit 1410 obtains the delay signal PG based on the first intermediate signal PG d Also at low powerAnd (7) flattening. The first transistor Q1 is responsive to the delay signal PG d And is turned off for low. In response to the first transistor Q1 being turned off, the second transistor Q2 is also turned off, so that the seventh transistor Q7 is not affected by the second transistor Q2, and the first linear voltage stabilizing circuit 161 operates normally in response to the output of the second comparator 1610 being turned on.
Next, when the first output voltage V is applied OUT1 Gradually increases to be higher than the first reference voltage V REF1 At this time, the first intermediate signal PG generated by the first comparator 1420 is inverted to a high level. The third transistor Q3 is turned off in response to the first intermediate signal PG being at a high level, so that the eighth transistor Q8 is not affected by the third transistor Q3, and is turned on in response to the output of the third comparator 1612, so that the second linear voltage stabilizing circuit 162 is enabled. At this time, since the first intermediate signal PG is at a high level, the delay circuit 1410 obtains the delay signal PG based on the first intermediate signal PG d Also high. The first transistor Q1 is responsive to the delay signal PG d Is turned on for high. In response to the first transistor Q1 being turned on, the second transistor Q2 is also turned on, so that the first control signal V ctrl1 Is pulled high causing the seventh transistor Q7 to be turned off, thereby disabling the first linear voltage regulating circuit 161.
In the embodiment shown in FIG. 4, it can be seen that the input terminal of the first linear voltage regulating circuit 161 is input to the input voltage V of the switching buck 12 IN . When the first linear regulator circuit 161 is enabled and the second linear regulator circuit 162 is disabled, the first linear regulator circuit 161 reaches steady state based on the input voltage V IN And a second reference voltage V REF2 Generated steady state output voltage V OUT2_HV The following:
at this time, the power consumption of the first linear voltage regulator circuit 161 is (V) IN -V OUT2_HV )*I load 。
With continued reference to FIG. 4, it can be seen that the input of the second linear voltage regulator circuit 162 is input at the input terminalFirst output voltage V of switching step-down transformer 12 OUT1 . When the first linear voltage stabilizing circuit 161 is disabled and the second linear voltage stabilizing circuit 162 is enabled, the second linear voltage stabilizing circuit 162 reaches a steady state based on the first output voltage V OUT1 And a second reference voltage V REF2 Generated steady state output voltage V OUT2_LV The following were used:
at this time, the power consumption of the second linear voltage regulator circuit 162 is (V) OUT1 -V OUT2_LV )*I load 。
Due to the input voltage V of the switching step-down transformer 12 IN Much greater than the first output voltage V of the switching step-down transformer 12 OUT1 And a second output voltage V of the first linear voltage regulator circuit 161 OUT2_HV And the second output voltage V of the second linear voltage stabilizing circuit 162 OUT2_LV The difference between the input voltage and the output voltage (V) of the second linear voltage stabilizing circuit 162 is not large OUT1 -V OUT2_LV ) Less than the input-output voltage difference (V) of the first linear voltage stabilizing circuit 161 IN -V OUT2_HV ). This reduces the power consumption of the linear regulator 16.
In one embodiment, the second reference voltage V REF2 Is the reference voltage generated by the switching dropper 12. A second output voltage V from the second voltage divider resistor R2 and the third voltage divider resistor R3 to the linear voltage reducer 16 OUT2 Sampling to obtain a first sampling voltage V HV And the first sampling voltage V is applied HV Is input as a feedback signal to the non-inverting terminal of the second comparator 1610. A second output voltage V from the first voltage divider resistor R1 and the second voltage divider resistor R2 to the linear voltage reducer 16 OUT2 Sampling to obtain a second sampling voltage V LV And the second sampling voltage V is applied LV Is input as a feedback signal to the non-inverting terminal of the third comparator 1612. By reasonably designing the resistance values of the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3, the first linear voltage-stabilizing circuit 161 and the second linear voltage-stabilizing circuit can be enabledThe output voltage of circuit 162 is within the desired error range.
In the embodiment of fig. 4, the second output voltage V of the linear regulator 16 is varied with the first output voltage V OUT2 Rise to make the first sampling voltage V HV Rises to be greater than a second reference voltage V REF2 . This causes the first control signal V output by the second comparator 1610 ctrl1 And gradually rises until finally the seventh transistor Q7 is turned off, so that the first linear voltage stabilizing circuit 161 is disabled. In this way, the first linear voltage regulating circuit 161 can be naturally and smoothly disabled, avoiding spiking through logic control alone. Meanwhile, the controller 161 can turn off the first linear voltage stabilizing circuit 161 for the second time through logic control, thereby improving the reliability of the circuit.
Fig. 5 shows a schematic circuit diagram of the controller 14 and the linear regulator 16 in the power supply apparatus 10 according to another embodiment of the present disclosure. The embodiment shown in fig. 5 differs from the embodiment shown in fig. 4 in that the second control circuit 142 is different. In the embodiment of fig. 5, the second control circuit 142 includes a current source 1422, a current mirror circuit 1424, an inverter 1426, and a third transistor Q3. Current source 1422 is for providing a reference current I ref . In one embodiment, the reference current I ref Indicating whether the output voltage of the switching dropper 12 has reached a steady state. The current mirror circuit 1424 is based on the first output voltage V of the switching step-down transformer 12 OUT1 And a reference current I ref A second intermediate signal Y1 is generated. The inverter 1426 inverts the second intermediate signal Y1 to generate the first intermediate signal PG. The third transistor Q3 is coupled between the power supply voltage VDD and the linear regulator 16 and is turned on in response to the first intermediate signal PG being a first value. In one embodiment, the first value is low and the third transistor Q3 is a PMOS transistor, e.g., a high voltage tolerant PMOS. It is to be understood that NMOS by simple circuit conversion is also applicable to the third transistor Q3 here.
In one embodiment, the current mirror circuit 1424 includes a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6. The fourth transistor Q4 is coupled between the current source 1422 and ground GND. A fifth transistor Q5 and a fourth transistorQ4 is common-gate connected and coupled between inverter 1426 and ground GND. The sixth transistor Q6 is coupled between the power supply voltage VDD and the inverter 1426 and is based on the first output voltage V of the switching dropper 12 OUT1 And a reference current I ref A second intermediate signal Y1 is generated. In one embodiment, the current mirror circuit 1424 is a 1. In one embodiment, the fourth transistor Q4 and the fifth transistor Q5 are NMOS transistors, such as high voltage tolerant NMOS transistors, and the sixth transistor Q6 is a PMOS transistor, such as a high voltage tolerant PMOS transistor. It is to be understood that PMOS is also applicable here to the fourth transistor Q4 and the fifth transistor Q5 by simple circuit conversion, and NMOS is also applicable here to the sixth transistor Q6 by simple circuit conversion.
The operation of the schematic circuit shown in fig. 5 is described in detail below. Specifically, the current flowing in the sixth transistor Q6 and the reference current I flowing in the fifth transistor Q5 are set to be equal ref The mirror currents of (a) are compared. Assume that the current mirror circuit 1424 is a 1. Initially, the first output voltage V of the switching step-down transformer 12 OUT1 When the current is small, the current flowing through the sixth transistor Q6 is large. The current flowing in the sixth transistor Q6 is larger than the reference current I ref At this time, the second intermediate signal Y1 is at a high level, and the inverted first intermediate signal PG is at a low level.
Next, when the first output voltage V is applied OUT1 The current flowing through the sixth transistor Q6 gradually decreases as it gradually increases. When the current flowing in the sixth transistor Q6 decreases below the reference current I ref At this time, the second intermediate signal Y1 falls to the low level, and the first intermediate signal PG generated by inversion becomes the high level.
In this embodiment, the operation principle of the first control circuit 141, the first linear voltage stabilizing circuit 161 and the second linear voltage stabilizing circuit 162 is the same as that of the embodiment shown in FIG. 4, and the description is omitted here.
Fig. 6 shows schematic waveform timing diagrams of respective signals of the power supply device 10 according to an embodiment of the present disclosure.
At time t1, the circuit starts to start, and the first output voltage and the second output voltage are both low level.
During the period from time t1 to time t2, the first output voltage V of the switching step-down transformer 12 OUT1 Gradually increases until it is higher than the first reference voltage V REF1 . At time t2, the first intermediate signal PG generated by the first comparator 1420 is inverted to a high level. At this time, the delayed signal PG of the first intermediate signal PG d Still low, the second linear voltage regulator circuit 162 is initially enabled and the first linear voltage regulator circuit 161 is still active. At this time, the input of the linear regulator 16 is still the input of the first linear voltage regulating circuit 161, i.e. the input voltage V of the switching step-down transformer 12 IN . The second output voltage V of the linear regulator 16 during the time period from t1 to t2 OUT2 Gradually increases to the voltage V output by the first linear voltage stabilizing circuit 161 after reaching the steady state OUT2_HV Then maintaining V OUT2_HV Until time t 2.
During the period from time t2 to time t3, the first output voltage V of the switching step-down transformer 12 OUT1 Continues to increase until a final steady-state output voltage V is reached O And then remains unchanged. The first intermediate signal PG maintains a high level. At time t3, the delayed signal PG of the first intermediate signal PG d The flip to high level disables the first linear voltage regulating circuit 161 and keeps the second linear voltage regulating circuit 162 enabled. At time t3, the input of the linear regulator 16 is the input of the second linear regulator circuit 162, i.e. the first output voltage V of the switching step-down transformer 12 OUT1 . The second output voltage V of the linear regulator 16 during the period from time t2 to time t3 OUT2 The voltage V gradually outputted from the first linear voltage stabilizing circuit 161 after reaching the steady state OUT2_HV The voltage V output after the second linear voltage stabilizing circuit 162 reaches the steady state is increased OUT2_LV . At time t3 and thereafter, the second output voltage V of the linear regulator 16 OUT2 Is maintained at the voltage V output by the second linear voltage stabilizing circuit 162 after reaching the steady state OUT2_LV And is not changed.
In one embodiment, the period from time T1 to time T2 represents a first time period T 1 And after time T3 represents a second time period T 2 . A first period of timeT 1 Typically short, e.g., a few milliseconds.
Through the embodiment of the disclosure, an improved power supply device is provided, in which a linear voltage regulator is integrated into a switching step-down transformer, and before the output voltage of the switching step-down transformer is stabilized, the input voltage of the switching step-down transformer is used as the input voltage of the linear voltage regulator, and after the output voltage of the switching step-down transformer is stabilized, the output voltage of the switching step-down transformer is used as the input voltage of the linear voltage regulator, so that the output function of the integrated switching step-down transformer can be enriched, the input-output voltage difference of the linear voltage regulator can be reduced, and the power consumption introduced by the linear voltage regulator can be reduced. In addition, through the embodiment of the disclosure, the first linear voltage stabilizing circuit can be naturally and smoothly disabled, and spike pulse caused by simple logic control can be avoided. Meanwhile, the controller can perform secondary turn-off on the first linear voltage stabilizing circuit, so that the reliability of the circuit is improved.
The embodiments may be further described using the following clauses:
a switching dropper configured to drop an input voltage to a first output voltage;
a controller configured to generate a set of control signals based on the first output voltage of the switching buck; and
a linear regulator configured to, based on the set of control signals:
generating a second output voltage based on the input voltage for a first period; and
generating the second output voltage based on the first output voltage for a second period of time after the first period of time.
a first control circuit configured to generate a first control signal based on a first intermediate signal, the first control signal causing the linear regulator to generate the second output voltage based on the input voltage during the first period; and
a second control circuit configured to generate the first intermediate signal and a second control signal based on the first output voltage, the second control signal causing the linear regulator to generate the second output voltage based on the first output voltage during the second period.
Clause 3. The power supply apparatus according to clause 1, wherein the linear regulator includes:
a first linear voltage regulation circuit configured to generate a second output voltage based on the input voltage during the first period and to be disabled during the second period; and
a second linear regulation circuit configured to generate the second output voltage based on the first output voltage during the second period and to be disabled during the first period.
Clause 4. The power supply device according to clause 2, wherein the first control circuit includes:
a delay circuit configured to delay the first intermediate signal into a delayed signal;
a first transistor coupled between a first end of a first resistor and ground and configured to turn on in response to the delayed signal being a second value; and
a second transistor coupled between a second terminal of the first resistor and the linear regulator and configured to turn on in response to the first transistor turning on.
Clause 5. The power supply device according to clause 2, wherein the second control circuit includes:
a first comparator configured to generate the first intermediate signal based on the first reference voltage and the first output voltage; and
a third transistor coupled between a supply voltage and the linear regulator and configured to turn on in response to the first intermediate signal being a first value.
Clause 6. The power supply device according to clause 2, wherein the second control circuit includes:
a current source for providing a reference current;
a current mirror circuit configured to generate a second intermediate signal based on the first output voltage and the reference current;
an inverter configured to invert the second intermediate signal to generate the first intermediate signal; and
a third transistor coupled between a supply voltage and the linear regulator and configured to turn on in response to the first intermediate signal being a first value.
Clause 7. The power supply device according to clause 6, wherein the current mirror circuit includes:
a fourth transistor coupled between the current source and ground;
a fifth transistor which is connected in common with the fourth transistor and which is coupled between the inverter and ground; and
a sixth transistor coupled between a supply voltage and the inverter and configured to generate the second intermediate signal based on the first output voltage and the reference current.
Clause 8. The power supply arrangement of clause 3, wherein the first and second linear voltage regulating circuits include:
a first voltage-dividing resistor, a second voltage-dividing resistor and a third voltage-dividing resistor connected in series between the second output node and ground, wherein the voltage output by the second output node is a second output voltage V OUT2 。
Clause 9. The power supply arrangement of clause 8, wherein the first linear voltage regulating circuit includes:
a second comparator configured to generate the first control signal based on a first sampling voltage between the second voltage-dividing resistor and the third voltage-dividing resistor and a second reference voltage; and
a seventh transistor configured to generate the second output voltage based on the input voltage in response to the first control signal.
a third comparator configured to generate the second control signal based on a second sampling voltage between the first voltage-dividing resistor and the second voltage-dividing resistor and a second reference voltage; and
an eighth transistor configured to generate the second output voltage based on the first output voltage in response to the second control signal.
Clause 11, a power supply apparatus, comprising:
a power source; and
the power supply device according to any one of claims 1 to 10, the input voltage being supplied by the power supply.
Further, the present disclosure provides various example embodiments, as described and as illustrated in the accompanying drawings. However, the present disclosure is not limited to the embodiments described and illustrated herein, but may extend to other embodiments, as known or as would be known to those skilled in the art. Reference in the specification to "one embodiment," "the embodiments," or "some embodiments" means that a particular feature, structure, or characteristic described is included in at least one embodiment, and the appearances of these phrases in various places in the specification are not necessarily all referring to the same embodiment.
Finally, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended drawings is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.
Claims (11)
1. A power supply device (10) comprising:
a switching step-down transformer (12) configured to convert an input voltage (V) IN ) Step-down to a first output voltage (V) OUT1 )；
A controller (14) configured to base the first output voltage (Vv) of the switching step-down transformer (12) OUT1 ) Generating a set of control signals; and
a linear regulator (16) configured to, based on the set of control signals:
in a first period (T) 1 ) Based on the input voltage (V) IN ) Generating a second output voltage (V) OUT2 ) (ii) a And
during the first period (T) 1 ) A second period of time (T) thereafter 2 ) Based on the first output voltage (V) OUT1 ) Generating the second output voltage (V) OUT2 )。
2. The power supply device (10) according to claim 1, wherein the controller (14) includes:
a first control circuit (141) configured to generate a first control signal (V) based on the first intermediate signal (PG) ctrl1 ) Said first control signal (Vctrl 1) causing said linear regulator (16) to operate for said first period (T) 1 ) Based on the input voltage (V) IN ) Generating the second output voltage (V) OUT2 ) (ii) a And
a second control circuit (142) configured to generate the first intermediate signal (PG) and a second control signal (V) based on the first output voltage (VOUT 1) ctrl2 ) Said second control signal (V) ctrl2 ) Causing the linear regulator (16) to operate for the second period (T) 2 ) Based on the first output voltage (V) OUT1 ) Generating the second output voltage (V) OUT2 )。
3. The power supply device (10) according to claim 1, wherein the linear regulator (16) comprises:
a first linear voltage regulation circuit (161) configured to be in the first time period (T) 1 ) Based on the input voltage (V) IN ) Generating a second output voltage (V) OUT2 ) And disabled for said second period (T2); and
a second linear voltage regulating circuit (162) configured to operate for the second period of time (T) 2 ) Based on the first output voltage (V) OUT1 ) Generating the second output voltage (V) OUT2 ) And during said first period (T) 1 ) Is disabled.
4. The power supply device (10) according to claim 2, wherein the first control circuit (141) includes:
a delay circuit (1410) configured to delay the first intermediate signal (PG) into a delayed signal (PG) d )；
A first transistor (Q1) coupled between a first end of the first resistor and ground and configured to be responsive to the delayed signal (PG) d ) Is turned on for a second value; and
a second transistor (Q2) coupled between a second terminal of the first resistor and the linear regulator (16) and configured to conduct in response to the first transistor (Q1) conducting.
5. The power supply device (10) according to claim 2, wherein the second control circuit (142) comprises:
a first comparator (1420) configured to be based on the first reference voltage (Vv) REF1 ) And said first output voltage (V) OUT1 ) -generating the first intermediate signal (PG); and
a third transistor (Q3) coupled between a supply voltage and the linear regulator (16) and configured to turn on in response to the first intermediate signal (PG) being a first value.
6. The power supply device (10) according to claim 2, wherein the second control circuit (142) includes:
a current source (1422) for providing a reference current (I) ref )；
A current mirror circuit (1424) configured to be based on the first output voltage (V) OUT1 ) And the reference current (I) ref ) Generating a second intermediate signal (Y1);
an inverter (1426) configured to invert the second intermediate signal (Y1) to generate the first intermediate signal (PG); and
a third transistor (Q3) coupled between a supply voltage and the linear regulator (16) and configured to turn on in response to the first intermediate signal (PG) being a first value.
7. The power supply device (10) according to claim 6, wherein the current mirror circuit (1424) includes:
a fourth transistor (Q4) coupled between the current source (1422) and ground;
a fifth transistor (Q5) which is common-gate connected with the fourth transistor (Q4) and which is coupled between the inverter (1426) and ground; and
a sixth transistor (Q6) coupled between a supply voltage and the inverter (1426) and configured to be based on the first output voltage (V OUT1 ) And the reference current (I) ref ) Generating the second intermediate signal (Y1).
8. The power supply arrangement (10) of claim 3, wherein the first linear voltage regulating circuit (161) and the second linear voltage regulating circuit (162) comprise:
a first voltage-dividing resistor, a second voltage-dividing resistor and a third voltage-dividing resistor connected in series between the second output node and ground, wherein the voltage output by the second output node is the second output voltage V OUT2 。
9. The power supply arrangement (10) of claim 8, wherein the first linear voltage regulating circuit (161) comprises:
a second comparator (1610) configured to be based on a first sampling voltage (V) between the second and third voltage-dividing resistors HV ) And a second reference voltage (V) REF2 ) Generating the first control signal (V) ctrl1 ) (ii) a And
a seventh transistor (Q7) configured to respond to the first control signal (V) ctrl1 ) Based on the input voltage (V) IN ) Generating the second output voltage (V) OUT2 )。
10. The power supply arrangement (10) of claim 8 wherein the second linear voltage regulating circuit (162) includes:
a third comparator (1612) provided withIs arranged based on a second sampling voltage (V) between the first voltage-dividing resistor and the second voltage-dividing resistor LV ) And a second reference voltage (V) REF2 ) Generating the second control signal (V) ctrl2 ) (ii) a And
an eighth transistor (Q8) configured to respond to the second control signal (V) ctrl2 ) Based on the first output voltage (V) OUT1 ) Generating the second output voltage (V) OUT2 )。
11. A power supply system (1) comprising:
a power supply (2); and
the power supply device (10) according to any one of claims 1 to 10, the input voltage (V) being provided by the power supply (2) IN )。
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| CN202210975589.1A CN115173673A (en) | 2022-08-15 | 2022-08-15 | Power supply device and power supply system |
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201174058Y (en) * | 2007-11-12 | 2008-12-31 | 张飞然 | Standby electric power of ultramicro power consumption |
| CN101470453A (en) * | 2007-12-24 | 2009-07-01 | 瑞昱半导体股份有限公司 | Hybrid voltage regulation apparatus and method |
| CN102642472A (en) * | 2011-02-17 | 2012-08-22 | 上海航鼎电子科技发展有限公司 | Method and device for power management and deadlock protective control of vehicle-mounted positioning and tracking equipment |
| CN103226369A (en) * | 2012-01-31 | 2013-07-31 | 富士通天株式会社 | Power circuit |
| CN103345288A (en) * | 2013-06-19 | 2013-10-09 | 天津大学 | Linear voltage stabilizing power circuit with large-swing input |
| CN205622514U (en) * | 2016-04-29 | 2016-10-05 | 深圳市华芯邦科技有限公司 | Direct current of mixed type circuit converting means that can step down |
| CN107769524A (en) * | 2017-11-09 | 2018-03-06 | 杰华特微电子（杭州）有限公司 | power supply circuit and switching power supply |
| CN109101067A (en) * | 2018-08-10 | 2018-12-28 | 电子科技大学 | A kind of low pressure difference linear voltage regulator of dual power rail |
| CN110011536A (en) * | 2019-05-06 | 2019-07-12 | 核芯互联(北京)科技有限公司 | A kind of power circuit |
| CN111158419A (en) * | 2020-01-13 | 2020-05-15 | 维沃移动通信有限公司 | Power supply circuit, current acquisition method and electronic equipment |
| CN111786557A (en) * | 2020-09-07 | 2020-10-16 | 武汉精测电子集团股份有限公司 | Power circuit and signal generator capable of automatically reducing power consumption of LDO (low dropout regulator) |
| CN111934546A (en) * | 2020-08-10 | 2020-11-13 | 昂宝电子（上海）有限公司 | Switching regulator control system and switching regulator |
| CN112148053A (en) * | 2019-06-28 | 2020-12-29 | 台湾积体电路制造股份有限公司 | Circuit and method for generating reference voltage and reference voltage generator |
-
2022
- 2022-08-15 CN CN202210975589.1A patent/CN115173673A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201174058Y (en) * | 2007-11-12 | 2008-12-31 | 张飞然 | Standby electric power of ultramicro power consumption |
| CN101470453A (en) * | 2007-12-24 | 2009-07-01 | 瑞昱半导体股份有限公司 | Hybrid voltage regulation apparatus and method |
| CN102642472A (en) * | 2011-02-17 | 2012-08-22 | 上海航鼎电子科技发展有限公司 | Method and device for power management and deadlock protective control of vehicle-mounted positioning and tracking equipment |
| CN103226369A (en) * | 2012-01-31 | 2013-07-31 | 富士通天株式会社 | Power circuit |
| CN103345288A (en) * | 2013-06-19 | 2013-10-09 | 天津大学 | Linear voltage stabilizing power circuit with large-swing input |
| CN205622514U (en) * | 2016-04-29 | 2016-10-05 | 深圳市华芯邦科技有限公司 | Direct current of mixed type circuit converting means that can step down |
| CN107769524A (en) * | 2017-11-09 | 2018-03-06 | 杰华特微电子（杭州）有限公司 | power supply circuit and switching power supply |
| CN109101067A (en) * | 2018-08-10 | 2018-12-28 | 电子科技大学 | A kind of low pressure difference linear voltage regulator of dual power rail |
| CN110011536A (en) * | 2019-05-06 | 2019-07-12 | 核芯互联(北京)科技有限公司 | A kind of power circuit |
| CN112148053A (en) * | 2019-06-28 | 2020-12-29 | 台湾积体电路制造股份有限公司 | Circuit and method for generating reference voltage and reference voltage generator |
| CN111158419A (en) * | 2020-01-13 | 2020-05-15 | 维沃移动通信有限公司 | Power supply circuit, current acquisition method and electronic equipment |
| CN111934546A (en) * | 2020-08-10 | 2020-11-13 | 昂宝电子（上海）有限公司 | Switching regulator control system and switching regulator |
| CN111786557A (en) * | 2020-09-07 | 2020-10-16 | 武汉精测电子集团股份有限公司 | Power circuit and signal generator capable of automatically reducing power consumption of LDO (low dropout regulator) |
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