CN111555615B - Frequency regulating circuit suitable for buck-boost converter - Google Patents

Frequency regulating circuit suitable for buck-boost converter Download PDF

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CN111555615B
CN111555615B CN202010393315.2A CN202010393315A CN111555615B CN 111555615 B CN111555615 B CN 111555615B CN 202010393315 A CN202010393315 A CN 202010393315A CN 111555615 B CN111555615 B CN 111555615B
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CN111555615A (en
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奚冬杰
徐晴昊
李现坤
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits

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  • Power Engineering (AREA)
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Abstract

The invention discloses a frequency regulating circuit suitable for a buck-boost converter, and belongs to the technical field of electronic analog circuits. The frequency adjusting circuit suitable for the buck-boost converter comprises NMOS transistors MN 1-MN 4, PMOS transistors MP 1-MP 4, triodes NPN 1-NPN 4, resistors R1-R4, a diode D1, current sources I1-I4, an operational amplifier AMP1 and a comparator COMP 1. Aiming at the application occasion with instantaneous peak input, the circuit of the invention does not need to set the working frequency of a chip too low for increasing the conduction time of the power tube, and meets the requirement of current detection delay on the minimum conduction time of the power tube; thereby avoiding the use of large-sized peripheral devices and finally reducing the design cost.

Description

Frequency regulating circuit suitable for buck-boost converter
Technical Field
The invention relates to the technical field of electronic analog circuits, in particular to a frequency regulating circuit suitable for a buck-boost converter.
Background
In a power switch control circuit, a buck-boost converter is widely applied due to the advantages of simple circuit structure, high efficiency, easy control, random combination of input and output voltages and the like. The circuit structure of the conventional buck-boost converter is shown in fig. 1. PWM is a control logic level that controls the power transistor MN1 to turn on and off periodically. D1 is a reverse freewheeling diode. When MN1 is turned on, D1 is turned off, and external input V isINThe inductor L1 is charged. When MN1 is turned off, D1 is turned on and freewheels reversely from the output filter capacitor COUTUp-drawing current, thus finally outputting VOUTNegative pressure.
Generally, to improve the dynamic response performance of the chip, the buck-boost converter performs overall loop control in a peak current mode to maintain stable output voltage. In each turn-on period of the power tube MN1, the inductance current value needs to be detected, and when the inductance current value rises to a set value, the power tube MN1 is required to be immediately turned off until the next clock period comes and then turned on again. In fig. 1, the comparator AMP0 plays a role in current detection, and in the stage of MN1 turning on, the voltage difference between the positive end and the negative end gradually increases as the current in the inductor rises, and AMP0 outputs a high level to turn off MN1 immediately when the inductor current rises to a set value, and turns on MN1 again after waiting for the next clock cycle. And considering the transmission delay of each node in the circuit, if the current detection function needs to be ensured to be normally realized, the loop is controlled, and the circuit output is stabilized. The minimum on time of the power tube MN1 is required to be longer than the current detection comparator AMP0 delay.
Traditional buck-boostThe frequency (f) of operation of the converter in a fixed application, if the parameters of the peripheral device are determinedSW) Is a fixed value. When determining the input V for a certain groupINAnd an output VOUT-, its on-time (T) in each switching cycleON) Comprises the following steps:
Figure BDA0002486734410000011
from the above analysis, it can be known that the conventional buck-boost converter works as the input VINFar greater than the output VOUT-In each switching period, the conduction time of the power tube MN1 is very small, and the final conduction time TONThe delay requirement of the current detection comparator is not met, the current detection function cannot be normally realized, and a loop cannot be controlled to stabilize the output voltage.
Disclosure of Invention
The invention aims to provide a frequency regulating circuit suitable for a buck-boost converter, which aims to solve the problems that the traditional buck-boost converter has the characteristic that the working frequency is irrelevant to the input and output voltages, and when the traditional buck-boost converter works under the conditions of maximum input and minimum output, the minimum conduction time of a power tube cannot meet the current detection delay requirement, so that a chip cannot work normally, a loop is not controlled, and the output is unstable.
In order to solve the technical problem, the invention provides a frequency regulating circuit suitable for a buck-boost converter, which comprises NMOS tubes MN 1-MN 4, PMOS tubes MP 1-MP 4, triodes NPN 1-NPN 4, resistors R1-R4, a diode D1, current sources I1-I4, an operational amplifier AMP1 and a comparator COMP 1; wherein the content of the first and second substances,
the drain terminal of NMOS transistor MN1 is connected to the base terminal of triode NPN1, the gate terminal is connected to the gate terminal of NMOS transistor MN4, the source terminal is connected to the output terminal VOUT-; the drain end of the NMOS tube MN2 is connected with the first end of a resistor R3, the gate end is connected with the output end of a comparator COMP1, and the source end is connected with the first end of a second resistor R2; the drain end of the NMOS tube MN3 is connected with the drain end of the PMOS tube MP3, the gate end is connected with the output end of the operational amplifier AMP1, and the source end is connected with the first end of a resistor R4; the drain terminal of NMOS transistor MN4 is connected to the drain terminal of PMOS transistor MP4, the gate terminal is connected to the drain terminal of PMOS transistor MP4, and the source terminal is connected to the output terminal VOUT-；
PMOS transistor MP1 with drain connected to its gate, gate connected to NPN4 collector, and source connected to input end VIN(ii) a The drain terminal of PMOS transistor MP2 is connected to the first terminal of resistor R1, the gate terminal is connected to the gate terminal of PMOS transistor MP1, the source terminal is connected to input terminal VIN(ii) a PMOS transistor MP3 with drain terminal connected to drain terminal of NMOS transistor MN3, gate terminal connected to gate terminal of PMOS transistor MP4, source terminal connected to input terminal VIN(ii) a PMOS transistor MP4 with drain terminal connected to gate terminal of NMOS transistor MN4, gate terminal connected to gate terminal of PMOS transistor MP3, and source terminal connected to input terminal VIN；
The collector of the triode NPN1 is connected with the negative terminal of the current source I1, the base is connected with the drain terminal of the NMOS transistor MN1, the emitter is connected with the output terminal VOUT-; the collector of the triode NPN2 is connected with the input end VINThe base electrode is connected with the negative end of a current source I2, and the emitter electrode is connected with the drain end of an NMOS tube MN 1; the collector of the triode NPN3 is connected with the input end VINThe base electrode is connected with the base electrode of an NPN triode NPN2, and the emitter electrode is connected with the positive end of a current source I4; the collector of the triode NPN4 is connected with the drain of the PMOS tube MP1, the base is connected with the positive end of the current source I4, and the emitter is connected with the output end VOUT-；
The resistor R1 has a first terminal connected to the drain terminal of the PMOS transistor MP2 and a second terminal connected to the output terminal VOUT-; the resistor R2 has a first terminal connected to the source terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R3 has a first terminal connected to the drain terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R4 has a first terminal connected to the source terminal of the NMOS transistor MN3 and a second terminal connected to the output terminal VOUT-；
The positive ends of the current sources I1-I3 are connected with the input end VIN(ii) a The negative end of the current source I1 is connected with the collector of the triode NPN1, the negative end of the current source I2 is connected with the base of the triode NPN2, and the negative end of the current source I3 is connected with the first end of the resistor R3; the positive end of the current source I4 is connected with the emitter of the triode NPN3, and the negative end is connected with the output end VOUT-；
The positive end of the diode D1 is connected with the base electrode of the triode NPN2, and the negative end of the diode D1 is connected with the collector electrode of the triode NPN 1; the positive input end of the operational amplifier AMP1 is connected with the drain end of an NMOS tube MN2, the negative input end is connected with the source end of an NMOS tube MN3, and the output end is connected with the gate end of an NMOS tube MN 3; the positive input end of the comparator COMP1 is connected with the drain end of the PMOS tube MP2, the negative input end is connected with the reference voltage VREF1, and the output end is connected with the gate end of the NMOS tube MN 2.
Optionally, the current source I4 includes an operational amplifier AMP2, PMOS transistors MP11 and MP12, an NMOS transistor MN11, and a resistor R11;
PMOS tube MP11 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN11, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 12; PMOS tube MP12 source end connected with input end VINThe drain end is connected with the grid end of the drain;
the gate of the NMOS transistor MN11 is connected with the output end of the operational amplifier AMP2, and the source end is connected with the output end V through a resistor R11OUT-；
The positive input end of the operational amplifier AMP2 is grounded GND, and the negative input end is connected with the source end of the NMOS tube MN 11.
Optionally, the current source I1 includes an operational amplifier AMP3, PMOS transistors MP21 and MP22, an NMOS transistor MN21, and a resistor R21;
PMOS tube MP21 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN21, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 22; PMOS tube MP22 source end connected with input end VINThe drain end is connected with the grid end of the drain;
the gate of the NMOS transistor MN21 is connected with the output end of the operational amplifier AMP3, and the source end is connected with the output end V through a resistor R21OUT-；
An operational amplifier AMP3 has a positive input terminal connected to the input terminal VINAnd the negative input end is connected with the source end of an NMOS tube MN 21.
The invention has the following beneficial effects:
(1) for a certain fixed input and output combination, if the conduction time of a power tube corresponding to the working frequency of the circuit meets the requirement of current detection delay on the minimum conduction time, the frequency regulating circuit does not work and has no influence on the working of the circuit; if the output voltage does not meet the preset value, the frequency regulating circuit acts to reduce the working frequency of the chip to one fifth of the set value, so that the chip can normally work to maintain the stability of the output voltage;
(2) aiming at the application occasion with instantaneous peak input, the circuit of the invention does not need to set the working frequency of a chip too low for increasing the conduction time of the power tube, and meets the requirement of current detection delay on the minimum conduction time of the power tube; thereby avoiding the use of large-sized peripheral devices and finally reducing the design cost.
Drawings
FIG. 1 is a schematic diagram of a conventional buck-boost converter system architecture;
FIG. 2 is a schematic diagram of a frequency regulation circuit suitable for a buck-boost converter according to the present invention;
FIG. 3 is a graph of (V)IN+|VOUT- |) a proportional current generating circuit;
FIG. 4 is a graph of the sum | VOUT- | is proportional to the current generating circuit.
Detailed Description
The frequency regulating circuit suitable for the buck-boost converter according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a frequency regulating circuit suitable for a buck-boost converter, which has a structure shown in fig. 2 and comprises NMOS tubes MN 1-MN 4, PMOS tubes MP 1-MP 4, triodes NPN 1-NPN 4, resistors R1-R4, a diode D1, current sources I1-I4, an operational amplifier AMP1 and a comparator COMP 1; the drain terminal of NMOS transistor MN1 is connected to base electrode of triode NPN1, gate terminal is connected to gate terminal of NMOS transistor MN4, source terminal is connected to output terminal VOUT-; the drain end of the NMOS tube MN2 is connected with the first end of a resistor R3, the gate end is connected with the output end of a comparator COMP1, and the source end is connected with the first end of a second resistor R2; the drain end of the NMOS tube MN3 is connected with the drain end of the PMOS tube MP3, the gate end is connected with the output end of the operational amplifier AMP1, and the source end is connected with the first end of a resistor R4; the drain terminal of NMOS transistor MN4 is connected to the drain terminal of PMOS transistor MP4, the gate terminal is connected to the drain terminal of PMOS transistor MP4, and the source terminal is connected to the output terminal VOUT-; PMOS transistor MP1 with drain connected to its gate, gate connected to NPN4 collector, and source connected to input end VIN(ii) a The drain terminal of PMOS transistor MP2 is connected to the first terminal of resistor R1, the gate terminal is connected to the gate terminal of PMOS transistor MP1, the source terminal is connected to input terminal VIN(ii) a PMOS transistor MP3 with drain terminal connected to drain terminal of NMOS transistor MN3, gate terminal connected to gate terminal of PMOS transistor MP4, source terminal connected to input terminal VIN(ii) a PMOS transistor MP4 with drain terminal connected to gate terminal of NMOS transistor MN4, gate terminal connected to gate terminal of PMOS transistor MP3, and source terminal connected to input terminal VIN(ii) a The collector of the triode NPN1 is connected with the negative terminal of the current source I1, the base is connected with the drain terminal of the NMOS transistor MN1, the emitter is connected with the output terminal VOUT-; the collector of the triode NPN2 is connected with the input end VINThe base electrode is connected with the negative end of a current source I2, and the emitter electrode is connected with the drain end of an NMOS tube MN 1; the collector of the triode NPN3 is connected with the input end VINThe base electrode is connected with the base electrode of an NPN triode NPN2, and the emitter electrode is connected with the positive end of a current source I4; the collector of the triode NPN4 is connected with the drain of the PMOS tube MP1, the base is connected with the positive end of the current source I4, and the emitter is connected with the output end VOUT-; the resistor R1 has a first terminal connected to the drain terminal of the PMOS transistor MP2 and a second terminal connected to the output terminal VOUT-; the resistor R2 has a first terminal connected to the source terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R3 has a first terminal connected to the drain terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R4 has a first terminal connected to the source terminal of the NMOS transistor MN3 and a second terminal connected to the output terminal VOUT-; the positive ends of the current sources I1-I3 are connected with the input end VIN(ii) a The negative end of the current source I1 is connected with the collector of the triode NPN1, the negative end of the current source I2 is connected with the base of the triode NPN2, and the negative end of the current source I3 is connected with the first end of the resistor R3; the positive end of the current source I4 is connected with the emitter of the triode NPN3, and the negative end is connected with the output end VOUT-; the positive end of the diode D1 is connected with the base electrode of the triode NPN2, and the negative end of the diode D1 is connected with the collector electrode of the triode NPN 1; the positive input end of the operational amplifier AMP1 is connected with the drain end of an NMOS tube MN2, the negative input end is connected with the source end of an NMOS tube MN3, and the output end is connected with the gate end of an NMOS tube MN 3; the positive input end of the comparator COMP1 is connected with the drain end of the PMOS tube MP2, the negative input end is connected with the reference voltage VREF1, and the output end is connected with the gate end of the NMOS tube MN 2.
Referring to FIG. 3, the current source I1 is a schematic diagram of the structure, namely, the AND (V)IN+|VOUT- |) proportional current generating circuit, including an operational amplifier AMP3, PMOS transistors MP21 and MP22, NMOS transistor MN21 and resistor R21; PMOS tube MP21 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN21, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 22; PMOS tube MP22 source end connected with input end VINThe drain end is connected with the grid end of the drain; the gate of the NMOS transistor MN21 is connected with the output end of the operational amplifier AMP3, and the source end is connected with the output end V through a resistor R21OUT-; an operational amplifier AMP3 has a positive input terminal connected to the input terminal VINAnd the negative input end is connected with the source end of an NMOS tube MN 21.
FIG. 4 is a schematic diagram of a current source I4, i.e., AND | VOUT- | proportional current generating circuit, including operational amplifier AMP2, PMOS tubes MP11 and MP12, and NMOS tube MN11 and a resistor R11; PMOS tube MP11 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN11, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 12; PMOS tube MP12 source end connected with input end VINThe drain end is connected with the grid end of the drain; the gate of the NMOS transistor MN11 is connected with the output end of the operational amplifier AMP2, and the source end is connected with the output end V through a resistor R11OUT-; the positive input end of the operational amplifier AMP2 is grounded GND, and the negative input end is connected with the source end of the NMOS tube MN 11.
The working principle of the invention is as follows:
(1) and (V)IN+|VOUT- |) proportional current generating circuit analysis:
FIG. 3 is a graph of AND (V)IN+|VOUT- |) is proportional to the current generating circuit. The operational amplifier AMP3 and NMOS transistor MN21 perform negative feedback clamping action, which forces the source terminal voltage and input terminal V of NMOS transistor MN21INAre equal. The PMOS transistors MP21 and MP22 form a current mirror that mirrors the current flowing through resistor R21 to I1, so that for I1 there are:
Figure BDA0002486734410000061
(2) and | VOUT- | proportional current generating circuit analysis:
FIG. 4 is a graph of AND | VOUT- | is proportional to the current generating circuit. The operational amplifier AMP2 and NMOS transistor MN11 act as a negative feedback clamp, which forces the source terminal voltage of NMOS transistor MN11 to be equal to ground GND. The PMOS transistors MP12 and MP11 form a current mirror that mirrors the current flowing through resistor R11 to I4, so that for I4 there are:
Figure BDA0002486734410000062
(3) the frequency adjustment circuit analyzes:
fig. 2 shows a frequency regulating circuit suitable for a buck-boost converter, in which the current sources I1 and I4 are generated by the circuits shown in fig. 3 and 4, respectively.
The operational amplifier AMP1 and NMOS transistor MN3 in FIG. 2 act as a negative feedback clamp, forcing the source voltages of NMOS transistor MN3 to be equal toThe positive input terminals of the operational amplifier AMP1 are preset with the same reference voltage. The charge and discharge current of the oscillator in the circuit can be set through the resistor R4. The PMOS transistors MP3 and MP4 and the NMOS transistors MN1 and MN4 form a current mirror, so that the current I flowing through the NMOS transistor MN1 is converted intoMN1Comprises the following steps:
IMN1∝fSW (3)
for transistors NPN1, NPN2, NPN3 and NPN4, their respective base and emitter voltages VBE(NPN1)、VBE(NPN2)、VBE(NPN3)And VBE(NPN4)The following relationships exist:
VBE(NPN1)+VBE(NPN2)＝VBE(NPN3)+VBE(NPN4) (4)
thus, for the current I flowing through the transistor NPN4NPN4The following expression is given:
Figure BDA0002486734410000063
according to formula (5), INPN4And on-time TonIn inverse proportion. PMOS transistors MP1 and MP2 form a current mirror, which is turned on for a time TonWhen the voltage is smaller than the required set value, the positive input terminal voltage of the comparator COMP1 in fig. 2 rises, at this time, the comparator COMP1 outputs a high level, and the NMOS transistor MN2 is turned on as a switching transistor. Setting R2/R3 to 1/5, namely, when the NMOS transistor MN2 is turned on, adjusting the preset reference voltage at the positive input terminal of the operational amplifier AMP1 to be one fifth of the initial value, so as to reduce the charge-discharge current of the oscillator inside the circuit, and finally reduce the operating frequency of the circuit, so that the on-time of the power transistor in each period of the circuit meets the delay requirement of the current detection comparator.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (3)

1. A frequency adjusting circuit suitable for a buck-boost converter is characterized by comprising NMOS transistors MN 1-MN 4, PMOS transistors MP 1-MP 4, triodes NPN 1-NPN 4, resistors R1-R4, a diode D1, current sources I1-I4, an operational amplifier AMP1 and a comparator COMP 1; wherein the content of the first and second substances,
the drain terminal of NMOS transistor MN1 is connected to the base terminal of triode NPN1, the gate terminal is connected to the gate terminal of NMOS transistor MN4, the source terminal is connected to the output terminal VOUT-; the drain end of the NMOS tube MN2 is connected with the first end of a resistor R3, the gate end is connected with the output end of a comparator COMP1, and the source end is connected with the first end of a second resistor R2; the drain end of the NMOS tube MN3 is connected with the drain end of the PMOS tube MP3, the gate end is connected with the output end of the operational amplifier AMP1, and the source end is connected with the first end of a resistor R4; the drain terminal of NMOS transistor MN4 is connected to the drain terminal of PMOS transistor MP4, the gate terminal is connected to the drain terminal of PMOS transistor MP4, and the source terminal is connected to the output terminal VOUT-；
PMOS transistor MP1 with drain connected to its gate, gate connected to NPN4 collector, and source connected to input end VIN(ii) a The drain terminal of PMOS transistor MP2 is connected to the first terminal of resistor R1, the gate terminal is connected to the gate terminal of PMOS transistor MP1, the source terminal is connected to input terminal VIN(ii) a PMOS transistor MP3 with drain terminal connected to drain terminal of NMOS transistor MN3, gate terminal connected to gate terminal of PMOS transistor MP4, source terminal connected to input terminal VIN(ii) a PMOS transistor MP4 with drain terminal connected to gate terminal of NMOS transistor MN4, gate terminal connected to gate terminal of PMOS transistor MP3, and source terminal connected to input terminal VIN；
The collector of the triode NPN1 is connected with the negative terminal of the current source I1, the base is connected with the drain terminal of the NMOS transistor MN1, the emitter is connected with the output terminal VOUT-; the collector of the triode NPN2 is connected with the input end VINThe base electrode is connected with the negative end of a current source I2, and the emitter electrode is connected with the drain end of an NMOS tube MN 1; the collector of the triode NPN3 is connected with the input end VINThe base electrode is connected with the base electrode of an NPN triode NPN2, and the emitter electrode is connected with the positive end of a current source I4; the collector of the triode NPN4 is connected with the drain of the PMOS tube MP1, the base is connected with the positive end of the current source I4, and the emitter is connected with the output end VOUT-；
The resistor R1 has a first terminal connected to the drain terminal of the PMOS transistor MP2 and a second terminal connected to the output terminal VOUT-; the resistor R2 has a first terminal connected to the source terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R3 has a first terminal connected to the drain terminal of the NMOS transistor MN2 and a second terminal connected to the output terminal VOUT-; the resistor R4 has a first terminal connected to the source terminal of the NMOS transistor MN3 and a second terminal connected to the output terminal VOUT-；
The positive ends of the current sources I1-I3 are connected with the input end VIN(ii) a The negative end of the current source I1 is connected with the collector of the triode NPN1, the negative end of the current source I2 is connected with the base of the triode NPN2,the negative end of the current source I3 is connected with the first end of a resistor R3; the positive end of the current source I4 is connected with the emitter of the triode NPN3, and the negative end is connected with the output end VOUT-；
The positive end of the diode D1 is connected with the base electrode of the triode NPN2, and the negative end of the diode D1 is connected with the collector electrode of the triode NPN 1; the positive input end of the operational amplifier AMP1 is connected with the drain end of an NMOS tube MN2, the negative input end is connected with the source end of an NMOS tube MN3, and the output end is connected with the gate end of an NMOS tube MN 3; the positive input end of the comparator COMP1 is connected with the drain end of the PMOS tube MP2, the negative input end is connected with the reference voltage VREF1, and the output end is connected with the gate end of the NMOS tube MN 2.
2. The frequency regulation circuit suitable for use in a buck-boost converter as claimed in claim 1, wherein said current source I4 comprises an operational amplifier AMP2, PMOS transistors MP11 and MP12, NMOS transistor MN11 and a resistor R11;
PMOS tube MP11 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN11, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 12; PMOS tube MP12 source end connected with input end VINThe drain end is connected with the grid end of the drain;
the gate of the NMOS transistor MN11 is connected with the output end of the operational amplifier AMP2, and the source end is connected with the output end V through a resistor R11OUT-；
The positive input end of the operational amplifier AMP2 is grounded GND, and the negative input end is connected with the source end of the NMOS tube MN 11.
3. The frequency regulation circuit suitable for use in a buck-boost converter as claimed in claim 1, wherein said current source I1 comprises an operational amplifier AMP3, PMOS transistors MP21 and MP22, NMOS transistor MN21 and a resistor R21;
PMOS tube MP21 source end connected with input end VINThe drain end is connected with the drain end of an NMOS (N-channel metal oxide semiconductor) tube MN21, and the gate end is connected with the gate end of a PMOS (P-channel metal oxide semiconductor) tube MP 22; PMOS tube MP22 source end connected with input end VINThe drain end is connected with the grid end of the drain;
the gate of the NMOS transistor MN21 is connected with the output end of the operational amplifier AMP3, and the source end is connected with the output end V through a resistor R21OUT-；
An operational amplifier AMP3 has a positive input terminal connected to the input terminal VINAnd the negative input end is connected with the source end of an NMOS tube MN 21.
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CN114362513B (en) * 2022-01-12 2023-09-01 四川创安微电子有限公司 Negative boost circuit in chip and charging and discharging method thereof
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