CN112953519A - Self-adaptive dynamic delay circuit - Google Patents

Self-adaptive dynamic delay circuit Download PDF

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CN112953519A
CN112953519A CN202110116651.7A CN202110116651A CN112953519A CN 112953519 A CN112953519 A CN 112953519A CN 202110116651 A CN202110116651 A CN 202110116651A CN 112953519 A CN112953519 A CN 112953519A
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current
switching tube
resistor
electrode
dynamic
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CN112953519B (en
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周泽坤
艾雪
王祖傲
王卓
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

A self-adaptive dynamic delay circuit charges a capacitor by generating a dynamic current, and compares the voltage of the capacitor with a reference voltage to generate the output of the dynamic delay circuit; the dynamic current generation module comprises a bias unit, a differential input stage, an upper limit setting unit, a lower limit setting unit and four current mirrors, wherein the bias unit is used for providing bias; the two input ends of the differential input stage are respectively connected with an input voltage and the output end of the upper and lower limit setting unit and are used for converting the input voltage into differential current; the upper and lower limit setting unit sets an upper current limit by using a third resistor, a fourth resistor and a second NPN type triode and sets a lower current limit by using the third NPN type triode; the four current mirrors are combined with the structure of the differential input stage and the upper and lower LIMIT setting units to control the dynamic current, so that the dynamic current is a fixed value when VIN is more than or equal to VIN _ LIMIT
Figure DDA0002920643760000011
The time-dynamic current is linearly controlled by the input voltage at
Figure DDA0002920643760000012
The time-dependent dynamic current is zero. The invention not only realizes the flexible setting of the upper limit of the dynamic current, but also realizes the linear control of the dynamic current along with the input voltage.

Description

Self-adaptive dynamic delay circuit
Technical Field
The invention belongs to the technical field of power management, and relates to a self-adaptive dynamic delay circuit.
Background
In recent years, the widespread use and the increasing development of portable electronic products have driven the vigorous development of the power supply industry, and at the same time, more stringent requirements are put forward on power supply products. Instead of being small due to the limited load range, single control mode voltage converters have a wide load range and a more efficient hybrid of multiple control modes. In a mixed-mode system, under the condition of a large load, a boundary mode is usually adopted, namely, each working period firstly charges the inductor of the converter, then discharges the inductor until the energy of the inductor is exhausted, and immediately starts the next period to charge the inductor again, so that the working efficiency of the converter is improved; under the condition of a small load, an intermittent mode is usually adopted, namely, each working cycle firstly charges the inductor of the converter, then discharges until the energy of the inductor is exhausted, and then starts the next cycle to charge the inductor again after a period of time and the current cycle is finished so as to reduce the switching loss under light load; under smaller load conditions, a burst-triggered mode is used, i.e., the converter inductor is charged after a plurality of cycles, to further reduce switching losses. The wide use of multi-mode hybrid systems also puts higher demands on the market for accurate switching of different operating modes.
In the existing chip with mixed mode control, a dynamic delay circuit is often used to switch different working modes. The common method for realizing dynamic delay is to use the voltage with load information to perform the enabling control on a plurality of constant currents, namely, the effective constant current numbers are different in different modes, so that the total charging current is different, and the variable delay is generated, and the delay cannot be linearly changed along with the load condition in the mode. Another common delay generation method is to directly convert the voltage with load information into current for charging, thereby generating the change of delay, but this method generates dynamic current, the upper limit of the current is determined by the input voltage with load information, and cannot be flexibly set.
Disclosure of Invention
Aiming at the problems that the first traditional dynamic delay mode can not carry out linear control according to the load and the second traditional dynamic delay mode can not flexibly set the upper current limit, the invention provides a self-adaptive dynamic delay circuit which can flexibly set the upper current limit so as to more accurately and effectively adjust the switching points of different modes in a mixed mode control system; meanwhile, the delay time can be linearly controlled through the input voltage.
The technical scheme of the invention is as follows:
a self-adaptive dynamic delay circuit comprises a comparator, a capacitor and an enabling module, wherein two input ends of the comparator are respectively connected with the voltage on the capacitor and a reference voltage, and the output end of the comparator generates an output signal of the dynamic delay circuit;
the dynamic delay circuit also comprises a dynamic current generation module for generating dynamic current, wherein the enabling module controls the dynamic current to charge the capacitor when an enabling signal is effective, and controls the capacitor to discharge when the enabling signal is ineffective;
the dynamic current generation module comprises a biasing unit, a differential input stage, an upper limit setting unit, a lower limit setting unit, a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, wherein the biasing unit is used for generating a first biasing current, a second biasing current and a third biasing current;
the differential input stage comprises two input ends, wherein the first input end is connected with the input voltage of the dynamic delay circuit, and the second input end is connected with the output end of the upper and lower limit setting unit; the first bias current flows through a branch where two input ends of the differential input stage are located, and provides bias for the differential input stage; the differential input stage is used for converting the input voltage of the dynamic delay circuit into corresponding differential current and flowing out of a branch where a first input end of the differential input stage is located;
the upper and lower limit setting unit comprises a third resistor, a fourth resistor, a second NPN type triode and a third NPN type triode, one end of the third resistor is connected with power voltage, and the other end of the third resistor is connected with a base electrode of the third NPN type triode and one end of the fourth resistor and serves as the output end of the upper and lower limit setting unit; the base electrode and the collector electrode of the second NPN type triode are connected with the other end of the fourth resistor, and the emitting electrode of the second NPN type triode is grounded; an emitter of the third NPN type triode is connected with the input voltage of the dynamic time delay circuit;
the second bias current flows through a collector of a third NPN type triode on one hand and is mirrored to a first branch circuit by the first current mirror on the other hand; the second current mirror is used for mirroring the differential current to a second branch circuit; the third bias current flows through the second branch circuit, and the current obtained by subtracting the third bias current from the current mirrored by the second current mirror in the second branch circuit is mirrored to the first branch circuit by the third current mirror; in the first branch circuit, the current obtained by subtracting the current mirrored by the third current mirror from the current mirrored by the first current mirror is mirrored by the fourth current mirror to obtain the dynamic current;
the upper voltage limit of the input voltage VIN of the dynamic time delay circuit is
Figure BDA0002920643740000021
The lower LIMIT of the voltage is VIN _ LIMIT-VBE3(ii) a The linear change range of the input voltage of the dynamic time delay circuit is delta V;
when VIN is more than or equal to VIN _ LIMIT, the third NPN type triode is cut off, and the second bias current is totally mirrored to the first branch circuit by the first current mirror; meanwhile, if the current mirrored by the second current mirror in the second branch circuit is smaller than the third bias current, a switching tube forming the third current mirror is turned off, and the current mirrored by the third current mirror to the first branch circuit is zero; when the dynamic current is IBIAS2×K1×K4；
When in use
Figure BDA0002920643740000022
When the second branch is started, the second branch is startedThe current mirrored by the second current mirror is greater than the third bias current, so that a switching tube forming the third current mirror works in a saturation region, and the current mirrored by the third current mirror to the first branch is (K)2×IDM-IBIAS3)×K3(ii) a The third NPN type triode is still cut off at the moment, and the dynamic current is [ I ]BIAS2×K1-(K2×IDM-IBIAS3)×K3]×K4；
When in use
Figure BDA0002920643740000031
When it is, let (K)2×IDM-IBIAS3)×K3>IBIAS2×K1When the dynamic current is zero;
wherein R is3And R4The resistance values of the third resistor and the fourth resistor, VCCIs the voltage value of the supply voltage, VBE2And VBE3Base-emitter voltage values, I, of the second NPN transistor and the third NPN transistor, respectivelyDMIs the differential current, IBIAS2And IBIAS3The current values of the second bias current and the third bias current are respectively, and the mirror image ratios of the first current mirror, the second current mirror, the third current mirror and the fourth current mirror are respectively 1: K1、1:K2、1:K3、1:K4。
Specifically, the differential input stage comprises a first switch tube, a second switch tube, a first resistor and a second resistor, wherein the first resistor and the second resistor have the same resistance value, and the first switch tube and the second switch tube are PNP-type triodes or PMOS tubes;
the grid or the base of the first switching tube is used as a first input end of the differential input stage, the source or the emitter of the first switching tube is connected with one end of the first resistor, and the drain or the collector of the first switching tube outputs the differential current;
the grid or the base of the second switching tube is used as a second input end of the differential input stage, the source or the emitter of the second switching tube is connected with one end of the second resistor, and the drain or the collector of the second switching tube is grounded;
the other end of the first resistor and the other end of the second resistor are interconnected and connected to the second bias current.
Specifically, the bias unit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein the grid drain of the first PMOS tube is in short circuit connection with the grids of the second PMOS tube, the third PMOS tube and the fourth PMOS tube and unit bias current, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube and is connected with power supply voltage; and the drain electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube respectively output the first bias current, the second bias current and the third bias current.
Specifically, the second current mirror comprises a third switching tube and a fourth switching tube, and the third switching tube and the fourth switching tube are NPN type triodes or NMOS tubes; bases or grids of the third switching tube and the fourth switching tube are interconnected and connected with a collector or a drain of the third switching tube and the differential current, and emitters or sources of the third switching tube and the fourth switching tube are grounded; the collector or the drain of the fourth switching tube is connected with the drain of the fourth PMOS tube;
the third current mirror comprises a fifth switching tube, a sixth switching tube, a fifth resistor and a sixth resistor, wherein the fifth switching tube and the sixth switching tube are PNP type triodes or PMOS tubes; the base electrode or the grid electrode of the fifth switching tube is connected with the collector electrode or the drain electrode of the fifth switching tube, the base electrode or the grid electrode of the sixth switching tube and the drain electrode of the fourth PMOS tube; an emitter or a source of the fifth switching tube is connected with a power supply voltage through a fifth resistor; an emitter or a source of the sixth switching tube is connected with the power supply voltage through the sixth resistor;
the first current mirror comprises a seventh switching tube and an eighth switching tube, the seventh switching tube and the eighth switching tube are NPN type triodes or NMOS tubes, a grid electrode or a base electrode of the seventh switching tube is interconnected with a drain electrode or a collector electrode thereof and connected with a grid electrode or a base electrode of the eighth switching tube, a drain electrode of the third PMOS tube and a collector electrode of the third NPN type triode, and a source electrode or an emitter electrode thereof is connected with a source electrode or an emitter electrode of the eighth switching tube and grounded;
the fourth current mirror comprises a ninth switching tube and a tenth switching tube, and the ninth switching tube and the tenth switching tube are PNP type triodes or PMOS tubes; the grid electrode or the base electrode of the ninth switching tube is interconnected with the drain electrode or the collector electrode thereof and is connected with the grid electrode or the base electrode of the tenth switching tube, the drain electrode or the collector electrode of the eighth switching tube and the drain electrode or the collector electrode of the sixth switching tube, and the source electrode or the emitter electrode thereof is connected with the source electrode or the emitter electrode of the tenth switching tube and is connected with the power supply voltage; the drain electrode or the collector electrode of the tenth switching tube outputs the dynamic current.
Specifically, the mirror ratio of the third current mirror is 1:1, and the resistance values of the fifth resistor and the sixth resistor are equal; the mirror image ratio of a current mirror formed by the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube is 1:1:1:1, the mirror image ratio of the first current mirror is 1:1, and the mirror image ratio of the second current mirror is 1: 2.
The invention has the beneficial effects that: the dynamic current generation module can flexibly set the upper limit of the dynamic current by adjusting the resistance values of the third resistor R3 and the fourth resistor R4, and simultaneously sets the lower limit of the dynamic current by utilizing the third NPN type triode QN3, thereby realizing the linear control of the dynamic current by the input voltage in the linear change range of the dynamic current; the dynamic current generated by the invention is utilized to charge the fixed capacitor, and the capacitor voltage is compared with the fixed reference voltage to obtain the self-adaptive dynamic delay time, so that the invention is particularly suitable for the state switching of a multi-mode hybrid system, and the accurate and effective adjustment of the switching points of different modes in the mixed-mode control system is realized.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is an equivalent frame diagram of an adaptive dynamic delay circuit according to the present invention.
Fig. 2 is a circuit diagram of an implementation of an adaptive dynamic delay circuit according to an embodiment of the present invention.
FIG. 3 is a diagram of an embodiment of an adaptive dynamic delay circuit according to the present invention, in which the input voltage and the dynamic current VIN-I output by the dynamic current moduleDYNAnd (5) a relationship schematic diagram.
FIG. 4 is a timing diagram of an embodiment of an adaptive dynamic delay circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the adaptive dynamic delay circuit of the present invention includes a comparator a1 and a capacitor CDYNA dynamic current generation module and an enable module, two input ends of a comparator A1 are respectively connected with the voltage V on the capacitorDYNAnd a reference voltage VREFThe output end of the dynamic delay circuit generates an output signal V of the dynamic delay circuitDEN. The dynamic current generation module is used for generating a dynamic current IDYNWhen the enable signal is effective, the enable module controls the dynamic current IDYNIs a capacitor CDYNCharging, when the enable signal is invalid, the enable module controls the capacitor CDYNAnd (4) discharging.
The invention can be applied to realize the state switching of the multi-mode hybrid system, and can also be used in a voltage-controlled oscillator as voltage information to time information. In this embodiment, in order to apply the dynamic delay circuit of the present invention to a multi-mode hybrid controlled voltage converter, for switching the state of the system, the voltage containing the load information of the voltage converter is used as the input voltage VIN of the dynamic delay circuit, the enable signal may be the pulse width modulation signal PWM of the voltage converter, the enable module is implemented by a first NMOS transistor MN1, the gate of the first NMOS transistor MN1 is connected to the pulse width modulation signal PWM of the voltage converter, the source thereof is grounded,the drain electrode of the capacitor is connected with a capacitor CDYNAnd an input of comparator a 1; capacitor CDYNAnd the other end of the same is grounded. Each time the PWM signal is turned down, the dynamic current IDYNTo the capacitor CDYNStarting the charging timing when VDYNUp to VREFComparator A1 output voltage VDENAnd turning over and marking the end of timing. When entering the next period, the PWM signal is turned high, and the capacitor C is coupled through the first NMOS transistor MN1DYNReset by discharging, VDYNThe voltage reset is zero.
The dynamic current generation module is used for generating a dynamic current IDYNThe dynamic current generation module comprises a bias unit, a differential input stage, an upper limit setting unit, a lower limit setting unit, a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, wherein the bias unit is used for generating a first bias current IBIAS1A second bias current IBIAS2And a third bias current IBIAS3. As shown in fig. 2, an implementation structure of the bias unit is shown, in this embodiment, the bias unit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, but the bias unit may also be implemented by other structures, such as other suitable current mirror structures or implemented by replacing the PMOS transistors MP1-MP4 in this embodiment with PNP-type triodes, in this embodiment, the gate-drain of the first PMOS transistor MP1 is shorted and connected to the gates of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4, and the unit bias current IBIASThe source electrodes of the first PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected with the power voltage VCC(ii) a The drains of the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 respectively output a first bias current IBIAS1A second bias current IBIAS2And a third bias current IBIAS3。
The differential input stage comprises two input ends, wherein the first input end is connected with the input voltage VIN of the dynamic delay circuit, and the second input end is connected with the output end of the upper and lower limit setting unit; a first bias current IBIAS1The bias is provided for the differential input stage by flowing through the branch circuits where the two input ends of the differential input stage are located; differential input stage for coupling dynamic delay circuit to outputThe input voltage VIN is converted into a corresponding differential current and flows out of the branch where the first input terminal of the differential input stage is located. As shown in fig. 2, an implementation structure of the differential input stage is provided, and in addition, the differential input stage may also adopt other structures, only the input voltage VIN can be converted into a differential current, in this embodiment, the differential input stage includes a first switch tube, a second switch tube, a first resistor R1, and a second resistor R2, and resistors are added to source ends or emitter ends of the first switch tube and the second switch tube to linearize transconductance, where resistances of the first resistor R1 and the second resistor R2 are equal, and the first switch tube and the second switch tube are PNP triodes or PMOS tubes, for example, in this embodiment, the first switch tube and the second switch tube are a first PNP triode QP1 and a second PNP triode QP2, respectively; a gate or a base of the first switching transistor is used as a first input terminal of the differential input stage and is connected to the input voltage VIN, a source or an emitter of the first switching transistor is connected to one end of the first resistor R1, a drain or a collector of the first switching transistor outputs a differential current, the differential current is mirrored to the second branch by the second current mirror, the second current mirror in this embodiment is composed of a first NPN-type triode QN1 and a fourth NPN-type triode QN4, and the current I flowing through the first NPN-type triode QN1QN1Namely the differential current; the grid or the base of the second switching tube is used as a second input end of the differential input stage, the source or the emitter of the second switching tube is connected with one end of a second resistor R2, and the drain or the collector of the second switching tube is grounded; the other end of the first resistor R1 and the other end of the second resistor R2 are interconnected and connected to a second bias current IBIAS2. The differential input stage converts the variation of the input voltage VIN into a differential current (I in this embodiment)QN1) In addition, the resistance values of the first resistor R1 and the second resistor R2 are equal, so that the dynamic current I is ensuredDYNAnd the input voltage VIN.
The upper and lower limit setting unit comprises a third resistor R3, a fourth resistor R4, a second NPN type triode QN2 and a third NPN type triode QN3, one end of the third resistor R3 is connected with a power supply voltage VCCThe other end of the third NPN type triode QN3 is connected with the base electrode of the third NPN type triode QN3 and one end of the fourth resistor R4, and the other end of the third NPN type triode QN3 is used as the output end of the upper and lower limit setting unit and is connected with the grid electrode or the base electrode of the second switching tube; the base and collector of the second NPN transistor QN2 are connectedThe other end of the four-resistor R4 is grounded; the emitter of the third NPN transistor QN3 is connected to the input voltage VIN of the dynamic delay circuit.
The differential input stage and the upper and lower LIMIT setting unit form a differential amplifier, the upper LIMIT of the dynamic current can be set by the differential amplifier, namely, a reference signal VIN _ LIMIT is generated by a third resistor R3, a fourth resistor R4 and a second NPN type triode QN2 and is used for determining the upper LIMIT of the control range of the input voltage VIN, and VIN _ LIMIT is set by adjusting the resistance values of the third resistor R3 and the fourth resistor R3, so that the input of the differential amplifier is adjustable, and the flexible adjustment of the upper LIMIT of the dynamic current is realized; meanwhile, an emitter of the third NPN type triode QN3 is connected with the input voltage VIN for carrying out lower limit clamping on the input voltage VIN and ensuring that the input voltage VIN is lower than the VIN _ ILMIN by at most one base-emitter voltage V of QN3BE3In some embodiments VBE3About 0.7V. It can be seen that the upper and lower limit setting unit sets the upper limit of the dynamic current by using the third resistor R3, the fourth resistor R4 and the second NPN type transistor QN2, and sets the lower limit of the dynamic current by using the third NPN type transistor QN3, thereby flexibly setting the dynamic current range, and more accurately and effectively adjusting the switching points of different modes in the mixed mode control system.
After the emitter of the first PNP transistor QP1 is connected to the first resistor R1, the transconductance of the first PNP transistor QP1 degrades to the following relationship:
Figure BDA0002920643740000061
when R is1＞＞gQP1In time, there are:
Figure BDA0002920643740000062
wherein g isQP1Is the transconductance, g, of the first PNP transistor QP1 itselfm1Is the equivalent transconductance of the emitter of a first PNP type triode QP1 connected with a first resistor R11Is the resistance value of the first resistor R1.
The transconductance of the first PNP transistor QP1 follows the collector current ICThe change of the voltage is changed, so that a large nonlinear relation between the current and the voltage is generated, the first resistor R1 is not affected by the change of the voltage, and therefore, the linear relation between the current and the voltage can be improved by the first resistor R1. The linear variation range Δ V of VIN can be obtained by combining the bias current (for convenience of illustration, the first bias current I is used in this embodimentBIAS1A second bias current IBIAS2And a third bias current IBIAS3All of which are unit bias currents IBIASCurrent value of), therefore:
ΔV＝R1IBIAS
the upper limit control signal VIN — ILMIN of VIN is determined by the resistor voltage division:
Figure BDA0002920643740000071
wherein R is3And R4Are the resistances, V, of the third resistor R3 and the fourth resistor R4, respectivelyCCIs the voltage value of the supply voltage, VBE2Is the base-emitter voltage value of the second NPN transistor QN 2. The signal VIN _ ILMIN may be adjusted by adjusting R3And R4The upper limit of the current is flexibly controlled, and the value of the input voltage VIN when the current reaches the upper limit can be accurately controlled, so that the switching point can be accurately controlled when the system is switched in the working mode.
The first current mirror, the second current mirror, the third current mirror and the fourth current mirror are used for carrying out linear control on the dynamic current in combination with the differential amplifier, so that the input voltage VIN has different characteristics in different ranges. Second bias current IBIAS2On one hand, the current flows through the collector of the third NPN transistor QN3, and on the other hand, the current is mirrored to the first branch by the first current mirror, as shown in fig. 2, in this embodiment, the first current mirror includes a seventh switch tube and an eighth switch tube, the seventh switch tube and the eighth switch tube are NPN transistors or NMOS tubes, for example, the seventh switch tube is implemented by a first NMOS tube MN1, the eighth switch tube is implemented by a second NMOS tube MN2, and the gate of the first NMOS tube MN1 is shorted and connected to the drain thereofThe grid electrode of the second NMOS transistor MN2, the drain electrode of the third PMOS transistor MP3 and the collector electrode of the third NPN type triode QN3 are connected, and the source electrode of the third NPN type triode QN3 is connected with the source electrode of the second NMOS transistor MN2 and grounded; the branch where the second NMOS transistor MN2 is located is the first branch.
The second current mirror is used for mirroring the differential current to the second branch circuit, and in this embodiment, the second current mirror includes a third switching tube and a fourth switching tube, the third switching tube and the fourth switching tube are NPN-type triodes or NMOS tubes, bases or gates of the third switching tube and the fourth switching tube are interconnected and connected to a collector or a drain of the third switching tube and the differential current, and emitters or sources of the third switching tube and the fourth switching tube are both grounded; the collector or the drain of the fourth switching tube is connected with the drain of the fourth PMOS tube MP 4; in this embodiment, the third switching tube is a first NPN transistor QN1, the fourth switching tube is a fourth NPN transistor QN4, and the fourth NPN transistor QN4 is the second branch.
Third bias current IBIAS3The current flows through the second branch, that is, the drain of the fourth PMOS transistor MP4 is connected to the collector of the fourth NPN transistor QN4, and the third bias current I output by the fourth PMOS transistor MP4BIAS3Flows into the second branch in which the fourth NPN transistor QN4 is located.
The current in the second branch mirrored by the second current mirror (i.e. I)QN4) Minus a third bias current IBIAS3The resulting current is mirrored by the third current mirror to the first branch. In this embodiment, the third current mirror includes a fifth switch tube, a sixth switch tube, a fifth resistor R5, and a sixth resistor R6, where the fifth switch tube and the sixth switch tube are PNP-type triodes or PMOS tubes, for example, in this embodiment, the fifth switch tube is a third PNP-type triode QP3, and the sixth switch tube is a fourth PNP-type triode QP 4; the base electrode or the grid electrode of the fifth switching tube is connected with the collector electrode or the drain electrode of the fifth switching tube, the base electrode or the grid electrode of the sixth switching tube and the drain electrode of the fourth PMOS tube MP 4; the emitter or the source of the fifth switching tube is connected with a power supply voltage V after passing through a fifth resistor R5CC(ii) a The emitter or the source of the sixth switching tube is connected with the power supply voltage V after passing through a sixth resistor R6CC(ii) a So that the third current mirror will IQN4-IBIAS3Mirror the first branch in which the second NMOS transistor MN2 is located.
The current in the first branch mirrored by the first current mirror (i.e., I)MN2) The current obtained by subtracting the current mirrored by the third current mirror is mirrored by the fourth current mirror to obtain the dynamic current IDYN. In this embodiment, the fourth current mirror includes a ninth switch tube and a tenth switch tube, the ninth switch tube and the tenth switch tube are PNP-type triodes or PMOS tubes, for example, the ninth switch tube is implemented by a fifth PMOS tube MP5, the tenth switch tube is implemented by a sixth PMOS tube MP6, a gate-drain short circuit of the fifth PMOS tube MP5 is connected to a gate of the sixth PMOS tube MP6, a drain of the second NMOS tube MN2, and a drain or a collector of the sixth switch tube, and a source thereof is connected to a source of the sixth PMOS tube MP6 and to the power voltage VCC(ii) a The drain of the sixth PMOS transistor MP6 outputs the dynamic current IDYN。
The dynamic current I generated by the inventionDYNCan be controlled linearly by the input voltage VIN and then by means of the dynamic current IDYNTo fixed capacitor CDYNCharging, capacitor voltage VDYNAnd a fixed reference voltage VREFAnd comparing to obtain the self-adaptive dynamic delay time. The dynamic current I at each stage of the present invention is analyzed in detail belowDYNFor convenience of illustration, in this embodiment, the mirror ratio of the current mirror formed by the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is set to 1:1:1:1, so that the first bias current I is set to 1:1:1BIAS1A second bias current IBIAS2And a third bias current IBIAS3All of which are unit bias currents IBIASThe mirror ratio of the third current mirror is set to 1:1, the mirror ratio of the first current mirror is set to 1:1, in which case the mirror ratio of the second current mirror needs to be correspondingly set to 1: 2; in addition, since the mirror ratio of the third current mirror is set to 1:1, the resistances of the fifth resistor R5 and the sixth resistor R6 are set to be equal in this embodiment, so as to ensure that the current mirror relationship between the two transistors QP3 and QP4 constituting the third current mirror is accurate. The proportion of each current mirror can be specifically set according to requirements according to different practical situations as long as the condition that the current mirrored by the second current mirror in the second branch is smaller than the third current mirror when VIN is more than or equal to VIN _ LIMIT is metBias current when
Figure BDA0002920643740000081
Figure BDA0002920643740000082
The current mirrored by the second current mirror in the second branch is greater than the third bias current when
Figure BDA0002920643740000083
Figure BDA0002920643740000084
Season (K)2×IDM-IBIAS3)×K3>IBIAS2×K1That is, the mirror image ratio of the first current mirror, the second current mirror, the third current mirror and the fourth current mirror is 1: K respectively1、1:K2、1:K3、1:K4。
FIG. 3 is a schematic diagram of VIN-I of the dynamic current generation module in this embodimentDYNA curve diagram, which is used for the dynamic current I according to the value range of the input voltage VINDYNAnd the input voltage VIN.
The upper LIMIT of the input voltage VIN of the dynamic delay circuit is VIN _ LIMIT and the lower LIMIT of the input voltage VIN is VIN _ LIMIT-VBE3(ii) a The linear variation range of the input voltage of the dynamic time delay circuit is delta V.
When VIN ≧ VIN _ LIMIT, the third NPN-type transistor QN3 is turned off, so the second bias current IBIAS2All are mirrored to the first branch by the first current mirror; simultaneously, the current mirrored by the second current mirror in the second branch is smaller than the third bias current IBIAS3If the current mirror is in the first branch, the switching tube forming the third current mirror is turned off, and the current mirrored to the first branch by the third current mirror is zero; at this time, the dynamic current IDYNIs IBIAS2×K1×K4。
In view of the structure of FIG. 2, since the first resistor R1 and the second resistor R2 have equal resistance, I is equal toBIAS2＝IBIAS3＝IBIASTherefore, the current flowing through the first NPN transistor QN1 is less than 0.5IBIASThe second current mirror has a mirror ratio of 1:2, so that the current of the fourth NPN transistor QN4 is less than the third bias current IBIAS3＝IBIASTherefore, the voltage at the drain of the fourth PMOS transistor MP4 will rise, pushing the fourth PMOS transistor MP4 into the linear region, and turning off the third PNP transistor QP3 and the fourth PNP transistor QP4 that form the third current mirror. In addition, the third NPN transistor QN3 is also turned off, resulting in the transistor I provided by the third PMOS transistor MP3BIASAll the current flows through the first NMOS transistor MN1, the current of the fifth PMOS transistor MP5 is determined to be I by the second NMOS transistor MN2 in the first current mirror mirroring the current of the first NMOS transistor MN1BIASAt this time, the dynamic current IDYNComprises the following steps:
IDYN＝K4IBIAS
within the value range of the section VIN, the dynamic current IDYNIs not affected by the input voltage VIN.
When in use
Figure BDA0002920643740000091
In the second branch, the current mirrored by the second current mirror is made larger than the third bias current IBIAS3So that the switching tube forming the third current mirror operates in the saturation region, and the current mirrored to the first branch by the third current mirror is (K)2×IDM-IBIAS3)×K3(ii) a At this time, the third NPN transistor QN3 is still turned off, and the dynamic current I is at this timeDYNIs [ I ]BIAS2×K1-(K2×IDM-IBIAS3)×K3]×K4，IDMIs a differential current.
Referring to fig. 2, the current mirrored by the second current mirror is the current I flowing through the fourth NPN transistor QN4QN4The method comprises the following steps:
Figure BDA0002920643740000092
the current of the fourth NPN type triode QN4 is larger than the third bias current IBIAS3＝IBIASThe fourth PMOS transistor MP4 works in saturation region and flows through the third PNP type triodeThe current at QP3 is:
Figure BDA0002920643740000093
the fourth PNP transistor QP4 in the third current mirror mirrors the current of the third PNP transistor QP3, and since the mirror ratio of the third current mirror is 1:1 in this embodiment, the current of the fourth PNP transistor QP4 flows through the same magnitude as the current of the third PNP transistor QP 3. At this time, the third NPN transistor QN3 is still in the off state, and thus the current flowing through the second NMOS transistor MN2 is IBIASSo that the dynamic current at this time is IDYNComprises the following steps:
Figure BDA0002920643740000101
within this range, the dynamic current IDYNVaries linearly with the input voltage VIN.
When in use
Figure BDA0002920643740000102
When it is, let (K)2×IDM-IBIAS3)×K3>IBIAS2×K1At this time, the dynamic current IDYNIs zero.
Referring to fig. 2, the first bias current I provided by the second PMOS transistor MP2BIASAll the current flows through the first NPN transistor QN1, and the current of the fourth NPN transistor QN4 is 2IBIASSince the current of the fourth PMOS transistor MP4 is also IBIASTherefore, the currents of the third PNP transistor QP3 and the fourth PNP transistor QP4 are IBIAS. No matter the third NPN transistor QN3 is in the on state or the off state, the current of the second NMOS transistor MN2 cannot exceed IBIASTherefore, the fifth PMOS transistor MP5 has no current, so the dynamic current I is at this timeDYNComprises the following steps:
IDYN＝0
dynamic current I in this value rangeDYNIs zero and is not affected by the input voltage VIN.
If the input voltage VIN continues to decrease, the input voltage VIN is clamped at the lower limit by the conduction of the third NPN type transistor QN3, and the currents on the first NMOS transistor MN1, the second NMOS transistor MN2, and the fourth PNP type transistor QP4 are reduced to zero, thereby reducing the power consumption of the system.
Dynamic current IDYNSupplying the fixed capacitor C when the pulse width modulation signal PWM of the voltage converter is at a low levelDYNCharging to obtain delay time:
Figure BDA0002920643740000103
the waveform diagram of each key signal is shown in FIG. 4, VDYNIs a capacitor CDYNVoltage of VDENIs a capacitor voltage VDYNAnd a reference voltage VREFOutput voltage through comparator, when VDYN>VREFWhen, VDENIs high. Wherein, in the T0,
Figure BDA0002920643740000104
IDYNwhen the PWM signal is low, the delay time is 0; during the time periods T1 and T2,
Figure BDA0002920643740000105
IDYNlinearly with VIN, the delay time is shorter compared to T1 due to higher VIN at T2; within T3 and T4, VIN is more than or equal to VIN _ LIMIT, IDYNThe maximum is reached, the delay time is the shortest, and the delay time is not changed along with the change of VIN any more.
In summary, the present invention provides a new structure to implement the setting of the upper and lower limits of the dynamic current, so that the upper limit of the current can be flexibly set according to the adjustment resistance value, and in addition, the third NPN type transistor QN3 is used to set the lower limit of the dynamic current, thereby implementing the flexible adjustment of the dynamic current range. The dynamic delay circuit provided by the invention can be used for realizing the state switching of a multi-mode hybrid system, can also be used in a voltage-controlled oscillator as voltage information to time information, and is not limited by a suitable system. The mirror image ratio of each current mirror is not limited as long as the setting condition is met, and in addition, the mirror image ratio of the fourth current mirror can be set randomly according to the required delay time.
Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its broader aspects.

Claims (5)

1. A self-adaptive dynamic delay circuit comprises a comparator, a capacitor and an enabling module, wherein two input ends of the comparator are respectively connected with the voltage on the capacitor and a reference voltage, and the output end of the comparator generates an output signal of the dynamic delay circuit;
the dynamic time delay circuit is characterized by further comprising a dynamic current generation module for generating dynamic current, wherein when an enable signal is effective, the enable module controls the dynamic current to charge the capacitor, and when the enable signal is ineffective, the enable module controls the capacitor to discharge;
the dynamic current generation module comprises a biasing unit, a differential input stage, an upper limit setting unit, a lower limit setting unit, a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, wherein the biasing unit is used for generating a first biasing current, a second biasing current and a third biasing current;
the differential input stage comprises two input ends, wherein the first input end is connected with the input voltage of the dynamic delay circuit, and the second input end is connected with the output end of the upper and lower limit setting unit; the first bias current flows through a branch where two input ends of the differential input stage are located, and provides bias for the differential input stage; the differential input stage is used for converting the input voltage of the dynamic delay circuit into corresponding differential current and flowing out of a branch where a first input end of the differential input stage is located;
the upper and lower limit setting unit comprises a third resistor, a fourth resistor, a second NPN type triode and a third NPN type triode, one end of the third resistor is connected with power voltage, and the other end of the third resistor is connected with a base electrode of the third NPN type triode and one end of the fourth resistor and serves as the output end of the upper and lower limit setting unit; the base electrode and the collector electrode of the second NPN type triode are connected with the other end of the fourth resistor, and the emitting electrode of the second NPN type triode is grounded; an emitter of the third NPN type triode is connected with the input voltage of the dynamic time delay circuit;
the second bias current flows through a collector of a third NPN type triode on one hand and is mirrored to a first branch circuit by the first current mirror on the other hand; the second current mirror is used for mirroring the differential current to a second branch circuit; the third bias current flows through the second branch circuit, and the current obtained by subtracting the third bias current from the current mirrored by the second current mirror in the second branch circuit is mirrored to the first branch circuit by the third current mirror; in the first branch circuit, the current obtained by subtracting the current mirrored by the third current mirror from the current mirrored by the first current mirror is mirrored by the fourth current mirror to obtain the dynamic current;
the upper voltage limit of the input voltage VIN of the dynamic time delay circuit is
Figure FDA0002920643730000011
The lower LIMIT of the voltage is VIN _ LIMIT-VBE3(ii) a The linear change range of the input voltage of the dynamic time delay circuit is delta V;
when VIN is more than or equal to VIN _ LIMIT, the third NPN type triode is cut off, and the second bias current is totally mirrored to the first branch circuit by the first current mirror; meanwhile, if the current mirrored by the second current mirror in the second branch circuit is smaller than the third bias current, a switching tube forming the third current mirror is turned off, and the current mirrored by the third current mirror to the first branch circuit is zero; when the dynamic current is IBIAS2×K1×K4；
When in use
Figure FDA0002920643730000012
When the current mirrored by the second current mirror in the second branch is made larger than the third bias current, the on state of the third current mirror is formedWhen the switch is in a saturation region, the current mirrored to the first branch by the third current mirror is (K)2×IDM-IBIAS3)×K3(ii) a The third NPN type triode is still cut off at the moment, and the dynamic current is [ I ]BIAS2×K1-(K2×IDM-IBIAS3)×K3]×K4；
When in use
Figure FDA0002920643730000021
When it is, let (K)2×IDM-IBIAS3)×K3>IBIAS2×K1When the dynamic current is zero;
wherein R is3And R4The resistance values of the third resistor and the fourth resistor, VCCIs the voltage value of the supply voltage, VBE2And VBE3Base-emitter voltage values, I, of the second NPN transistor and the third NPN transistor, respectivelyDMIs the differential current, IBIAS2And IBIAS3The current values of the second bias current and the third bias current are respectively, and the mirror image ratios of the first current mirror, the second current mirror, the third current mirror and the fourth current mirror are respectively 1: K1、1:K2、1:K3、1:K4。
2. The adaptive dynamic delay circuit of claim 1, wherein the differential input stage comprises a first switch tube, a second switch tube, a first resistor and a second resistor, wherein the first resistor and the second resistor have equal resistance values, and the first switch tube and the second switch tube are PNP transistors or PMOS transistors;
the grid or the base of the first switching tube is used as a first input end of the differential input stage, the source or the emitter of the first switching tube is connected with one end of the first resistor, and the drain or the collector of the first switching tube outputs the differential current;
the grid or the base of the second switching tube is used as a second input end of the differential input stage, the source or the emitter of the second switching tube is connected with one end of the second resistor, and the drain or the collector of the second switching tube is grounded;
the other end of the first resistor and the other end of the second resistor are interconnected and connected to the second bias current.
3. The adaptive dynamic delay circuit according to claim 1 or 2, wherein the bias unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, a gate-drain short circuit of the first PMOS transistor is connected with gates of the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor and a unit bias current, and a source electrode of the first PMOS transistor is connected with source electrodes of the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor and is connected with a power supply voltage; and the drain electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube respectively output the first bias current, the second bias current and the third bias current.
4. The adaptive dynamic delay circuit of claim 3, wherein the second current mirror comprises a third switching tube and a fourth switching tube, and the third switching tube and the fourth switching tube are NPN type triodes or NMOS tubes; bases or grids of the third switching tube and the fourth switching tube are interconnected and connected with a collector or a drain of the third switching tube and the differential current, and emitters or sources of the third switching tube and the fourth switching tube are grounded; the collector or the drain of the fourth switching tube is connected with the drain of the fourth PMOS tube;
the third current mirror comprises a fifth switching tube, a sixth switching tube, a fifth resistor and a sixth resistor, wherein the fifth switching tube and the sixth switching tube are PNP type triodes or PMOS tubes; the base electrode or the grid electrode of the fifth switching tube is connected with the collector electrode or the drain electrode of the fifth switching tube, the base electrode or the grid electrode of the sixth switching tube and the drain electrode of the fourth PMOS tube; an emitter or a source of the fifth switching tube is connected with a power supply voltage through a fifth resistor; an emitter or a source of the sixth switching tube is connected with the power supply voltage through the sixth resistor;
the first current mirror comprises a seventh switching tube and an eighth switching tube, the seventh switching tube and the eighth switching tube are NPN type triodes or NMOS tubes, a grid electrode or a base electrode of the seventh switching tube is interconnected with a drain electrode or a collector electrode thereof and connected with a grid electrode or a base electrode of the eighth switching tube, a drain electrode of the third PMOS tube and a collector electrode of the third NPN type triode, and a source electrode or an emitter electrode thereof is connected with a source electrode or an emitter electrode of the eighth switching tube and grounded;
the fourth current mirror comprises a ninth switching tube and a tenth switching tube, and the ninth switching tube and the tenth switching tube are PNP type triodes or PMOS tubes; the grid electrode or the base electrode of the ninth switching tube is interconnected with the drain electrode or the collector electrode thereof and is connected with the grid electrode or the base electrode of the tenth switching tube, the drain electrode or the collector electrode of the eighth switching tube and the drain electrode or the collector electrode of the sixth switching tube, and the source electrode or the emitter electrode thereof is connected with the source electrode or the emitter electrode of the tenth switching tube and is connected with the power supply voltage; the drain electrode or the collector electrode of the tenth switching tube outputs the dynamic current.
5. The adaptive dynamic delay circuit of claim 4, wherein the third current mirror has a mirror ratio of 1:1, and the fifth resistor and the sixth resistor have equal resistance values; the mirror image ratio of a current mirror formed by the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube is 1:1:1:1, the mirror image ratio of the first current mirror is 1:1, and the mirror image ratio of the second current mirror is 1: 2.
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