CN102609025A - Dynamic current doubling circuit and linear voltage regulator integrated with the circuit - Google Patents

Abstract

The invention discloses a dynamic current doubling circuit and a linear voltage regulator integrated with the circuit. The dynamic current doubling circuit can dynamically regulate the magnitude of the output bias voltage according to the condition of an external output load. The low dropout linear voltage regulator integrated with the dynamic current doubling circuit can couple a leaping voltage to the dynamic current doubling circuit by a capacitor within a very short time when the output voltage leaps, a tail current source current of the differential pairs of a transconductance operational amplifier is increased instantaneously by controlling the magnitude of the bias voltage, the gate voltage of a regulating tube can be regulated rapidly, the problem of low slew rate caused by the slow change of the gate voltage of the regulating tube is solved, and the transconductance of the differential pair tube is increased by the increase of the tail current source current of the differential pairs, thereby increasing bandwidth of LDO (low dropout regulator), and the tail current source current only increases instantaneously without excessive power consumption.

Description

The linear voltage regulator of a kind of dynamic current multiple circuit and integrated this circuit

Technical field

The invention belongs to the power management techniques field, be specifically related to a kind of low pressure difference linear voltage regulator (Low Dropout Regulator, design LDO).

Background technology

Low pressure difference linear voltage regulator LDO has advantages such as cost is low, output noise is little, circuit structure is simple, chip occupying area is little, has become one type of important circuit in the power management chip.

The essence of LDO is to utilize burning voltage that band-gap reference produces and negative feedback control loop to obtain one basically not with the output voltage of environmental change.Existing typical LDO is as shown in Figure 1, specifically comprises: adjustment pipe MP1, error amplifier EA, resistance-feedback network.Its basic functional principle is following: resistance-feedback network produces feedback voltage; Error amplifier amplifies the error small-signal between feedback voltage and the reference voltage; Amplify output through the adjustment pipe again, form negative feedback thus, guaranteed the stable of output voltage; Because error amplifier is clamped to the R1 of error amplifier and the tie point of R2, so output voltage V with reference voltage V ref _OUT=(1+R1/R2) Vref.

For higher load capacity is arranged, the area of general adjustment pipe MP1 is bigger, forms the electric capacity up to tens of pF at the grid of adjustment pipe MP1, and simultaneously in order to reduce the power consumption of LDO, static working current is very little, makes the pendulum rate SR=I of LDO _G/ C _ParVery little, wherein, C _ParBe adjustment tube grid equivalent capacity, I _GBe the grid charging and discharging currents, slower thereby the grid voltage of MP1 pipe changes, cause the drain current of MP1 pipe also to change slowly thereupon, when the output current saltus step, output voltage needs long recovery stabilization time, and can produce high due to voltage spikes; Static working current is very little simultaneously, also can produce very big influence to the bandwidth of LDO, and the differential pair tube mutual conductance in the error amplifier does

And the system bandwidth expression formula is GB=g _M/ C _Par, thereby less static working current can reduce the bandwidth of LDO.To this problem the relevant art scheme is proposed in some documents, such as at document: P.Hazucha, T.Karnik; B.A.Bradley, C.Parsons, D.Finan; And S.Borkar, Area-efficient linear regulator with ultra-fast load regulation, IEEE J.Solid-State Circuits; Vol.40, no.4, among the 933-940 through increasing pendulum rate and the bandwidth that error amplifier tail current source method of current increases LDO; Though improved pendulum rate and bandwidth, the constant caudal electric current of 6mA can produce very large power consumption, and simultaneously traditional LDO is in order to increase the stability of system; The LDO sheet need connect a load capacitance outward, will increase system cost.

Summary of the invention

The objective of the invention is to have proposed a kind of dynamic current multiple circuit in order to solve the problems referred to above that existing low pressure difference linear voltage regulator exists.

Technical scheme of the present invention is: a kind of dynamic current multiple circuit; Comprise; The one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe; The 7th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and first resistance and first electric capacity, concrete annexation is:

The grid of the one PMOS pipe links to each other with the grid of the 2nd PMOS pipe and is connected to second bias voltage; The source electrode of the one PMOS pipe connects outer power voltage; Drain electrode connects an end of drain electrode, grid and first resistance unit of NMOS pipe, and the source electrode of NMOS pipe connects earth potential; The other end of first resistance unit connects the grid of the 2nd NMOS pipe, an end of first electric capacity, the grid of the 3rd NMOS pipe, and the other end of first electric capacity is as the input end of dynamic current multiple circuit; The source electrode of the 2nd NMOS pipe connects earth potential, and drain electrode connects the drain electrode of the 2nd PMOS pipe, the grid of the 5th NMOS pipe, the grid of the 5th PMOS pipe, and the source electrode of the 2nd PMOS pipe connects outer power voltage; The drain electrode of the 3rd NMOS pipe connects the grid of the 3rd PMOS pipe and the grid of drain electrode and the 4th PMOS pipe, and source electrode connects earth potential, and the source electrode of the 3rd PMOS pipe connects outer power voltage; The source electrode of the 4th PMOS pipe connects outer power voltage, the grid of the drain electrode of drain electrode connection the 4th NMOS pipe and the 6th PMOS pipe, the 8th NMOS pipe; Grid phase downlink connection first bias voltage of the 4th NMOS pipe, the 7th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the source electrode of the 4th NMOS pipe connects earth potential; The grid of drain electrode phase downlink connection the 6th NMOS pipe of the 5th PMOS pipe, the 5th NMOS pipe, the source electrode of the 5th PMOS pipe connects outer power voltage, and the source electrode of the 5th NMOS pipe connects earth potential; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 6th NMOS pipe, the 9th NMOS pipe, the 11 NMOS pipe, the 7th PMOS pipe links to each other with grid as the output terminal of dynamic current multiple circuit; The source electrode of the 6th NMOS pipe connects the drain electrode of the 7th NMOS pipe, and the source electrode of the 7th NMOS pipe connects earth potential; The drain electrode of the 6th PMOS pipe links to each other with the drain electrode of the 8th NMOS pipe and is connected to the grid of the 9th NMOS pipe, and the source electrode of the 6th PMOS pipe connects outer power voltage, and the source electrode of the 8th NMOS pipe connects earth potential; The source electrode of the 9th NMOS pipe connects the drain electrode of the tenth NMOS pipe, and the source electrode of the tenth NMOS pipe connects earth potential; The source electrode of the 11 NMOS pipe connects earth potential, and the source electrode of the 7th PMOS pipe connects outer power voltage.

The invention allows for a kind of low pressure difference linear voltage regulator of integrated above-mentioned dynamic current multiple circuit; Also comprise: OTA, adjustment pipe, second resistance unit, the 3rd resistance unit, second electric capacity, the 3rd electric capacity; Wherein, The inverting input of OTA is as reference voltage input; In-phase input end connects an end of second resistance unit, an end of the 3rd resistance unit and an end of second electric capacity, and output terminal is connected to the grid of adjustment pipe, and the other end of the 3rd resistance unit is connected to earth potential; The drain electrode of one end of the other end of the other end of second resistance unit, second electric capacity, the 3rd electric capacity, dynamic current multiple circuit input end and adjustment pipe links to each other as the output terminal of said linear voltage regulator; The other end of the 3rd electric capacity is connected to the miller-compensated point of OTA, and the source electrode of adjustment pipe is connected to outer power voltage; The output terminal of dynamic current multiple circuit provides bias voltage for the OTA tail current source.

Beneficial effect of the present invention: dynamic current multiple circuit of the present invention can be according to the situation of outside output load; The size of dynamic adjustment output offset voltage, thereby can provide dynamic bias voltage to improve the performance of LDO for the amplifier in the linear voltage regulator.The integrated low pressure difference linear voltage regulator of dynamic current multiple circuit of the present invention is compared with existing LDO, owing to adopt the tail current source biasing of dynamic current multiple circuit as OTA; When output voltage generation saltus step; Can leaping voltage be capacitively coupled in the dynamic current multiple circuit in the extremely short time, make the tail current source electric current moment increase of the differential pair of OTA through the size of controlling bias voltage, make the gate voltage of adjusting pipe can access fast and adjust; Overcome greatly because the slow low problem of pendulum rate that causes of adjustment tube grid change in voltage; Thereby improved the pendulum rate of LDO circuit, reduced the overshoot of output voltage and owe, and the increase of the tail current source electric current of differential pair towards phenomenon; Also increased the mutual conductance of differential pair tube; Thereby increased the bandwidth of LDO, and the tail current source electric current is to increase moment, can not consume too much power consumption; Difference linear constant voltage regulator of the present invention has adopted integrated technology on the sheet simultaneously, no longer needs the outer load capacitance of big sheet, has reduced system cost.

Description of drawings

Fig. 1 is the topology diagram of common LDO circuit.

The dynamic current multiple circuit figure that Fig. 2 proposes for the present invention.

The LDO topology diagram that have dynamic current multiple circuit of Fig. 3 for being proposed among the present invention.

Fig. 4 is OTA circuit diagram among the LDO of the present invention's proposition.

Fig. 5 is not for having the simulation waveform comparison diagram of dynamic current multiple circuit LDO and the saltus step of integrated dynamic current multiple circuit LDO load current.

Embodiment

Below in conjunction with accompanying drawing and concrete embodiment the present invention is done further elaboration.

The dynamic current multiple circuit that the present invention proposes is as shown in Figure 2; Comprise; PMOS pipe MP1, MP2, MP3, MP4, MP5, MP6, MP7 and NMOS pipe MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11 and resistance unit R1 and capacitor C 1; Wherein the grid of MP1 links to each other with the grid of MP2 and is connected to the second bias voltage Vb2; The source electrode of MP1 connects outer power voltage Vin, and drain electrode connects the end of drain electrode, grid and the R1 of MN1, and the source electrode of MN1 connects earth potential Vss; The other end of the grid C1 of the grid of the other end connection MN2 of R1, the end of C1, MN3 is as the input end V1 of dynamic current multiple circuit; The source electrode of MN2 pipe connects earth potential Vss, and drain electrode connects the grid of drain electrode, MP5 and the MN5 of MP2, and the source electrode of MP2 connects outer power voltage Vin; The drain electrode of MN3 connects the grid of MP3 and the grid of drain electrode and MN4, and source electrode connects earth potential Vss, and the source electrode of MP3 connects outer power voltage Vin; The source electrode of MP4 pipe connects outer power voltage Vin, the grid of the drain electrode of drain electrode connection MN4 and MP6, MN8; The grid phase downlink connection first bias voltage Vb1 of MN4, MN7, MN10, MN11, the source electrode of MN4 connects earth potential Vss; The grid of the drain electrode phase downlink connection MN6 of MP5, MN5, the source electrode of MP5 connects outer power voltage Vin, and the source electrode of MN5 connects earth potential Vss; The drain electrode of the drain electrode of MN6, the drain electrode of MN9, MN11, the drain electrode of MP7 and grid link to each other as the output terminal V2 of dynamic current multiple circuit, and the source electrode of MN6 connects the drain electrode of MN7, and the source electrode of MN7 connects earth potential Vss; The drain electrode of MP6 links to each other with the drain electrode of MN8 and is connected to the grid of MN9, and the source electrode of MP6 connects outer power voltage Vin, and the source electrode of MN8 connects earth potential Vss; The source electrode of MN9 connects the drain electrode of MN10, and the source electrode of MN10 connects earth potential Vss; The source electrode of MN11 connects earth potential Vss, and the source electrode of MP7 connects outer power voltage Vin.

The invention allows for the low pressure difference linear voltage regulator of integrated above-mentioned current multiplication circuit; As shown in Figure 3, also comprise: OTA OTA, adjustment pipe M0, resistance unit R2, R3, capacitor C 2, wherein; The inverting input of OTA OTA is as reference voltage V ref input end; In-phase input end connects an end, the end of R3 and the end of C2 of R2, and output terminal is connected to the grid of M0, and the other end of R3 is connected to earth potential Vss; The drain electrode of the end of the other end of R2, the other end of C2, C3, the input end of dynamic current multiplication current and M0 links to each other as the output terminal V of LDO _OUT, the other end of C3 is connected to the miller-compensated point of OTA; The output terminal of dynamic current multiple circuit is that OTA tail current source end Bias provides bias voltage.

Here provide a kind of way of realization of OTA OTA, as shown in Figure 4:

Comprise that specifically 5 PMOS pipe MP8, MP9, MP10, MP11, MP12 and 5 NMOS manage MN12, MN13, MN14, MN15, MN16; Wherein, The grid of MP10 is as the tail current source end Bias of OTA; Source electrode connects outer power voltage Vin, and drain electrode links to each other with the source electrode of MP11, MP12; The grid of MP11 is as the inverting input V of said OTA _INN, the drain electrode of MP11 links to each other as the miller-compensated point of this OTA with the grid of the drain and gate of MN13, MN12, the grid of MN14, and the source electrode of MN13 connects earth potential Vss; The grid of MP12 is as the in-phase input end V of said OTA _INP, the grid of the drain electrode of drain electrode connection MN14, the grid of MN15 and drain electrode, MN16, the source electrode of MN15 and MN14 is connected earth potential Vss; The drain electrode of MN12 connects the drain and gate of MP8 and the grid of MP9, and the source electrode of MN12 connects earth potential Vss, and the source electrode of MP8 connects external power source Vin; The drain electrode of MN16 links to each other with the drain electrode of MP9 as the output terminal VOUT1 of OTA, and the source electrode of MN16 connects earth potential Vss, and the source electrode of MP9 connects outer power voltage Vin.

The dynamic current multiple circuit is emphasis of the present invention place; Its effect is to change at load current; During the saltus step of LDO output voltage, can increase the differential-pair tail current source electric current of OTA fast, thereby the adjustment output voltage stabilization is to determined value in the extremely short time; Improve LDO pendulum rate, and increased the bandwidth of LDO.MP2, MN2 form the first current subtraction device in this module; MP4, MN4 form the second current subtraction device, and MP5, MN5 form first phase inverter, and MP6, MN8 form second phase inverter; MN6, MN7 form the overshoot current adjusting module, and MN9, MN10 composition are owed towards current adjusting module.Vb2 is biased in drain current that MP1 produces and Vb1 to be biased in the drain current that produces among the MN4 identical in the design, and for ease of analysis, the drain current of supposing MP1, MN4 is I.

Under stable case; The image current of MP2 is 2I in first current subtraction device; The image current of MN2 is I, and then this moment, the MP2 plumber did at linear zone, and this current subtraction device is output as high level;, the phase inverter anti-phase is added to the grid of MN6 after becoming low level, so the current adjusting module no current output of transistor MN6, MN7 composition.In like manner, also no current output of the current adjusting module that MN9, MN10 form so the dynamic current multiple circuit only provides constant bias voltage to the tail current source of differential amplifier under steady state (SS), makes the quiescent current of LDO very little, and power consumption is also less.

Under astable situation, when output load current diminished suddenly, output voltage had a very high upwards pulse; This pulse voltage is coupled to the grid of transistor MN2, MN3 through capacitor C 1; Thereby make the drain electrode of MN2, MN3 obtain very big electric current, for the current subtraction device that MP4, MN4 form, MP4 will continue to operate in linear zone; Output still is high level; And the current subtraction device output of MP2, MN2 composition becomes low level, opens through making the MN6 pipe after the anti-phase, and then the MP7 drain current becomes I _MP7=I _MN6+ I _MN11Thereby, the electric current of the tail current source MP10 of differential amplifier also can be increased thereupon, the mutual conductance of differential pair tube also can increase so, and the bandwidth GB of this LDO increases, and pendulum rate SR is enhanced.In like manner, when load current became suddenly big, output voltage had very low under-voltage; Then the current adjusting module output current of MP9, MP10 composition makes the tail current source electric current of difference amplifier increase equally, makes the mutual conductance of differential pair tube increase; Improve the bandwidth of LDO, increased the pendulum rate of LDO.

The purposes of OTA OTA in LDO circuit of the present invention is that the voltage Vref of reverse input end is clamped to same input end, and for adjusting the grid of managing M0 suitable WV is provided.Then the LDO output voltage is:

$V_{\mathrm{out}}=(1+\frac{R_2}{R_3})*V_{\mathrm{ref}}$

The grid of NMOS pipe MN14 in this operational amplifier connects the grid of MN13; It is in order to improve the pendulum rate of LDO that drain electrode is connected with the drain electrode of MN15; When the saltus step of LDO output end voltage; MN14 has increased operational amplifier and has exchanged the charge or discharge electric current of homogeneous tube grid, thereby the pendulum rate is enhanced the shunting action of MN15 pipe.

In order to realize the object of the invention, those of ordinary skill in the art is to be appreciated that and can also adopts other similar operational amplifier structure.

Capacitor C 2 is introduced as next zero point and a limit for system in this LDO circuit:

Zero frequency: ${\mathrm{\ω}}_z=\frac{1}{C2*R2}$

Pole frequency: ${\mathrm{\ω}}_p=\frac{1}{C2*(R2//R3)}$

Be inferior limit that produces among the LDO in order to offset the zero point that produces, and to compare R2 less owing to resistance unit R3, thus produce high pole frequency, thus increased the bandwidth of system, improved system stability; C3 is a miller compensation electric capacity, is used for increasing the phase margin of OTA, and this invention is adopted compensation technique in the sheet for integrated LDO on the sheet, therefore no longer needs the outer electric capacity of big sheet; Capacitor C 1 constitutes capacitive coupling with resistance unit R1, guarantees under stable case, and output voltage does not act on the dynamic current multiple circuit, and when output voltage generation saltus step, skip signal is coupled in the current multiplication circuit, thereby to LDO generation effect.

If remove the dynamic current multiple circuit, and the tail current source that adopts constant voltage to be biased to OTA is supplied power, and has just obtained not having the LDO of dynamic current multiple circuit.Size of current did not equate when control did not have the tail current size of dynamic current multiple circuit LDO and has dynamic current multiple circuit LDO stable state; Compare through emulation; Emulation contrast oscillogram when obtaining output current generation increase saltus step as shown in Figure 5 and reducing saltus step; Wherein load current is the square-wave signal of 1mA to 100mA, and the rise-fall delay of this signal is 1us.From Fig. 5, can obtain following table:

Table 1

Thereby can see the superiority of the linear voltage regulator of the integrated dynamic current doubling technology of the present invention; And improve the method for LDO pendulum rate and bandwidth with respect to the tail current source size of current of passing through the increase OTA that document in the background technology is mentioned; Quiescent current was 4uA when the LDO that is designed among the present invention stablized, and on the basis of having improved pendulum rate and bandwidth, had reduced the LDO power consumption.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these teachings disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (3)

1. dynamic current multiple circuit; Comprise; The one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe; The 7th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe and first resistance and first electric capacity, concrete annexation is:

The grid of the one PMOS pipe links to each other with the grid of the 2nd PMOS pipe and is connected to second bias voltage; The source electrode of the one PMOS pipe connects outer power voltage; Drain electrode connects an end of drain electrode, grid and first resistance unit of NMOS pipe, and the source electrode of NMOS pipe connects earth potential; The other end of first resistance unit connects the grid of the 2nd NMOS pipe, an end of first electric capacity, the grid of the 3rd NMOS pipe, and the other end of first electric capacity is as the input end of dynamic current multiple circuit; The source electrode of the 2nd NMOS pipe connects earth potential, and drain electrode connects the drain electrode of the 2nd PMOS pipe, the grid of the 5th NMOS pipe, the grid of the 5th PMOS pipe, and the source electrode of the 2nd PMOS pipe connects outer power voltage; The drain electrode of the 3rd NMOS pipe connects the grid of the 3rd PMOS pipe and the grid of drain electrode and the 4th PMOS pipe, and source electrode connects earth potential, and the source electrode of the 3rd PMOS pipe connects outer power voltage; The source electrode of the 4th PMOS pipe connects outer power voltage, the grid of the drain electrode of drain electrode connection the 4th NMOS pipe and the 6th PMOS pipe, the 8th NMOS pipe; Grid phase downlink connection first bias voltage of the 4th NMOS pipe, the 7th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the source electrode of the 4th NMOS pipe connects earth potential; The grid of drain electrode phase downlink connection the 6th NMOS pipe of the 5th PMOS pipe, the 5th NMOS pipe, the source electrode of the 5th PMOS pipe connects outer power voltage, and the source electrode of the 5th NMOS pipe connects earth potential; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 6th NMOS pipe, the 9th NMOS pipe, the 11 NMOS pipe, the 7th PMOS pipe links to each other with grid as the output terminal of dynamic current multiple circuit; The source electrode of the 6th NMOS pipe connects the drain electrode of the 7th NMOS pipe, and the source electrode of the 7th NMOS pipe connects earth potential; The drain electrode of the 6th PMOS pipe links to each other with the drain electrode of the 8th NMOS pipe and is connected to the grid of the 9th NMOS pipe, and the source electrode of the 6th PMOS pipe connects outer power voltage, and the source electrode of the 8th NMOS pipe connects earth potential; The source electrode of the 9th NMOS pipe connects the drain electrode of the tenth NMOS pipe, and the source electrode of the tenth NMOS pipe connects earth potential; The source electrode of the 11 NMOS pipe connects earth potential, and the source electrode of the 7th PMOS pipe connects outer power voltage.

2. the low pressure difference linear voltage regulator of the described dynamic current multiple circuit of integrated claim 1; It is characterized in that; Also comprise: OTA, adjustment pipe, second resistance unit, the 3rd resistance unit, second electric capacity, the 3rd electric capacity; Wherein, the inverting input of OTA is as reference voltage input, and in-phase input end connects an end of second resistance unit, an end of the 3rd resistance unit and an end of second electric capacity; Output terminal is connected to the grid of adjustment pipe, and the other end of the 3rd resistance unit is connected to earth potential; The drain electrode of one end of the other end of the other end of second resistance unit, second electric capacity, the 3rd electric capacity, dynamic current multiple circuit input end and adjustment pipe links to each other as the output terminal of said linear voltage regulator; The other end of the 3rd electric capacity is connected to the miller-compensated point of OTA, and the source electrode of adjustment pipe is connected to outer power voltage; The output terminal of dynamic current multiple circuit provides bias voltage for the OTA tail current source.

3. low pressure difference linear voltage regulator according to claim 2; It is characterized in that; Said OTA comprises that specifically 5 PMOS pipe MP8, MP9, MP10, MP11, MP12 and 5 NMOS manage MN12, MN13, MN14, MN15, MN16, and wherein, the grid of MP10 is as the tail current source end of OTA; Source electrode connects outer power voltage, and drain electrode links to each other with the source electrode of MP11, MP12; The grid of MP11 is as the inverting input of said operational amplifier, and the drain electrode of MP11 links to each other as the miller-compensated point of said OTA with the grid of the drain and gate of MN13, MN12, the grid of MN14, and the source electrode of MN13 connects earth potential; The grid of MP12 is as the in-phase input end of said OTA, and drain electrode connects grid and the drain electrode of drain electrode, the MN15 of MN14, the grid of MN16, and the source electrode of MN15 and MN14 is connected earth potential; The drain electrode of MN12 connects the drain and gate of MP8 and the grid of MP9, and the source electrode of MN12 connects earth potential, and the source electrode of MP8 connects external power source; The drain electrode of MN16 links to each other as the output terminal of said OTA with the drain electrode of MP9, and the source electrode of MN16 connects earth potential, and the source electrode of MP9 connects outer power voltage.

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