CN106168828A - A kind of power supply circuits with overcurrent protection function - Google Patents

Abstract

The invention belongs to technical field of power management, relate to a kind of power supply circuits with overcurrent protection function.The in-line power circuit of the present invention; compared with existing relevant supply module; use self-powered link form; considerably reduce the use of high voltage transistor; it is effectively saved chip area; the Problem of Failure that chip causes under excessive load is efficiently avoid after the most integrated overload protection; improve the reliability of system; the protection of power supply surplus simultaneously improves the upper punch spike caused to underloading saltus step in heavy duty effectively, improves transient response and is effectively improved the precision of output voltage.

Description

A kind of power supply circuits with overcurrent protection function

Technical field

The invention belongs to technical field of power management, relate to a kind of power supply circuits with overcurrent protection function.

Background technology

The correlation module being required for by chip internal from the power supply of peripheral power supply to chip internal realizes blood pressure lowering Or strengthen the problem such as stability of power supply, generally by low pressure difference linear voltage regulator (Low Dropout under traditional meaning Regulator, LDO) complete.The essence of LDO is the burning voltage utilizing band-gap reference to produce and negative feedback control loop obtains One, the most not with the output voltage of environmental change, can provide again bigger load capacity simultaneously.Existing typical LDO is such as Shown in Fig. 1, specifically include: adjust pipe MP1, error amplifier EA, resistance-feedback network, load resistance RL, load capacitance CL.Its Basic functional principle is: resistance-feedback network produces feedback voltage, and error amplifier is by between feedback voltage and reference voltage Error small-signal is amplified, more adjusted pipe amplifies output, is consequently formed negative feedback, it is ensured that stablizing of output voltage, by In error amplifier by the junction point of clamped for reference voltage V ref R1 and R2 to error amplifier, so output voltage has Vout =(1+R1/R2) Vref.

In the middle of actual chip power supply circuit design, typically directly powered by external input voltage, outside high Pressure power supply needs internal substantial amounts of high tension apparatus, layout design needs consume substantial amounts of area；The most either chip In-line power or LDO single circuit design output voltage are all to have external terminal, and short circuit and overload condition, chip exists inefficacy Risk.

Summary of the invention

The invention aims to solve existing low pressure difference linear voltage regulator deposit when providing stabilized power source to chip Problem, it is achieved that in high precision, the chip internal power supply circuits of self-powered, high reliability.

The technical scheme is that a kind of power supply circuits with overcurrent protection function, including error amplifier block, Bias unit, protection circuit and adjustment output stage；It is defeated that error amplifier block reference voltage V REF and adjustment output stage produce Go out feedback voltage to compare, finally feedback voltage is clamped at reference voltage；Bias unit is powered by external power source VDD, produces Raw bias current is system power supply；Protection circuit is for closing circuit after exceeding limit value at output short-circuit or load Disconnected, it is additionally operable to be switched to underloading that the size of the superfluous limit current-sharing branch current of power supply of short time occurs in load by heavy duty；

Described error amplifier block include the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 13rd NMOS tube MN13, the 14th NMOS tube MN14 and the first PMOS MP1, Second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, a NPN Audion Q1, the 2nd NPN audion Q2, the 3rd NPN audion Q3, the 4th NPN audion Q4, the 5th NPN audion Q5, the 6th NPN audion Q6, the 6th resistance R6, the 7th resistance R7 and electric capacity C1；Wherein, NPN audion Q1 and a 2nd NPN audion Q2 connects feedback voltage V FB of output, the 2nd NPN tri-pole as the input of amplifier unit to pipe, the base stage of a NPN audion Q1 The base stage of pipe Q2 connects reference voltage V REF, and a NPN audion Q1, the emitter stage short circuit of the 2nd NPN audion Q2 are followed by second The drain electrode of NMOS tube MN2 pipe, the source electrode of the second NMOS tube MN2 and the drain electrode of the first NMOS tube MN1 are connected, the first NMOS tube MN1 Source ground, the colelctor electrode of a NPN audion Q1 and the 2nd NPN audion Q2 respectively with the 3rd NPN audion Q3 and The emitter stage of four NPN audion Q4 is connected, and the 3rd NPN audion Q3, the 4th NPN audion Q4 are all base collector short circuit shapes Formula, the base stage of the 3rd NPN audion Q3 and colelctor electrode are connected with the grid of the first PMOS MP1 and drain electrode, the first PMOS MP1 Grid and the 4th PMOS MP4 grid be connected, the first PMOS MP1, the source electrode of the 4th PMOS MP4 connect adjustment output stage Output voltage VRegulated, MP1 and the 4th PMOS MP4 formed fundamental current mirror annexation, the 4th NPN audion Q4 The grid of base collector and the second PMOS MP2 and drain electrode be connected, the grid of the second PMOS MP2 and the 3rd PMOS The grid of MP3 is connected, and the second PMOS MP2, the source electrode of the 3rd PMOS MP3 connect the output voltage adjusting output stage VRegulated, the second PMOS MP2 and the 3rd PMOS MP3 form fundamental current mirror annexation；3rd PMOS MP3 Drain and be connected with the grid of the 9th NMOS tube MN9 and drain electrode, the 9th NMOS tube MN9 with grid and the grid of the tenth NMOS tube MN10 The most connected, the base collector of the 9th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 and the 5th NPN audion Q5 is connected, the The emitter stage of five NPN audion Q5 and the base collector of the 6th NPN audion Q6 are connected, the transmitting of the 6th NPN audion Q6 Pole ground connection, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 form fundamental current mirror annexation, the leakage of the 4th PMOS MP4 Pole is connected with the drain electrode of the tenth NMOS tube MN10, and the first order as error amplifier exports, and connects the 11st NMOS tube MN11 Grid, the source electrode of the source electrode of the 11st NMOS tube MN11 and the 9th NMOS tube MN9, the tenth NMOS tube MN10 is connected, and the 11st The drain electrode of NMOS tube MN11 is connected with the source electrode of the 13rd NMOS tube MN13, and it is defeated that the grid of the 13rd NMOS tube MN13 connects adjustment Go out higher partial pressure VA of the output voltage VRegulated of level, drain terminal connecting resistance the 6th resistance of the 13rd NMOS tube MN13 One end of R6, one end of the 6th resistance another termination capacitor C1 of R6, the grid of another termination the 11st NMOS tube MN11 of electric capacity C1 Pole, resistance the 6th resistance R6 and electric capacity C1 uses as miller compensation, and the drain electrode of the 13rd NMOS tube MN13 meets the 14th NMOS The source electrode of pipe MN14, the 14th NMOS tube MN14 grid leak short circuit the one end with resistance the 7th resistance R7 be connected, resistance the 7th electricity Another termination bias input end that is the 6th PMOS MP6 drain electrode of resistance R7, the grid of the 6th PMOS MP6 connects the 8th of bias unit The grid of PMOS MP8, the source electrode of the 6th PMOS MP6 connects the drain electrode of the 5th PMOS MP5, the grid of the 5th PMOS MP5 Connecing the grid of bias unit the 7th PMOS MP7, the source electrode of the 5th PMOS MP5 meets input voltage VDD, the 7th resistance R7 and The node that six PMOS MP6 are connected is as the adjustment outfan of error amplifier；

Described bias unit includes the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, Eight NMOS tube MN8, the 12nd NMOS tube MN12；12nd NMOS tube MN12 connects input as the enable pipe of offset portion, source electrode Bias current, grid meets enable signal VEN, and drain electrode connects grid and the drain electrode of the tenth PMOS MP10；Tenth PMOS MP10 Grid is connected with the grid of the 9th PMOS MP9 simultaneously, and the 9th PMOS MP9, the source electrode of the tenth PMOS MP10 connect input electricity Pressure VDD, the 9th PMOS MP9, the tenth PMOS MP10 form fundamental current mirror annexation, the drain electrode of the 9th PMOS MP9 The grid of the 8th NMOS tube MN8 is connected with drain electrode, the source electrode of the 8th NMOS tube MN8 and the grid of the 7th NMOS tube MN7 and drain electrode Being connected, the source ground of the 7th NMOS tube MN7, the 7th NMOS tube MN7, the 8th NMOS tube MN8 are as N-type basic cascade electricity The base image branch road of stream mirror, the grid of the 6th NMOS tube MN6 and the grid of the 8th NMOS tube MN8 are connected, the 6th NMOS tube MN6 Source electrode and the drain electrode of the 5th NMOS tube MN5 be connected, the grid of the 5th NMOS tube MN5 and the grid of the 7th NMOS tube MN7 are connected, The source ground of the 5th NMOS tube MN5, the drain electrode of the 6th NMOS tube MN6 is connected with the grid of the 8th PMOS MP8 and drain electrode, the The source electrode of eight PMOS MP8 and the grid of the 7th PMOS MP7 and drain electrode are connected, and the source electrode of the 7th PMOS MP7 connects input electricity Pressure VDD, the 7th PMOS MP7 and the 8th PMOS MP8 form the mirror image branch of basic p-type common-source common-gate current mirror.4th The grid of NMOS tube MN4 and the grid of the 8th NMOS tube MN8 are connected, and the source electrode of the 4th NMOS tube MN4 connects the 3rd NMOS tube MN3 Drain electrode, the grid of the 3rd NMOS tube MN3 and the grid of the 7th NMOS tube MN7 be connected, the source ground of the 3rd NMOS tube MN3, 3rd NMOS tube MN3, the 4th one bias current of NMOS tube MN4 mirror image export from the drain electrode of the 4th NMOS tube MN4；

Described protected location includes diode D1, the 15th NMOS tube MN15, the 16th NMOS tube MN16, the second adjustment pipe NJ2, the 11st PMOS MP11, the 12nd PMOS MP12, the 13rd PMOS MP13, the first PNP triode Q7, second PNP triode Q8, the 3rd PNP triode Q9, the 8th resistance RS1, the 9th resistance RS2；It is defeated that second adjustment pipe NJ2 grid connects adjustment Going out the adjustment tube grid in grade circuit, be also the adjustment output port of error amplifier simultaneously, the second source electrode adjusting pipe NJ2 connects Adjusting the output voltage VRegulated of output stage, second adjusts one end of source electrode connecting resistance the 8th resistance RS1 of pipe NJ2, electricity Hindering another termination input voltage VDD of the 8th resistance RS1, the node that the second adjustment pipe NJ2 and resistance the 8th resistance RS1 connects is same Time be connected with the base stage of the first PNP triode Q7, the emitter stage of the first PNP triode Q7 is connected with input voltage VDD, first The emitter stage of PNP triode Q7 colelctor electrode and the 12nd PMOS MP12 is connected, the grid and second of the 12nd PMOS MP12 The base collector of PNP triode Q8 is connected, the emitter stage of the second PNP triode Q8 and the grid leakage of the 11st PMOS MP11 The most connected, the source electrode of the 11st PMOS MP11 meets input voltage VDD, the base collector of the second PNP triode Q8 simultaneously with The drain electrode of the 4th NMOS tube MN4 of biasing branch road is connected；The drain electrode of the 12nd PMOS MP12 and the 16th NMOS tube MN16 Grid drain electrode is connected, and the grid of the 16th NMOS tube MN16 is connected with the grid of the 15th NMOS tube MN15 simultaneously, and the 15th NMOS tube MN15, the source electrode of the 16th NMOS tube MN16 meet the output voltage VRegulated, the 15th NMOS adjusting output stage Pipe MN15, the 16th NMOS tube MN16 form fundamental current mirror linking relationship, and the drain electrode of the 15th NMOS tube MN15 connects error and puts The drain electrode of afterbody biasing the 6th PMOS MP6 of big device；In the grid of the 13rd PMOS MP13 and error amplifier the The drain electrode of 13 NMOS tube MN13 is connected, and the 13rd PMOS MP13 grounded drain, the 13rd PMOS MP13 source electrode connects the 9th One end of resistance RS2, is connected with the base stage of the 3rd PNP triode Q9 simultaneously, and another termination of the 9th resistance RS2 adjusts output stage Output voltage VRegulated, the emitter stage of the 3rd PNP triode Q9 connect adjust output stage output voltage VRegulated, 3rd PNP triode Q9 colelctor electrode connects the forward end of diode D1, the grid of negative sense termination the 13rd PMOS MP13 of D2；

Described tune output stage includes the first adjustment pipe NJ1, the tenth resistance R0, the first resistance R1, the second resistance R2, the 3rd electricity Resistance R3, the 4th resistance R4, the 5th resistance R5, electric capacity COUT；First drain terminal adjusting pipe NJ1 meets input voltage VDD, and grid connects The node that 6th PMOS MP6 and the 7th resistance R7 are connected, source is as the output voltage VRegulated adjusting output stage；With Time VRegulated and the tenth resistance R0 one end be connected, the tenth resistance R0 another termination output capacitance COUT, as circuit Finally export VOUT, VRegulated by resistance the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, 5th resistance R5 is connected to ground, draws two feedback voltages, and between the second resistance R2 and the 3rd resistance R3, higher dividing potential drop VA connects The grid of internal 13rd NMOS tube MN13 of error amplifier is made clamp and is used, dividing between the 3rd resistance R3 and the 4th resistance R4 Pressure is input to the input of error amplifier, the base stage of audion the oneth NPN audion Q1 as feedback voltage.

Beneficial effects of the present invention is, the in-line power circuit of the present invention, compared with existing relevant supply module, uses Self-powered link form, considerably reduces the use of high voltage transistor, has been effectively saved chip area, the most integrated Efficiently avoid the Problem of Failure that chip causes under excessive load after overload protection, improve the reliability of system, with Time superfluous protection of powering effectively improve the upper punch spike caused in heavy duty to underloading saltus step, improve transient response and have Effect improves the precision of output voltage.

Accompanying drawing explanation

Fig. 1 tradition is in order to produce the circuit structure diagram of internal electric source signal；

The high accuracy that Fig. 2 present invention proposes is integrated with the self-powered circuit topology diagram closing key protection；

Circuit full figure in Fig. 3 present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

The system topology figure of the high accuracy self-starting power supply circuits that the present invention proposes is made up of 5 parts as shown in Figure 2, Error amplifier block, biasing circuit, overload protecting circuit, power supply surplus protection circuit and power adjust output stage；Error The feedback information of output voltage is compared by amplifier with reference voltage, and output adjusts the gate source voltage of power tube, thus reaches to adjust The purpose of joint output；Overcurrent protection is connected between VDD and output voltage VO UT, is turned off by circuit after stream being detected；Supply The superfluous protection of electricity is connected between output voltage and ground, and during being switched to underloading by heavy duty, it is unnecessary that this branch road can equalize Electric current；In addition to adjusting pipe and being powered by VDD with overload protection, error amplifier, power supply surplus protection part are by output voltage Power itself, thus reduce the demand of high tension apparatus.Labor is carried out below in conjunction with Fig. 3 circuit full figure.

Major loop is made up of by means of individual amplifier unit and power output stage, and concrete error amplifier block includes, NMOS tube MN1, MN2, MN9, MN10, MN11, MN13, MN14 and PMOS MP1, MP2, MP3, MP4, MP5, MP6 and NPN audion Q1, Q2, Q3, Q4, Q5, Q6 and resistance R6, R7 and electric capacity C1；Wherein audion Q1 and Q2 as the input of amplifier unit to pipe Q1 Base stage connect feedback voltage V FB of output, the base stage of Q2 connects reference voltage V REF, and the emitter stage short circuit of Q1, Q2 is followed by MN2 pipe Drain electrode, the source electrode of MN2 is connected with the drain electrode of MN1, the source ground of MN1, the colelctor electrode of Q1 and Q2 respectively with the transmitting of Q3 Yu Q4 The most connected, Q3, Q4 are all that base collector short circuit form, the base stage of Q3 and colelctor electrode are connected with grid and the drain electrode of MP1, MP1 Grid be connected with the grid of MP4, the source electrode of MP1, MP4 connect adjustment output voltage VRegulated, MP1 and MP4 formed substantially Current mirror annexation, the base collector of Q4 is connected with the grid of MP2 and drain electrode, and the grid of MP2 is connected with the grid of MP3, The source electrode of MP2, MP3 meets adjustment output voltage VRegulated, MP2 and MP3 and forms fundamental current mirror annexation.The leakage of MP3 Pole is connected with grid and the drain electrode of MN9, and MN9 is connected with the grid of MN10 with grid, the source electrode of MN9, MN10 and the base stage of Q5 Colelctor electrode is connected, and the emitter stage of Q5 is connected with the base collector of Q6, the grounded emitter of Q6, MN9 and MN10 forms electricity substantially Stream mirror annexation, the drain electrode of MP4 is connected with the drain electrode of MN10, and the first order as error amplifier exports, and connects the grid of MN11 Pole, the source electrode of MN11 is connected with the source electrode of MN9, MN10, and the drain electrode of MN11 is connected with the source electrode of MN13, and the grid of MN13 connects adjustment One higher partial pressure VA of output voltage VRegulated, one end of the drain terminal connecting resistance R6 of MN13, another termination capacitor C1 of R6 One end, electric capacity C1 another termination MN11 grid, resistance R6 and electric capacity C1 uses as miller compensation, and the drain electrode of MN13 connects The source electrode of MN14, MN14 grid leak short circuit the one end with resistance R7 be connected, resistance R7 another termination bias input end i.e. MP6 leakage Pole, the grid of MP6 connects the grid of the MP8 of bias unit, and the source electrode of MP6 connects the drain electrode of MP5, and the grid of MP5 meets bias unit MP7 Grid, the source electrode of MP5 connects node that input voltage VDD, R7 and MP6 the be connected adjustment outfan as error amplifier.Merit Rate adjusts output and includes, adjusts pipe NJ1, resistance R0, R1, R2, R3, R4, R5, and electric capacity COUT forms；Adjust the drain terminal of pipe NJ1 Meeting VDD, grid connects the node that MP6 with R7 is connected, and source is as adjusting output voltage VRegulated；Simultaneously VRegulated with One end of R0 is connected, another termination output capacitance COUT of R0, and finally export VOUT, VRegulated as circuit pass through electricity Resistance R1, R2, R3, R4, R5 are connected to ground, draw two feedback voltages, and dividing potential drop VA higher between R2 and R3 connects error amplifier The grid of internal MN13 is made clamp and is used, and the dividing potential drop between R3 and R4 is input to the input of error amplifier as feedback voltage End, the base stage of audion Q1.Then having, final output is determined by feedback voltage division ratio and clamp reference voltage:

$V_{OUT}\≈V_{regulated}=V_{REF}\·\frac{R_1+R_2+R_3+R_4+R_5}{R_4+R_5}$

In the power supply of chip designs, typically requiring one filter capacitor COUT of extension at pin, capacitance is at several μ F The order of magnitude, is adjusting addition R0 between output voltage VRegulated and final output voltage VO UT in the design, is effectively changing Being apt to the exchange stability of circuit, the zero point producing a relatively intermediate frequency carries out compensating the parasitic poles within circuit, R0 Design between precision and stability, there is trade-off relation, R0 the biggest then chip institute adaptable filtered external frequency range more Greatly, the stability of loop is the best, but owing to being powered by VOUT, the upper larger current that will flow through of R0, excessive R0 will There is error between VOUT and design load, choosing of the resistance of R0 meet in the design:

$R0\≤\frac{{\mathrm{\ΔV}}_{error}}{I_{Load,max}}$

Wherein Δ Verror is the maximum deviation that output voltage VO UT can be allowed, ILoad, max are that the maximum of circuit is born Carry electric current.

In error amplifier, the effect of audion Q3, Q4, Q5, Q6 is to prevent in practice owing to the shake of ground wire causes The phenomenon that electric current pours in down a chimney.

The addition of protection circuit is another beneficial effect of the present invention, below from overload protection and power supply surplus protection two Angle is illustrated.

Overload protection is as follows: NJ2 grid connection circuit mainly adjusts tube grid, is also the adjustment output of error amplifier simultaneously Port, the source electrode of NJ2 connects the one end of source electrode connecting resistance RS1 adjusting output voltage VRegulated, NJ2, another of resistance RS1 The node that termination input voltage VDD, NJ2 and resistance RS1 connect is connected with the base stage of audion Q7 simultaneously, the transmitting of audion Q7 Pole is connected with input voltage VDD, and Q7 colelctor electrode is connected with the emitter stage of MP12, the grid of MP12 and the base stage current collection of audion Q8 The most connected, the emitter stage of Q8 is connected with the grid drain electrode of MP11, and the source electrode of MP11 meets input voltage VDD, the base collector of Q8 Drain electrode with the MN4 of biasing branch road simultaneously is connected.The drain electrode of MP12 is connected with the grid drain electrode of MN16, the grid of MN16 simultaneously and The grid of MN15 is connected, and the source electrode of MN15, MN16 meets adjustment output voltage VRegulated, and MN15, MN16 form fundamental current Mirror linking relationship, the drain electrode of MN15 connects the drain electrode of the afterbody biasing MP6 of error amplifier；

By the load current of NJ2 sample circuit, sampling resistor RS1 produces pressure drop, when excessive load makes on RS1 Pressure drop when enough making audion Q7 open, circuit enters the overload protection stage, and overload protecting circuit will be inclined for error amplifier The electric current suction overload protection branch road put, now carries out constant maximum load work, when load current continues to increase, and biasing The electric current on road all flows into overload branch road, and output voltage is gradually reduced, and according to circuit full figure, load current is limited to:

$I_{Load}\≤N\×\frac{V_{BE}}{R_{S1}}$

Wherein N is the ratio of sampling tube NJ2 and the number in parallel of homophony homogeneous tube NJ1, and the size by regulation N and RS1 is permissible Set different load current limits, promote the reliability of circuit.

Power supply surplus protection is as follows: the grid of MP13 is connected with the source electrode of MN13 in error amplifier, MP13 grounded drain, One end of MP13 source electrode connecting resistance RS2, is connected with the base stage of audion Q9 simultaneously, and another termination of resistance RS2 adjusts output electricity The emitter stage of pressure VRegulated, Q9 meets adjustment output voltage VRegulated, and Q9 colelctor electrode meets the forward end of diode D1, D2 Negative sense termination MP13 grid；This branch road effect has two: one is by when heavily switching to light in generation load, due to system ring The adjustment hysteresis quality on road, the offer electric current generally adjusting pipe within a period of time of saltus step continues, now, the electric current of excess electron excess fraction Ground can be flowed into, the output voltage point that surplus of powering when effectively having contained due to load switching causes by RS2, MP13 branch road Peak；If the two is to adjust pipe NJ1 to use depletion mode transistor, then at the adjustment output node electricity of relatively low-load time error amplifier Position, the grid potential i.e. adjusting pipe is generally low than its source potential, overload protection branch road MN15 will source and drain exchange, now RS2, The gate source voltage difference adjusting pipe can be balanced at smaller value by the addition of MP13 branch road effectively, and its process is as follows: adjusts pipe and adopts With depletion mode transistor, if its VSG is relatively big, the VSG of corresponding MP13 is relatively big, and MP13 flows through more electric current, will by this process The VSG adjusting pipe reduces.Audion Q9 and diode D1, as the protection circuit of RS2 and MP13 branch road, prevents electric current on MP13 Excessive, then can obtain the maximum current that Gai Zhi road can equalize is:

$I_{Sinking}\≤\frac{V_{BE}}{R_{S2}}$

Generally this value designs between 1/2～2/3 of maximum load current.

Claims (1)

1. there are power supply circuits for overcurrent protection function, including error amplifier block, bias unit, protection circuit and tune Whole output stage；The output feedback voltage that error amplifier block reference voltage V REF and adjustment output stage produce compares, After feedback voltage is clamped at reference voltage；Bias unit is powered by external power source VDD, and generation bias current is system power supply； Protection circuit, for being turned off by circuit after exceeding limit value at output short-circuit or load, is additionally operable in load by heavy duty Switch to underloading that the size of the superfluous limit current-sharing branch current of power supply of short time occurs；

Described error amplifier block includes the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the tenth NMOS Pipe MN10, the 11st NMOS tube MN11, the 13rd NMOS tube MN13, the 14th NMOS tube MN14 and the first PMOS MP1, second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, NPN tri-pole Pipe Q1, the 2nd NPN audion Q2, the 3rd NPN audion Q3, the 4th NPN audion Q4, the 5th NPN audion Q5, the 6th NPN Audion Q6, the 6th resistance R6, the 7th resistance R7 and electric capacity C1；Wherein, a NPN audion Q1 and the 2nd NPN audion Q2 Input as amplifier unit connects feedback voltage V FB of output, the 2nd NPN audion to pipe, the base stage of a NPN audion Q1 The base stage of Q2 connects reference voltage V REF, and a NPN audion Q1, the emitter stage short circuit of the 2nd NPN audion Q2 are followed by second The drain electrode of NMOS tube MN2 pipe, the source electrode of the second NMOS tube MN2 and the drain electrode of the first NMOS tube MN1 are connected, the first NMOS tube MN1 Source ground, the colelctor electrode of a NPN audion Q1 and the 2nd NPN audion Q2 respectively with the 3rd NPN audion Q3 and The emitter stage of four NPN audion Q4 is connected, and the 3rd NPN audion Q3, the 4th NPN audion Q4 are all base collector short circuit shapes Formula, the base stage of the 3rd NPN audion Q3 and colelctor electrode are connected with the grid of the first PMOS MP1 and drain electrode, the first PMOS MP1 Grid and the 4th PMOS MP4 grid be connected, the first PMOS MP1, the source electrode of the 4th PMOS MP4 connect adjustment output stage Output voltage VRegulated, MP1 and the 4th PMOS MP4 formed fundamental current mirror annexation, the 4th NPN audion Q4 The grid of base collector and the second PMOS MP2 and drain electrode be connected, the grid of the second PMOS MP2 and the 3rd PMOS The grid of MP3 is connected, and the second PMOS MP2, the source electrode of the 3rd PMOS MP3 connect the output voltage adjusting output stage VRegulated, the second PMOS MP2 and the 3rd PMOS MP3 form fundamental current mirror annexation；3rd PMOS MP3 Drain and be connected with the grid of the 9th NMOS tube MN9 and drain electrode, the 9th NMOS tube MN9 with grid and the grid of the tenth NMOS tube MN10 The most connected, the base collector of the 9th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 and the 5th NPN audion Q5 is connected, the The emitter stage of five NPN audion Q5 and the base collector of the 6th NPN audion Q6 are connected, the transmitting of the 6th NPN audion Q6 Pole ground connection, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 form fundamental current mirror annexation, the leakage of the 4th PMOS MP4 Pole is connected with the drain electrode of the tenth NMOS tube MN10, and the first order as error amplifier exports, and connects the 11st NMOS tube MN11 Grid, the source electrode of the source electrode of the 11st NMOS tube MN11 and the 9th NMOS tube MN9, the tenth NMOS tube MN10 is connected, and the 11st The drain electrode of NMOS tube MN11 is connected with the source electrode of the 13rd NMOS tube MN13, and the grid of the 13rd NMOS tube MN13 connects adjustment output One higher partial pressure VA of the output voltage VRegulated of level, drain terminal connecting resistance the 6th resistance R6 of the 13rd NMOS tube MN13 One end, one end of the 6th resistance another termination capacitor C1 of R6, electric capacity C1 another termination the 11st NMOS tube MN11 grid, Resistance the 6th resistance R6 and electric capacity C1 uses as miller compensation, and the drain electrode of the 13rd NMOS tube MN13 connects the 14th NMOS tube The source electrode of MN14, the 14th NMOS tube MN14 grid leak short circuit the one end with resistance the 7th resistance R7 be connected, resistance the 7th resistance Another termination bias input end that is the 6th PMOS MP6 drain electrode of R7, the grid of the 6th PMOS MP6 connects the 8th of bias unit The grid of PMOS MP8, the source electrode of the 6th PMOS MP6 connects the drain electrode of the 5th PMOS MP5, the grid of the 5th PMOS MP5 Connecing the grid of bias unit the 7th PMOS MP7, the source electrode of the 5th PMOS MP5 meets input voltage VDD, the 7th resistance R7 and The node that six PMOS MP6 are connected is as the adjustment outfan of error amplifier；

Described bias unit include the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 12nd NMOS tube MN12；12nd NMOS tube MN12 is as the enable pipe of offset portion, and source electrode connects input partially Putting electric current, grid meets enable signal VEN, and drain electrode connects grid and the drain electrode of the tenth PMOS MP10；The grid of the tenth PMOS MP10 Pole is connected with the grid of the 9th PMOS MP9 simultaneously, and the 9th PMOS MP9, the source electrode of the tenth PMOS MP10 connect input voltage VDD, the 9th PMOS MP9, the tenth PMOS MP10 form fundamental current mirror annexation, the drain electrode of the 9th PMOS MP9 the The grid of eight NMOS tube MN8 is connected with drain electrode, the source electrode of the 8th NMOS tube MN8 and the grid of the 7th NMOS tube MN7 and drain electrode phase Even, the source ground of the 7th NMOS tube MN7, the 7th NMOS tube MN7, the 8th NMOS tube MN8 are as the basic cascode current of N-type The base image branch road of mirror, the grid of the 6th NMOS tube MN6 and the grid of the 8th NMOS tube MN8 are connected, the 6th NMOS tube MN6 The drain electrode of source electrode and the 5th NMOS tube MN5 is connected, and the grid of the 5th NMOS tube MN5 and the grid of the 7th NMOS tube MN7 are connected, the The source ground of five NMOS tube MN5, the drain electrode of the 6th NMOS tube MN6 is connected with the grid of the 8th PMOS MP8 and drain electrode, and the 8th The source electrode of PMOS MP8 and the grid of the 7th PMOS MP7 and drain electrode are connected, and the source electrode of the 7th PMOS MP7 connects input voltage VDD, the 7th PMOS MP7 and the 8th PMOS MP8 form the mirror image branch of basic p-type common-source common-gate current mirror；4th NMOS The grid of pipe MN4 and the grid of the 8th NMOS tube MN8 are connected, and the source electrode of the 4th NMOS tube MN4 connects the leakage of the 3rd NMOS tube MN3 Pole, the grid of the 3rd NMOS tube MN3 and the grid of the 7th NMOS tube MN7 are connected, the source ground of the 3rd NMOS tube MN3, and the 3rd NMOS tube MN3, the 4th one bias current of NMOS tube MN4 mirror image export from the drain electrode of the 4th NMOS tube MN4；

Described protected location include diode D1, the 15th NMOS tube MN15, the 16th NMOS tube MN16, second adjust pipe NJ2, 11st PMOS MP11, the 12nd PMOS MP12, the 13rd PMOS MP13, the first PNP triode Q7, the 2nd PNP tri- Pole pipe Q8, the 3rd PNP triode Q9, the 8th resistance RS1, the 9th resistance RS2；Second adjusts pipe NJ2 grid connects adjustment output stage Adjustment tube grid in circuit, is also the adjustment output port of error amplifier simultaneously, and the second source electrode adjusting pipe NJ2 connects adjustment The output voltage VRegulated of output stage, second adjusts one end of source electrode connecting resistance the 8th resistance RS1 of pipe NJ2, resistance the Another termination input voltage VDD of eight resistance RS1, second adjust the node that connects of pipe NJ2 and resistance the 8th resistance RS1 simultaneously with The base stage of the first PNP triode Q7 is connected, and the emitter stage of the first PNP triode Q7 is connected with input voltage VDD, a PNP tri- The emitter stage of pole pipe Q7 colelctor electrode and the 12nd PMOS MP12 is connected, the grid of the 12nd PMOS MP12 and the 2nd PNP tri- The base collector of pole pipe Q8 is connected, the emitter stage of the second PNP triode Q8 and the grid drain electrode phase of the 11st PMOS MP11 Even, the source electrode of the 11st PMOS MP11 meets input voltage VDD, the base collector of the second PNP triode Q8 simultaneously with biasing The drain electrode of the 4th NMOS tube MN4 of branch road is connected；The drain electrode of the 12nd PMOS MP12 and the grid of the 16th NMOS tube MN16 Drain electrode is connected, and the grid of the 16th NMOS tube MN16 is connected with the grid of the 15th NMOS tube MN15 simultaneously, the 15th NMOS tube MN15, the source electrode of the 16th NMOS tube MN16 connect adjust output stage output voltage VRegulated, the 15th NMOS tube MN15, 16th NMOS tube MN16 forms fundamental current mirror linking relationship, and the drain electrode of the 15th NMOS tube MN15 connects error amplifier The drain electrode of rear stage biasing the 6th PMOS MP6；The grid of the 13rd PMOS MP13 and the 13rd NMOS in error amplifier The source electrode of pipe MN13 is connected, and the 13rd PMOS MP13 grounded drain, the 13rd PMOS MP13 source electrode connects the 9th resistance RS2's One end, is connected with the base stage of the 3rd PNP triode Q9 simultaneously, and another termination of the 9th resistance RS2 adjusts the output electricity of output stage Pressure VRegulated, the emitter stage of the 3rd PNP triode Q9 meets the output voltage VRegulated, the 3rd PNP adjusting output stage Audion Q9 colelctor electrode connects the forward end of diode D1, the grid of negative sense termination the 13rd PMOS MP13 of D2；

Described tune output stage includes the first adjustment pipe NJ1, the tenth resistance R0, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, electric capacity COUT；First drain terminal adjusting pipe NJ1 meets input voltage VDD, and grid connects the 6th The node that PMOS MP6 and the 7th resistance R7 are connected, source is as the output voltage VRegulated adjusting output stage；Simultaneously One end of VRegulated and the tenth resistance R0 is connected, and another termination output capacitance COUT of the tenth resistance R0, as circuit Finally export VOUT, VRegulated by resistance the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the Five resistance R5 are connected to ground, draw two feedback voltages, and between the second resistance R2 and the 3rd resistance R3, higher dividing potential drop VA connects by mistake The grid of internal 13rd NMOS tube MN13 of difference amplifier is made clamp and is used, the dividing potential drop between the 3rd resistance R3 and the 4th resistance R4 The input of error amplifier, the base stage of audion the oneth NPN audion Q1 it is input to as feedback voltage.