CN106168828B - A kind of power supply circuit with overcurrent protection function - Google Patents
A kind of power supply circuit with overcurrent protection function Download PDFInfo
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- CN106168828B CN106168828B CN201610710668.4A CN201610710668A CN106168828B CN 106168828 B CN106168828 B CN 106168828B CN 201610710668 A CN201610710668 A CN 201610710668A CN 106168828 B CN106168828 B CN 106168828B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
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Abstract
The invention belongs to technical field of power management, it is related to a kind of power supply circuit with overcurrent protection function.In-line power circuit of the invention; compared with existing related power supply module; using confession electrical links form; considerably reduce the use of high voltage transistor; it has been effectively saved chip area; on the other hand the Problem of Failure that chip causes under excessive load is efficiently avoid after integrated overload protection; improve the reliability of system; superfluous protection of powering simultaneously effectively improve heavy duty cause to underloading saltus step on rush spike, improve transient response and effectively improve the precision of output voltage.
Description
Technical field
The invention belongs to technical field of power management, it is related to a kind of power supply circuit with overcurrent protection function.
Background technology
Power supply from peripheral power supply to chip internal is required for realizing step-down by the correlation module of chip internal
Or enhancing power supply stability the problems such as, under traditional meaning generally by low pressure difference linear voltage regulator (Low Dropout
Regulator, LDO) complete.The essence of LDO is obtained using the burning voltage and negative feedback control loop of band-gap reference generation
One substantially not with the output voltage of environmental change, while larger load capacity can be provided again.Existing typical LDO is such as
Shown in Fig. 1, specifically include：Adjustment pipe MP1, error amplifier EA, resistance-feedback network, load resistance RL, load capacitance CL.Its
Basic functional principle is：Resistance-feedback network produces feedback voltage, and error amplifier is by between feedback voltage and reference voltage
Error small-signal is amplified, then adjusted pipe amplifies output, is consequently formed negative-feedback, it is ensured that the stabilization of output voltage, by
In error amplifier by the tie point of the clamped R1 and R2 to error amplifier of reference voltage V ref, so output voltage has Vout
=(1+R1/R2) Vref.
In the middle of actual chip power supply circuit design, typically directly powered by external input voltage, it is on the one hand outside high
Pressure power supply needs internal substantial amounts of high tension apparatus, needs to consume substantial amounts of area in layout design；On the other hand either chip
In-line power or LDO single circuits design output voltage are have external terminal, and short-circuit and overload condition, chip has failure
Risk.
The content of the invention
Deposited when stabilized power source is provided to chip the invention aims to solve existing low pressure difference linear voltage regulator
Problem, realize the chip internal power supply circuit of high accuracy, self-powered, high reliability.
The technical scheme is that：A kind of power supply circuit with overcurrent protection function, including error amplifier block,
Bias unit, protection circuit and adjustment output stage；Error amplifier block produces reference voltage V REF and adjustment output stage
Output feedback voltage is compared, finally by feedback voltage clamp in reference voltage；Bias unit is powered by input voltage VDD,
Generation bias current is system power supply；Protection circuit is used to close circuit after output short-circuit or load exceed limit value
It is disconnected, it is additionally operable to the size that branch current is flowed in the limitation when load switches to underloading the power supply surplus of short time occur by heavy duty；
The error amplifier block includes the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the tenth
NMOS tube MN10, the 11st NMOS tube MN11, the 13rd NMOS tube MN13, the 14th NMOS tube MN14 and the first PMOS MP1,
Second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, a NPN
Triode Q1, the second NPN triode Q2, the 3rd NPN triode Q3, the 4th NPN triode Q4, the 5th NPN triode Q5, the 6th
NPN triode Q6, the 6th resistance R6, the 7th resistance R7 and electric capacity C1；Wherein, the first NPN triode Q1 and the second NPN triode
As the input of error amplifier block to pipe, the base stage of the first NPN triode Q1 meets the feedback voltage V FB of output, second to Q2
The base stage of NPN triode Q2 meets reference voltage V REF, after the first NPN triode Q1, the emitter stage short circuit of the second NPN triode Q2
The drain electrode of the second NMOS tube MN2 pipes is connect, the source electrode of the second NMOS tube MN2 is connected with the drain electrode of the first NMOS tube MN1, a NMOS
The colelctor electrode of the source ground of pipe MN1, the first NPN triode Q1 and the second NPN triode Q2 respectively with the 3rd NPN triode Q3
Emitter stage with the 4th NPN triode Q4 is connected, and the 3rd NPN triode Q3, the 4th NPN triode Q4 are that base collector is short
Form is connect, the base stage and colelctor electrode of the 3rd NPN triode Q3 are connected with the grid of the first PMOS MP1 and drain electrode, a PMOS
The grid of pipe MP1 is connected with the grid of the 4th PMOS MP4, and the first PMOS MP1, the source electrode of the 4th PMOS MP4 connect adjustment
The output voltage VRegulated, MP1 of output stage and the 4th PMOS MP4 form fundamental current mirror annexation, the 4th NPN tri-
The base collector of pole pipe Q4 is connected with the grid of the second PMOS MP2 and drain electrode, the grid and the 3rd of the second PMOS MP2
The grid of PMOS MP3 is connected, and the second PMOS MP2, the source electrode of the 3rd PMOS MP3 connect the output voltage of adjustment output stage
VRegulated, the second PMOS MP2 and the 3rd PMOS MP3 form fundamental current mirror annexation；3rd PMOS MP3's
Drain electrode and the grid of the 9th NMOS tube MN9 and draining is connected, the grid of the 9th NMOS tube MN9 and the grid of the tenth NMOS tube MN10
It is connected, the 9th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 are connected with the base collector of the 5th NPN triode Q5, the 5th
The emitter stage of NPN triode Q5 is connected with the base collector of the 6th NPN triode Q6, the emitter stage of the 6th NPN triode Q6
Ground connection, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 form fundamental current mirror annexation, the drain electrode of the 4th PMOS MP4
Drain electrode with the tenth NMOS tube MN10 is connected, and is exported as the first order of error amplifier, connects the grid of the 11st NMOS tube MN11
Pole, the source electrode of the 11st NMOS tube MN11 is connected with the source electrode of the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS
The drain electrode of pipe MN11 is connected with the source electrode of the 13rd NMOS tube MN13, and the grid of the 13rd NMOS tube MN13 connects adjustment output stage
One the one of the resistance R6 of drain terminal connecting resistance the 6th of higher partial pressure VA, the 13rd NMOS tube MN13 of output voltage VRegulated
End, one end of another termination capacitor C1 of the 6th resistance R6, the grid of the NMOS tube MN11 of another termination the 11st of electric capacity C1, resistance
6th resistance R6 and electric capacity C1 are used as miller compensation, and the drain electrode of the 13rd NMOS tube MN13 connects the 14th NMOS tube MN14's
Source electrode, the 14th NMOS tube MN14 grid leaks short circuit is simultaneously connected with one end of the resistance R7 of resistance the 7th, and resistance R7 is another for resistance the 7th
Termination bias input end is the 6th PMOS MP6 drain electrodes, and the grid of the 6th PMOS MP6 connects the 8th PMOS of bias unit
The grid of MP8, the source electrode of the 6th PMOS MP6 connects the drain electrode of the 5th PMOS MP5, and the grid of the 5th PMOS MP5 connects biasing
The grid of the PMOS MP7 of unit the 7th, the source electrode of the 5th PMOS MP5 meets input voltage VDD, the 7th resistance R7 and the 6th PMOS
Pipe MP6 connected node as error amplifier adjustment output end；
The bias unit includes the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS
MP10, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7,
Eight NMOS tube MN8, the 12nd NMOS tube MN12；12nd NMOS tube MN12 as bias unit enable pipe, source electrode connects input
Bias current, grid meets enable signal VEN, and drain electrode connects grid and the drain electrode of the tenth PMOS MP10；Tenth PMOS MP10's
Grid is connected with the grid of the 9th PMOS MP9 simultaneously, and the 9th PMOS MP9, the source electrode of the tenth PMOS MP10 connect input electricity
Pressure VDD, the 9th PMOS MP9, the tenth PMOS MP10 form fundamental current mirror annexation, the drain electrode of the 9th PMOS MP9
It is connected with drain electrode with the grid of the 8th NMOS tube MN8, grid and the leakage of the source electrode and the 7th NMOS tube MN7 of the 8th NMOS tube MN8
Extremely it is connected, the source ground of the 7th NMOS tube MN7, the 7th NMOS tube MN7, the 8th NMOS tube MN8 are used as the basic cascade of N-type
The base image branch road of current mirror, the grid of the 6th NMOS tube MN6 and the grid of the 8th NMOS tube MN8 are connected, the 6th NMOS tube
The source electrode of MN6 is connected with the drain electrode of the 5th NMOS tube MN5, the grid of the 5th NMOS tube MN5 and the grid phase of the 7th NMOS tube MN7
Even, the source ground of the 5th NMOS tube MN5, the drain electrode of the 6th NMOS tube MN6 and the grid of the 8th PMOS MP8 and drain electrode phase
Even, the source electrode of the 8th PMOS MP8 is connected with the grid of the 7th PMOS MP7 and drain electrode, and the source electrode of the 7th PMOS MP7 connects defeated
Enter voltage VDD, the 7th PMOS MP7 and the 8th PMOS MP8 and form the mirror image branch of basic p-type common-source common-gate current mirror.The
The grid of four NMOS tube MN4 is connected with the grid of the 8th NMOS tube MN8, and the source electrode of the 4th NMOS tube MN4 meets the 3rd NMOS tube MN3
Drain electrode, the grid of the 3rd NMOS tube MN3 is connected with the grid of the 7th NMOS tube MN7, the source ground of the 3rd NMOS tube MN3,
3rd NMOS tube MN3, the 4th one bias current of NMOS tube MN4 mirror images are exported from the drain electrode of the 4th NMOS tube MN4；
The protection circuit includes diode D1, the 15th NMOS tube MN15, the 16th NMOS tube MN16, the second adjustment pipe
NJ2, the 11st PMOS MP11, the 12nd PMOS MP12, the 13rd PMOS MP13, the first PNP triode Q7, second
PNP triode Q8, the 3rd PNP triode Q9, the 8th resistance RS1, the 9th resistance RS2；It is defeated that second adjustment pipe NJ2 grids connect adjustment
The adjustment tube grid gone out in grade circuit, while being also the adjustment output port of error amplifier, the drain electrode of the second adjustment pipe NJ2 connects
Adjust the output voltage VRegulated of output stage, one end of the resistance RS1 of source electrode connecting resistance the 8th of the second adjustment pipe NJ2, electricity
Another termination input voltage VDD of the 8th resistance RS1 is hindered, the node that the second adjustment pipe NJ2 and resistance RS1 of resistance the 8th connects is same
When be connected with the base stage of the first PNP triode Q7, the emitter stage of the first PNP triode Q7 is connected with input voltage VDD, first
PNP triode Q7 colelctor electrodes are connected with the source electrode of the 12nd PMOS MP12, the grid and the 2nd PNP of the 12nd PMOS MP12
The base collector of triode Q8 is connected, the emitter stage of the second PNP triode Q8 and the grid drain electrode of the 11st PMOS MP11
Be connected, the source electrode of the 11st PMOS MP11 meets input voltage VDD, the base collector of the second PNP triode Q8 simultaneously with it is inclined
The drain electrode for putting the 4th NMOS tube MN4 of unit is connected；The drain electrode of the 12nd PMOS MP12 and the grid of the 16th NMOS tube MN16
Pole drain electrode is connected, and the grid of the 16th NMOS tube MN16 is connected with the grid of the 15th NMOS tube MN15 simultaneously, the 15th NMOS
Pipe MN15, the source electrode of the 16th NMOS tube MN16 meet the output voltage VRegulated of adjustment output stage, the 15th NMOS tube
MN15, the 16th NMOS tube MN16 form fundamental current mirror annexation, and the drain electrode of the 15th NMOS tube MN15 connects error amplification
The afterbody of device biases the drain electrode of the 6th PMOS MP6；The tenth in the grid and error amplifier of the 13rd PMOS MP13
The drain electrode of three NMOS tube MN13 is connected, the 13rd PMOS MP13 grounded drains, and the 13rd PMOS MP13 source electrodes connect the 9th electricity
One end of RS2 is hindered, while be connected with the base stage of the 3rd PNP triode Q9, another termination adjustment output stage of the 9th resistance RS2
The emitter stage of output voltage VRegulated, the 3rd PNP triode Q9 meets the output voltage VRegulated of adjustment output stage, the
Three PNP triode Q9 colelctor electrodes connect the forward end of diode D1, and the negative sense of D1 terminates the grid of the 13rd PMOS MP13；
The adjustment output stage includes the first adjustment pipe NJ1, the tenth resistance R0, first resistor R1, second resistance R2, the 3rd
Resistance R3, the 4th resistance R4, the 5th resistance R5, electric capacity COUT；The drain terminal of the first adjustment pipe NJ1 meets input voltage VDD, and grid connects
The node that 6th PMOS MP6 is connected with the 7th resistance R7, source is used as the output voltage VRegulated for adjusting output stage；Together
When VRegulated be connected with one end of the tenth resistance R0, another termination output capacitance COUT of the tenth resistance R0, as circuit
Final output VOUT, VRegulated by resistance first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4,
5th resistance R5 is connected to ground, draws two feedback voltages, and partial pressure VA higher between second resistance R2 and 3rd resistor R3 connects
The grid of the 13rd NMOS tube MN13 of error amplifier inside is used as clamp, dividing between 3rd resistor R3 and the 4th resistance R4
Pressure is input to the input i.e. base stage of the NPN triode Q1 of triode first of error amplifier as feedback voltage.
Beneficial effects of the present invention are that in-line power circuit of the invention compared with existing related power supply module, is used
Confession electrical links form, considerably reduces the use of high voltage transistor, has been effectively saved chip area, on the other hand integrated
The Problem of Failure that chip causes under excessive load is efficiently avoid after overload protection, the reliability of system is improved, together
When power superfluous protection effectively improve heavy duty cause to underloading saltus step on rush spike, improve transient response and have
Effect improves the precision of output voltage.
Brief description of the drawings
Fig. 1 tradition is used to produce the circuit structure diagram of internal electric source signal；
Fig. 2 high accuracy proposed by the present invention is integrated with the self-powered circuit topology diagram of crucial protection；
Circuit full figure in Fig. 3 present invention.
Specific embodiment
Below in conjunction with the accompanying drawings, technical scheme is described in detail：
The system topology figure of high accuracy self-starting power supply circuit proposed by the present invention is made up of 5 parts as shown in Figure 2,
Error amplifier block, biasing circuit, overload protecting circuit, the superfluous protection circuit of power supply and power adjustment output stage；Error
Amplifier compares the feedback information of output voltage with reference voltage, the gate source voltage of output adjustment power tube, so as to reach tune
Save the purpose of output；Overcurrent protection is connected between VDD and output voltage VO UT, is detected and turn off circuit after excessively stream；For
Electric superfluous protection is connected between output voltage and ground, and during underloading is switched to by heavy duty, the branch road can be balanced unnecessary
Electric current；In addition to adjustment pipe is powered with overload protection by VDD, error amplifier, the superfluous protection part of power supply are by output voltage
Power itself, so as to reduce the demand of high tension apparatus.Labor is carried out with reference to Fig. 3 circuits full figure.
Major loop is made up of amplifier unit and power output stage by means of individual, and specific error amplifier block includes, NMOS tube
MN1, MN2, MN9, MN10, MN11, MN13, MN14 and PMOS MP1, MP2, MP3, MP4, MP5, MP6 and NPN triode Q1,
Q2, Q3, Q4, Q5, Q6 and resistance R6, R7 and electric capacity C1；Wherein triode Q1 and Q2 is as the input of amplifier unit to pipe Q1
The base stage of the base stage feedback voltage V FB, Q2 that connect output connect the emitter stage short circuit of reference voltage V REF, Q1, Q2 and be followed by MN2 pipes
Drain electrode, the source electrode of MN2 is connected with the drain electrode of MN1, the source ground of MN1, the colelctor electrode of Q1 and Q2 respectively with the transmitting of Q3 and Q4
Extremely it is connected, Q3, Q4 are base collector short circuit forms, the base stage and colelctor electrode of Q3 are connected with the grid of MP1 and drain electrode, MP1
Grid be connected with the grid of MP4, the source electrode of MP1, MP4 meets adjustment output voltage VRegulated, MP1 and MP4 and is formed substantially
Current mirror annexation, the base collector of Q4 is connected with the grid of MP2 and drain electrode, and the grid of MP2 is connected with the grid of MP3,
The source electrode of MP2, MP3 meets adjustment output voltage VRegulated, MP2 and MP3 and forms fundamental current mirror annexation.The leakage of MP3
The grid of pole and MN9 and drain electrode are connected, MN9's and grid be connected with the grid of MN10, the source electrode of MN9, MN10 and the base stage of Q5
Colelctor electrode is connected, and the emitter stage of Q5 is connected with the base collector of Q6, the grounded emitter of Q6, and MN9 and MN10 forms electricity substantially
Stream mirror annexation, the drain electrode of MP4 is connected with the drain electrode of MN10, is exported as the first order of error amplifier, connects the grid of MN11
Pole, the source electrode of MN11 is connected with the source electrode of MN9, MN10, and the drain electrode of MN11 is connected with the source electrode of MN13, and the grid of MN13 connects adjustment
One end of the drain terminal connecting resistance R6 of one the higher partial pressure VA, MN13 of output voltage VRegulated, another termination capacitor C1 of R6
One end, the grid of another termination MN11 of electric capacity C1, resistance R6 and electric capacity C1 use as miller compensation, and the drain electrode of MN13 connects
The source electrode of MN14, MN14 grid leaks short circuit is simultaneously connected with one end of resistance R7, and another termination bias input ends of resistance R7 are MP6 leakages
Pole, the grid of MP6 connects the grid of the MP8 of bias unit, and the source electrode of MP6 connects the drain electrode of MP5, and the grid of MP5 meets bias unit MP7
Grid, the source electrode of MP5 connects the adjustment output end of node that input voltage VDD, R7 and MP6 be connected as error amplifier.Work(
Rate adjustment is exported and including adjustment pipe NJ1, resistance R0, R1, R2, R3, R4, R5, electric capacity COUT compositions；The drain terminal of adjustment pipe NJ1
VDD is met, grid connects the node that MP6 is connected with R7, and source is used as adjustment output voltage VRegulated；Simultaneously VRegulated with
One end of R0 is connected, another termination output capacitance COUT of R0, as the final output VOUT, VRegulated of circuit by electricity
Resistance R1, R2, R3, R4, R5 are connected to ground, draw two feedback voltages, and partial pressure VA higher between R2 and R3 connects error amplifier
The grid of internal MN13 is used as clamp, and the partial pressure between R3 and R4 is input to the input of error amplifier as feedback voltage
End, the base stage of triode Q1.Then have, final output is determined by feedback voltage division ratio and clamp reference voltage：
Generally need to hang a filter capacitor COUT in the power supply design of chip, at pin, capacitance is in several μ F
The order of magnitude, R0 is added in the design between output voltage VRegulated and final output voltage VOUT is adjusted, and is effectively changed
It has been apt to the exchange stability of circuit, has produced a zero point compared with intermediate frequency compensated to the parasitic poles inside circuit, R0
Design there is trade-off relation between precision and stability, the R0 more adaptable filtered external frequency ranges of big then chip institute are more
Greatly, the stability of loop is better, but due to being powered by VOUT, R0 is upper will to flow through larger current, and excessive R0 will
There is error between VOUT and design load, the selection of the resistance of R0 in the design should meet：
Wherein Δ Verror is the maximum deviation that output voltage VO UT can allow, ILoad, max bear for the maximum of circuit
Carry electric current.
The effect of triode Q3, Q4, Q5, Q6 is to prevent in practice because the shake of ground wire causes in error amplifier
The phenomenon that electric current pours in down a chimney.
The addition of protection circuit is another beneficial effect of the invention, below from overload protection and the superfluous protection two of power supply
Angle is illustrated.
Overload protection is as follows：NJ2 grids connect circuit and mainly adjust tube grid, while being also the adjustment output of error amplifier
Port, the source electrode of NJ2 connects one end of the source electrode connecting resistance RS1 of adjustment output voltage VRegulated, NJ2, and resistance RS1's is another
The node that termination input voltage VDD, NJ2 and resistance RS1 connect is connected with the base stage of triode Q7 simultaneously, the transmitting of triode Q7
Pole is connected with input voltage VDD, and Q7 colelctor electrodes are connected with the emitter stage of MP12, the grid of MP12 and the base stage current collection of triode Q8
Extremely it is connected, the emitter stage of Q8 is connected with the grid drain electrode of MP11, and the source electrode of MP11 connects the base collector of input voltage VDD, Q8
Drain electrode with the MN4 of biasing branch road simultaneously is connected.The drain electrode of MP12 is connected with the grid drain electrode of MN16, the grid of MN16 simultaneously and
The grid of MN15 is connected, and the source electrode of MN15, MN16 meets adjustment output voltage VRegulated, MN15, MN16 and forms fundamental current
Mirror linking relationship, the drain electrode of MN15 connects the drain electrode of the afterbody biasing MP6 of error amplifier；
By the load current of NJ2 sample circuits, pressure drop is produced on sampling resistor RS1, when excessive load so that on RS1
Pressure drop make enough triode Q7 open when, circuit enter the overload protection stage, overload protecting circuit will be inclined for error amplifier
The electric current put is pumped into overload protection branch road, now carries out constant maximum load work, when load current continues to increase, biasing branch
The electric current on road all flows into overload branch road, and output voltage is gradually reduced, and according to circuit full figure, load current is limited to：
Wherein N is the ratio between sampling pipe NJ2 and number in parallel of homophony homogeneous tube NJ1, can be with by the size for adjusting N and RS1
The different load current limit of setting, lifts the reliability of circuit.
The superfluous protection of power supply is as follows：The grid of MP13 is connected with the source electrode of MN13 in error amplifier, MP13 grounded drains,
One end of MP13 source electrode connecting resistances RS2, while be connected with the base stage of triode Q9, another termination adjustment output electricity of resistance RS2
The emitter stage of pressure VRegulated, Q9 connects the forward end that adjustment output voltage VRegulated, Q9 colelctor electrode meets diode D1, D2
Negative sense terminate MP13 grid；Branch road effect has two：One is when there is load by switching to light again, due to system ring
The adjustment hysteresis quality on road, the offer electric current that pipe is adjusted generally within a period of time of saltus step continues, now, the electric current of excess electron excess fraction
Ground can be flowed into by RS2, MP13 branch road, output voltage point caused by surplus of being powered when effectively having contained due to load switching
Peak；If the two is adjustment, pipe NJ1 uses depletion mode transistor, in the adjustment output node electricity compared with low-load time error amplifier
Position, that is, adjust pipe grid potential it is generally lower than its source potential, overload protection branch road MN15 will source and drain exchange, now RS2,
The gate source voltage difference that can will effectively adjust pipe that adds of MP13 branch roads is balanced in smaller value, and its process is as follows：Adjustment pipe is adopted
With depletion mode transistor, if its VSG is larger, the VSG of correspondence MP13 is larger, and MP13 flows through more electric currents, will by the process
The VSG for adjusting pipe reduces.Triode Q9 and diode D1 prevents electric current on MP13 as the protection circuit of RS2 and MP13 branch roads
Excessive, then can obtain Gai Zhi roads can maximum current be in a balanced way：
Usual value design is between the 1/2~2/3 of maximum load current.
Claims (1)
1. a kind of power supply circuit with overcurrent protection function, including error amplifier block, bias unit, protection circuit and tune
Whole output stage；Be compared for the output feedback voltage that reference voltage V REF and adjustment output stage are produced by error amplifier block,
Finally by feedback voltage clamp in reference voltage；Bias unit is powered by input voltage VDD, produces bias current to be supplied for system
Electricity；Protection circuit is used to turn off circuit after output short-circuit or load exceed limit value, is additionally operable in load by weight
The size of branch current is flowed in limitation when load switches to underloading the power supply surplus of short time occur；
The error amplifier block includes the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the tenth NMOS
Pipe MN10, the 11st NMOS tube MN11, the 13rd NMOS tube MN13, the 14th NMOS tube MN14 and the first PMOS MP1, second
PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the poles of a NPN tri-
Pipe Q1, the second NPN triode Q2, the 3rd NPN triode Q3, the 4th NPN triode Q4, the 5th NPN triode Q5, the 6th NPN
Triode Q6, the 6th resistance R6, the 7th resistance R7 and electric capacity C1；Wherein, the first NPN triode Q1 and the second NPN triode Q2
As the input of error amplifier block to pipe, the base stage of the first NPN triode Q1 meets the feedback voltage V FB, the 2nd NPN of output
The base stage of triode Q2 meets reference voltage V REF, and the first NPN triode Q1, the emitter stage short circuit of the second NPN triode Q2 are followed by
The drain electrode of the second NMOS tube MN2 pipes, the source electrode of the second NMOS tube MN2 is connected with the drain electrode of the first NMOS tube MN1, the first NMOS tube
The colelctor electrode of the source ground of MN1, the first NPN triode Q1 and the second NPN triode Q2 respectively with the 3rd NPN triode Q3 with
The emitter stage of the 4th NPN triode Q4 is connected, and the 3rd NPN triode Q3, the 4th NPN triode Q4 are base collector short circuits
Form, the base stage and colelctor electrode of the 3rd NPN triode Q3 are connected with the grid of the first PMOS MP1 and drain electrode, the first PMOS
The grid of MP1 is connected with the grid of the 4th PMOS MP4, and it is defeated that the first PMOS MP1, the source electrode of the 4th PMOS MP4 connect adjustment
The output voltage VRegulated, MP1 and the 4th PMOS MP4 for going out level form fundamental current mirror annexation, the poles of the 4th NPN tri-
The base collector of pipe Q4 is connected with the grid of the second PMOS MP2 and drain electrode, the grid and the 3rd PMOS of the second PMOS MP2
The grid of pipe MP3 is connected, and the second PMOS MP2, the source electrode of the 3rd PMOS MP3 connect the output voltage of adjustment output stage
VRegulated, the second PMOS MP2 and the 3rd PMOS MP3 form fundamental current mirror annexation；3rd PMOS MP3's
Drain electrode and the grid of the 9th NMOS tube MN9 and draining is connected, the grid of the 9th NMOS tube MN9 and the grid of the tenth NMOS tube MN10
It is connected, the 9th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 are connected with the base collector of the 5th NPN triode Q5, the 5th
The emitter stage of NPN triode Q5 is connected with the base collector of the 6th NPN triode Q6, the emitter stage of the 6th NPN triode Q6
Ground connection, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 form fundamental current mirror annexation, the drain electrode of the 4th PMOS MP4
Drain electrode with the tenth NMOS tube MN10 is connected, and is exported as the first order of error amplifier, connects the grid of the 11st NMOS tube MN11
Pole, the source electrode of the 11st NMOS tube MN11 is connected with the source electrode of the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS
The drain electrode of pipe MN11 is connected with the source electrode of the 13rd NMOS tube MN13, and the grid of the 13rd NMOS tube MN13 connects adjustment output stage
One the one of the resistance R6 of drain terminal connecting resistance the 6th of higher partial pressure VA, the 13rd NMOS tube MN13 of output voltage VRegulated
End, one end of another termination capacitor C1 of the 6th resistance R6, the grid of the NMOS tube MN11 of another termination the 11st of electric capacity C1, resistance
6th resistance R6 and electric capacity C1 are used as miller compensation, and the drain electrode of the 13rd NMOS tube MN13 connects the 14th NMOS tube MN14's
Source electrode, the 14th NMOS tube MN14 grid leaks short circuit is simultaneously connected with one end of the resistance R7 of resistance the 7th, and resistance R7 is another for resistance the 7th
Termination bias input end is the 6th PMOS MP6 drain electrodes, and the grid of the 6th PMOS MP6 connects the 8th PMOS of bias unit
The grid of MP8, the source electrode of the 6th PMOS MP6 connects the drain electrode of the 5th PMOS MP5, and the grid of the 5th PMOS MP5 connects biasing
The grid of the PMOS MP7 of unit the 7th, the source electrode of the 5th PMOS MP5 meets input voltage VDD, the 7th resistance R7 and the 6th PMOS
Pipe MP6 connected node as error amplifier adjustment output end；
The bias unit include the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10,
3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th
NMOS tube MN8, the 12nd NMOS tube MN12；12nd NMOS tube MN12 as bias unit enable pipe, it is inclined that source electrode connects input
Electric current is put, grid meets enable signal VEN, and drain electrode connects grid and the drain electrode of the tenth PMOS MP10；The grid of the tenth PMOS MP10
Pole is connected with the grid of the 9th PMOS MP9 simultaneously, and the 9th PMOS MP9, the source electrode of the tenth PMOS MP10 connect input voltage
VDD, the 9th PMOS MP9, the tenth PMOS MP10 formed fundamental current mirror annexation, the drain electrode of the 9th PMOS MP9 and
The grid of the 8th NMOS tube MN8 is connected with drain electrode, grid and the drain electrode of the source electrode and the 7th NMOS tube MN7 of the 8th NMOS tube MN8
It is connected, the source ground of the 7th NMOS tube MN7, the 7th NMOS tube MN7, the 8th NMOS tube MN8 are used as the basic cascade electricity of N-type
The base image branch road of mirror is flowed, the grid of the 6th NMOS tube MN6 and the grid of the 8th NMOS tube MN8 are connected, the 6th NMOS tube MN6
Source electrode be connected with the drain electrode of the 5th NMOS tube MN5, the grid of the 5th NMOS tube MN5 and the grid of the 7th NMOS tube MN7 are connected,
The source ground of the 5th NMOS tube MN5, the drain electrode of the 6th NMOS tube MN6 is connected with the grid of the 8th PMOS MP8 and drain electrode, the
The source electrode of eight PMOS MP8 is connected with the grid of the 7th PMOS MP7 and drain electrode, and the source electrode of the 7th PMOS MP7 connects input electricity
Pressure VDD, the 7th PMOS MP7 and the 8th PMOS MP8 form the mirror image branch of basic p-type common-source common-gate current mirror；4th
The grid of NMOS tube MN4 is connected with the grid of the 8th NMOS tube MN8, and the source electrode of the 4th NMOS tube MN4 connects the 3rd NMOS tube MN3's
Drain electrode, the grid of the 3rd NMOS tube MN3 is connected with the grid of the 7th NMOS tube MN7, the source ground of the 3rd NMOS tube MN3, the
Three NMOS tube MN3, the 4th one bias current of NMOS tube MN4 mirror images are exported from the drain electrode of the 4th NMOS tube MN4；
The protection circuit include diode D1, the 15th NMOS tube MN15, the 16th NMOS tube MN16, the second adjustment pipe NJ2,
11st PMOS MP11, the 12nd PMOS MP12, the 13rd PMOS MP13, the first PNP triode Q7, the 2nd PNP tri-
Pole pipe Q8, the 3rd PNP triode Q9, the 8th resistance RS1, the 9th resistance RS2；Second adjustment pipe NJ2 grids connect adjustment output stage
Adjustment tube grid in circuit, while being also the adjustment output port of error amplifier, the drain electrode of the second adjustment pipe NJ2 connects adjustment
The output voltage VRegulated of output stage, one end of the resistance RS1 of source electrode connecting resistance the 8th of the second adjustment pipe NJ2, resistance the
Another termination input voltage VDD of eight resistance RS1, the second nodes for connecting of the adjustment pipe NJ2 and resistance RS1 of resistance the 8th simultaneously with
The base stage of the first PNP triode Q7 is connected, and the emitter stage of the first PNP triode Q7 is connected with input voltage VDD, a PNP tri-
Pole pipe Q7 colelctor electrodes are connected with the source electrode of the 12nd PMOS MP12, the grid of the 12nd PMOS MP12 and the poles of the 2nd PNP tri-
The base collector of pipe Q8 is connected, and the emitter stage of the second PNP triode Q8 is connected with the grid drain electrode of the 11st PMOS MP11,
The source electrode of the 11st PMOS MP11 meets input voltage VDD, and the base collector of the second PNP triode Q8 is while and bias unit
The 4th NMOS tube MN4 drain electrode be connected；The drain electrode of the 12nd PMOS MP12 and the grid drain electrode of the 16th NMOS tube MN16
It is connected, the grid of the 16th NMOS tube MN16 is connected with the grid of the 15th NMOS tube MN15 simultaneously, the 15th NMOS tube MN15,
The source electrode of the 16th NMOS tube MN16 meets the output voltage VRegulated of adjustment output stage, the 15th NMOS tube MN15, the tenth
Six NMOS tube MN16 form fundamental current mirror annexation, and the drain electrode of the 15th NMOS tube MN15 connects last of error amplifier
The drain electrode of the 6th PMOS MP6 of level biasing；The grid of the 13rd PMOS MP13 and the 13rd NMOS tube in error amplifier
The source electrode of MN13 is connected, and the 13rd PMOS MP13 grounded drains, the 13rd PMOS MP13 source electrodes connect the one of the 9th resistance RS2
End, while being connected with the base stage of the 3rd PNP triode Q9, another termination of the 9th resistance RS2 adjusts the output voltage of output stage
The emitter stage of VRegulated, the 3rd PNP triode Q9 meets the output voltage VRegulated, the 3rd PNP tri- of adjustment output stage
Pole pipe Q9 colelctor electrodes connect the forward end of diode D1, and the negative sense of D1 terminates the grid of the 13rd PMOS MP13；
The adjustment output stage includes the first adjustment pipe NJ1, the tenth resistance R0, first resistor R1, second resistance R2,3rd resistor
R3, the 4th resistance R4, the 5th resistance R5, electric capacity COUT；The drain terminal of the first adjustment pipe NJ1 meets input voltage VDD, and grid connects the 6th
The node that PMOS MP6 is connected with the 7th resistance R7, source is used as the output voltage VRegulated for adjusting output stage；Simultaneously
VRegulated is connected with one end of the tenth resistance R0, another termination output capacitance COUT of the tenth resistance R0, as circuit
Final output VOUT, VRegulated are by resistance first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the
Five resistance R5 are connected to ground, draw two feedback voltages, and partial pressure VA higher between second resistance R2 and 3rd resistor R3 connects mistake
The grid of difference amplifier the 13rd NMOS tube MN13 of inside is used as clamp, the partial pressure between 3rd resistor R3 and the 4th resistance R4
The input i.e. base stage of the NPN triode Q1 of triode first of error amplifier is input to as feedback voltage.
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| CN201610710668.4A CN106168828B (en) | 2016-08-23 | 2016-08-23 | A kind of power supply circuit with overcurrent protection function |
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| CN201610710668.4A CN106168828B (en) | 2016-08-23 | 2016-08-23 | A kind of power supply circuit with overcurrent protection function |
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| CN106168828B true CN106168828B (en) | 2017-06-06 |
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| CN106774600A (en) * | 2016-12-23 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of low power consumption power supply circuit |
| CN106532629B (en) * | 2016-12-29 | 2018-09-21 | 电子科技大学 | A kind of current foldback circuit with self-recovering function |
| CN108267663B (en) * | 2016-12-30 | 2021-04-27 | 技嘉科技股份有限公司 | Detection device |
| CN106936304B (en) * | 2017-05-16 | 2018-11-23 | 电子科技大学 | A kind of current limit circuit suitable for push-pull output stage LDO |
| US10345838B1 (en) * | 2018-06-26 | 2019-07-09 | Nxp B.V. | Voltage regulation circuits with separately activated control loops |
| CN110764410B (en) * | 2019-10-25 | 2022-05-24 | 深圳欧创芯半导体有限公司 | Method for accelerating transient response of negative feedback control system |
| CN113495592A (en) * | 2020-04-07 | 2021-10-12 | 炬芯科技股份有限公司 | Short-circuit current protection device and method for LDO (low dropout regulator), and LDO |
| CN114510109A (en) * | 2022-01-13 | 2022-05-17 | 电子科技大学 | high-PSR (power supply rejection) fast transient response dual-mode LDO (low dropout regulator) without off-chip capacitor |
| CN114879803B (en) * | 2022-05-24 | 2023-07-04 | 西安微电子技术研究所 | Current-limiting protection circuit structure of LDO |
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| CN100550560C (en) * | 2004-07-15 | 2009-10-14 | 罗姆股份有限公司 | Current foldback circuit |
| US20070206338A1 (en) * | 2004-08-10 | 2007-09-06 | Tsutomu Ishino | Circuit Protection Method, Protection Circuit and Power Supply Device Using The Protection Circuit |
| CN100589058C (en) * | 2007-12-27 | 2010-02-10 | 北京中星微电子有限公司 | Current limitation circuit as well as voltage regulator and DC-DC converter including the same |
| JP2013097505A (en) * | 2011-10-31 | 2013-05-20 | Mitsumi Electric Co Ltd | Semiconductor integrated circuit for regulator |
| EP2846213B1 (en) * | 2013-09-05 | 2023-05-03 | Renesas Design Germany GmbH | Method and apparatus for limiting startup inrush current for low dropout regulator |
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