CN103838290A - Ldo circuit - Google Patents
Ldo circuit Download PDFInfo
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- CN103838290A CN103838290A CN201410098539.5A CN201410098539A CN103838290A CN 103838290 A CN103838290 A CN 103838290A CN 201410098539 A CN201410098539 A CN 201410098539A CN 103838290 A CN103838290 A CN 103838290A
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- pass transistor
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Abstract
The invention provides an LDO circuit which comprises a differential amplifier, a power output PMOS transistor, a current mirror unit, a first resistor and a second resistor. The first resistor and the second resistor are connected between the drain electrode of the power output PMOS transistor and the ground in series, and the positive input end of the differential amplifier is connected between the first resistor and the second resistor. The current mirror unit and the grid electrode of the power output PMOS transistor are connected with the output end of the differential amplifier, and the drain electrode of the power output PMOS transistor is connected with the first resistor. A second node is formed between the drain electrode of the power output PMOS transistor and the first resistor, and the second node is connected with the output end of the LDO circuit. In the LDO circuit, the current mirror unit is added so that a zero point of the LDO circuit can move in the same direction with the second node when a load current varies. Thus, the stability of the LDO circuit is ensured.
Description
Technical field
The present invention relates to linear voltage regulator technical field, particularly a kind of LDO circuit.
Background technology
Low pressure difference linear voltage regulator (low dropout regulator, be called for short LDO) can produce output voltage through overregulating for chip provides power supply, is widely used at present in system level chip (System-on-a-Chip is called for short SoC).Whether low pressure difference linear voltage regulator needs shunt capacitance can be divided into plain edition LDO circuit according to it and without capacitor type LDO circuit (capacitorless LDO), plain edition LDO circuit generally needs one or two shunt capacitance, and does not generally need shunt capacitance without capacitor type LDO circuit.Traditional capacitorless LDO circuit is generally made up of parts such as differential amplifier, power MOS pipe and resistance, and the backfeed loop of differential amplifier, power MOS pipe and resistance composition is used for keeping the stable of output voltage.Common, traditional LDO circuit also comprises that compensating resistance for realizing compensation effect and Miller capacitance are to guarantee the stability of LDO circuit.
Please refer to Fig. 1, the structural representation of the capacitorless LDO circuit that it is prior art.As shown in Figure 1, existing capacitorless LDO circuit 100 comprises differential amplifier A1, power stage PMOS transistor mp10, compensating resistance Rm1, Miller capacitance Cc1, feedback resistance R11 and R12, wherein, the source electrode of power stage PMOS transistor mp10 is connected with supply voltage VDD, feedback resistance R11 and R12 are connected between the drain electrode and ground of power stage PMOS transistor mp10, the reverse input end of differential amplifier A1 connects a reference voltage Vref, the positive input of differential amplifier A1 is connected between described feedback resistance R11 and R12, the output terminal of differential amplifier A1 is connected with the grid of power stage PMOS transistor mp10, the drain electrode of power stage PMOS transistor mp10 is connected with feedback resistance R11, between the drain electrode of power stage PMOS transistor mp10 and feedback resistance R11, form Section Point N2, compensating resistance Rm1 and Miller capacitance Cc1 connect and mutually between described Section Point N2 and the output terminal of differential amplifier A1, described Section Point N2 is connected with the output terminal of described capacitorless LDO circuit 100, the output terminal of described capacitorless LDO circuit 100 is connected with a load capacitance CL1 conventionally, the electric capacity of described load capacitance CL1 can be 0.
The principle of work of described capacitorless LDO circuit 100 is as follows: capacitorless LDO circuit 100 produces output voltage VO UT according to the reference voltage Vref of input, after output voltage VO UT process feedback resistance R11 and R12 dividing potential drop, for the input end in the same way of differential amplifier A1 provides feedback voltage V FB, the expression formula of described feedback voltage V FB is:
VFB=〔R12÷（R11＋R12）〕×VOUT；
Differential amplifier A1 with reference to voltage Vref and feedback voltage V FB compare obtain difference DELTA V and will difference DELTA V amplify after obtain Δ Vmax, Δ Vmax is for driving the grid of described power stage PMOS transistor mp10, thereby change by the electric current of power stage PMOS transistor mp10, make reference voltage Vref and feedback voltage V FB approximately equal, and then make the magnitude of voltage of output voltage VO UT be tending towards constant.
But described capacitorless LDO circuit 100 is found in application process, its unstable properties in the time that larger variation occurs load current.The reason of described capacitorless LDO circuit 100 unstable properties is, described in when larger variation occurs load current, the zero point of capacitorless LDO circuit 100 is along with the second limit moves in the same way, because could not well follow the tracks of the variation of the second limit zero point, therefore cause harmful effect for stability.As shown in Figure 1, to move to high frequency by low frequency when larger variation the second limit occurs load current, and not change the zero point of described capacitorless LDO circuit 100, therefore, the second limit is made the bad stability of described capacitorless LDO circuit 100 to high frequency by low-frequency transfer.If load current sharply increased in moment, the directly normal work of the described capacitorless LDO circuit 100 of impact.
Therefore the problem that, how to solve existing capacitorless LDO circuit unstable properties in the time that load current sharply changes becomes the current technical matters of needing solution badly.
Summary of the invention
The object of the present invention is to provide a kind of LDO circuit, to solve the problem of existing capacitorless LDO circuit unstable properties in the time that load current sharply changes.
For solving the problems of the technologies described above, the invention provides a kind of LDO circuit, described LDO circuit comprises: differential amplifier, power stage PMOS transistor, current lens unit, the first resistance and the second resistance;
Wherein, described the first resistance and the second resistance are series between the transistorized drain electrode of described power stage PMOS and ground, the positive input of described differential amplifier is connected between described the first resistance and the second resistance, described current lens unit is all connected with the output terminal of described differential amplifier with the transistorized grid of described power stage PMOS, the transistorized drain electrode of described power stage PMOS is connected with described the first resistance, between the transistorized drain electrode of described power stage PMOS and described the first resistance, form Section Point, described Section Point is connected with the output terminal of described LDO circuit.
Preferably, in described LDO circuit, described current lens unit comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor;
A described PMOS transistor, the grid of the 4th nmos pass transistor and the 5th nmos pass transistor is all connected with the output terminal of described differential amplifier with the drain electrode of described the 3rd PMOS transistor and the 5th nmos pass transistor, described the first nmos pass transistor, the grid of the second nmos pass transistor and the 3rd nmos pass transistor and the drain electrode of described the first nmos pass transistor are all connected with the transistorized drain electrode of a described PMOS, described the first nmos pass transistor, the source grounding of the second nmos pass transistor and the 3rd nmos pass transistor, described the 2nd PMOS transistor is all connected with the drain electrode of described the 4th nmos pass transistor with the transistorized grid of the 3rd PMOS and the transistorized drain electrode of described the 2nd PMOS, the drain electrode of described the second nmos pass transistor is connected with the source electrode of described the 4th nmos pass transistor, the drain electrode of described the 3rd nmos pass transistor is connected with the source electrode of described the 5th nmos pass transistor.
Preferably, in described LDO circuit, the size of described the first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor all equates.
Preferably, in described LDO circuit, the size of described the 4th nmos pass transistor and the 5th nmos pass transistor is equal, and described the 2nd PMOS transistor and the transistorized size of the 3rd PMOS equate.
Preferably, in described LDO circuit, also comprise: compensating resistance and Miller capacitance;
Described compensating resistance and Miller capacitance series connection between described Section Point and the output terminal of described differential amplifier;
Between the transistorized grid of described power stage PMOS and described compensating resistance, form first node.
Preferably, in described LDO circuit, described compensating resistance is in parallel with described the 5th nmos pass transistor.
Preferably, in described LDO circuit, the reverse input end of described differential amplifier connects a reference voltage, and described power stage PMOS transistor, a PMOS transistor, the 2nd PMOS transistor and the transistorized source electrode of the 3rd PMOS are all connected with a supply voltage.
Preferably, in described LDO circuit, described LDO circuit is without capacitor type LDO circuit.
In LDO circuit provided by the invention, by increasing current lens unit, described LDO circuit can be moved in the same way with the second limit zero point in the time that load current changes, guarantee thus the stability of described LDO circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of the capacitorless LDO circuit of prior art;
Fig. 2 is the structural representation of the LDO circuit of the embodiment of the present invention.
Embodiment
LDO circuit the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, the structural representation of the LDO circuit that it is the embodiment of the present invention.As shown in Figure 2, described LDO circuit 200 comprises: differential amplifier A2, power stage PMOS transistor mp20, current lens unit 20, the first resistance R 21 and the second resistance R 22, wherein, described the first resistance R 21 and the second resistance R 22 are series between the drain electrode and ground of described power stage PMOS transistor mp20, the positive input of described differential amplifier A2 is connected between described the first resistance R 21 and the second resistance R 22, described current lens unit 20 is all connected with the output terminal of described differential amplifier A2 with the grid of described power stage PMOS transistor mp20, the drain electrode of described power stage PMOS transistor mp20 is connected with described the first resistance R 21, between the drain electrode of described power stage PMOS transistor mp20 and described the first resistance R 21, form Section Point Q2, described Section Point Q2 is connected with the output terminal of described LDO circuit 200.
Concrete, described current lens unit 20 comprises 5 nmos pass transistors and 3 PMOS transistors, in described 5 nmos pass transistors and 3 PMOS transistors, the one PMOS transistor mp1, the grid of the 4th nmos pass transistor mn4 and the 5th nmos pass transistor mn5 is all connected with the output terminal of described differential amplifier A2 with the drain electrode of the 3rd PMOS transistor mp3 and the 5th nmos pass transistor mn5, the first nmos pass transistor mn1, the grid of the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3 and the drain electrode of the first nmos pass transistor mn1 are all connected with the drain electrode of a PMOS transistor mp1, the first nmos pass transistor mn1, the source grounding of the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3, the grid of the 2nd PMOS transistor mp2 and the 3rd PMOS transistor mp3 and the drain electrode of the 2nd PMOS transistor mp2 are all connected with the drain electrode of the 4th nmos pass transistor mn4, the drain electrode of the second nmos pass transistor mn2 is connected with the source electrode of the 4th nmos pass transistor mn4, the drain electrode of the 3rd nmos pass transistor mn3 is connected with the source electrode of the 5th nmos pass transistor mn5.
Described current lens unit 20 comprises reference arm, the first output branch road and the second output branch road, described reference arm comprises the first nmos pass transistor mn1 and a PMOS transistor mp1, the first output branch road comprises the 2nd PMOS transistor mp2, the second nmos pass transistor mn2 and the 4th nmos pass transistor mn4, and the second output branch road comprises the 3rd PMOS transistor mp3, the 3rd nmos pass transistor mn3 and the 5th nmos pass transistor mn5.
Wherein, the size of the first nmos pass transistor mn1, the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3 all equates, the size of the 4th nmos pass transistor mn4 and the 5th nmos pass transistor mn5 is equal, and the size of the 2nd PMOS transistor mp2 and the 3rd PMOS transistor mp3 equates.Visible, the first output branch road and the second output branch structure symmetry in described current lens unit 20.
Because the first nmos pass transistor mn1, the second nmos pass transistor mn2 are connected with the grid of the 3rd nmos pass transistor mn3, the first nmos pass transistor mn1, the second nmos pass transistor mn2 are identical with the grid voltage of the 3rd nmos pass transistor, while, therefore the first electric current I 1, the second electric current I 2 and the 3rd electric current I 3 equated because the first nmos pass transistor mn1, the second nmos pass transistor mn2 and the 3rd nmos pass transistor mn3's is measure-alike.
Please continue to refer to Fig. 2, described LDO circuit 200 also comprises compensating resistance Rm2 and Miller capacitance Cc2, described compensating resistance Rm2 and Miller capacitance Cc2 connect mutually, between the grid of power stage PMOS transistor mp20 and compensating resistance Rm2, form first node Q1, between the drain electrode of power stage PMOS transistor mp20 and the first resistance R 21, form Section Point Q2, described compensating resistance Rm2 and Miller capacitance Cc2 are between described Section Point Q2 and the output terminal of differential amplifier A2.Wherein, described compensating resistance Rm2 is in parallel with the 5th nmos pass transistor mn5.
In the present embodiment, described LDO circuit 200 is without capacitor type LDO circuit (capacitorless LDO), and the output terminal of described LDO circuit 200 is connected with a load capacitance CL2, and the electric capacity of described load capacitance CL2 can be 0.
When described LDO circuit 200 is worked, the reverse input end input reference voltage Vref of differential amplifier A2, the equal input supply voltage VDD of the source electrode of power stage PMOS transistor mp20, a PMOS transistor mp1, the 2nd PMOS transistor mp2 and the 3rd PMOS transistor mp3.
The principle of work of described LDO circuit 200 is as follows: LDO circuit 200 produces output voltage VO UT according to reference voltage Vref, output voltage VO UT through after the first resistance R 21 and the second resistance R 22 dividing potential drops for the input end in the same way of differential amplifier A2 provides feedback voltage V FB, the expression formula of feedback voltage V FB is:
VFB=〔R22÷（R21＋R22）〕×VOUT；
Differential amplifier A2 with reference to voltage Vref and feedback voltage V FB compare obtain difference DELTA V and will difference DELTA V amplify after obtain Δ Vmax, Δ Vmax is for the grid of driving power output PMOS transistor mp20, thereby change by the electric current of power stage PMOS transistor mp20, make reference voltage Vref and feedback voltage V FB approximately equal, and then make the magnitude of voltage of output voltage VO UT be tending towards constant.
In the time that the load current of described LDO circuit 200 rises, the second limit moves to high frequency by low frequency.Meanwhile, the voltage Vg of first node Q1 declines, Vg declines the grid voltage of a PMOS transistor mp1 is declined, and makes thus the first electric current I 1 of described current lens unit 20 increase, and the second electric current I 2 and the 3rd electric current I 3 also increase to the first electric current I 1 thereupon and equate.The 3rd electric current I 3 increases, and means the resistance decreasing of the 5th nmos pass transistor mn5 drain-to-source, and compensating resistance Rm2 and the 5th nmos pass transistor mn5 parallel resistance also diminish thereupon.Therefore, the zero point of described LDO circuit 200 is also to high-frequency mobile, and zero point and the second limit in the same way movement can guarantee the stability of described LDO circuit 200.
To sum up, in the LDO circuit providing in the embodiment of the present invention, by increasing current lens unit, described LDO circuit can be moved in the same way with the second limit zero point in the time that load current changes, guarantee that described LDO circuit also can steady operation in the time that load current changes, even if load current sharply increased in moment, can not affect the normal work of described LDO circuit yet.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (8)
1. a LDO circuit, is characterized in that, comprising: differential amplifier, power stage PMOS transistor, current lens unit, the first resistance and the second resistance;
Wherein, described the first resistance and the second resistance are series between the transistorized drain electrode of described power stage PMOS and ground, the positive input of described differential amplifier is connected between described the first resistance and the second resistance, described current lens unit is all connected with the output terminal of described differential amplifier with the transistorized grid of described power stage PMOS, the transistorized drain electrode of described power stage PMOS is connected with described the first resistance, between the transistorized drain electrode of described power stage PMOS and described the first resistance, form Section Point, described Section Point is connected with the output terminal of described LDO circuit.
2. LDO circuit as claimed in claim 1, it is characterized in that, described current lens unit comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor;
A described PMOS transistor, the grid of the 4th nmos pass transistor and the 5th nmos pass transistor is all connected with the output terminal of described differential amplifier with the drain electrode of described the 3rd PMOS transistor and the 5th nmos pass transistor, described the first nmos pass transistor, the grid of the second nmos pass transistor and the 3rd nmos pass transistor and the drain electrode of described the first nmos pass transistor are all connected with the transistorized drain electrode of a described PMOS, described the first nmos pass transistor, the source grounding of the second nmos pass transistor and the 3rd nmos pass transistor, described the 2nd PMOS transistor is all connected with the drain electrode of described the 4th nmos pass transistor with the transistorized grid of the 3rd PMOS and the transistorized drain electrode of described the 2nd PMOS, the drain electrode of described the second nmos pass transistor is connected with the source electrode of described the 4th nmos pass transistor, the drain electrode of described the 3rd nmos pass transistor is connected with the source electrode of described the 5th nmos pass transistor.
3. LDO circuit as claimed in claim 2, is characterized in that, the size of described the first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor all equates.
4. LDO circuit as claimed in claim 2, is characterized in that, the size of described the 4th nmos pass transistor and the 5th nmos pass transistor is equal, and described the 2nd PMOS transistor and the transistorized size of the 3rd PMOS equate.
5. LDO circuit as claimed in claim 1, is characterized in that, also comprises: compensating resistance and Miller capacitance;
Described compensating resistance and Miller capacitance series connection between described Section Point and the output terminal of described differential amplifier;
Between the transistorized grid of described power stage PMOS and described compensating resistance, form first node.
6. LDO circuit as claimed in claim 5, is characterized in that, described compensating resistance is in parallel with described the 5th nmos pass transistor.
7. LDO circuit as claimed in claim 6, it is characterized in that, the reverse input end of described differential amplifier connects a reference voltage, and described power stage PMOS transistor, a PMOS transistor, the 2nd PMOS transistor and the transistorized source electrode of the 3rd PMOS are all connected with a supply voltage.
8. LDO circuit as claimed in claim 1, is characterized in that, described LDO circuit is without capacitor type LDO circuit.
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| CN104950974A (en) * | 2015-06-30 | 2015-09-30 | 华为技术有限公司 | Low dropout linear regulator, method for improving stability of low dropout linear regulator and phase-locked loop |
| EP3107209A3 (en) * | 2015-05-27 | 2017-04-05 | STMicroelectronics Srl | Voltage regulator with improved electrical properties and corresponding control method |
| CN107797602A (en) * | 2016-08-31 | 2018-03-13 | 意法半导体股份有限公司 | Miller-compensated circuit and corresponding adjuster, system and method |
| CN108964448A (en) * | 2018-08-27 | 2018-12-07 | 重庆西南集成电路设计有限责任公司 | A kind of power generation circuit |
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| CN104734498A (en) * | 2015-04-13 | 2015-06-24 | 无锡新硅微电子有限公司 | DC-DC voltage rising module and voltage rising module overvoltage protection circuit |
| US9684324B2 (en) | 2015-05-27 | 2017-06-20 | Stmicroelectronics S.R.L. | Voltage regulator with improved electrical properties and corresponding control method |
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| US10915123B2 (en) | 2015-06-30 | 2021-02-09 | Huawei Technologies Co., Ltd. | Low dropout regulator and phase-locked loop |
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| US10254778B1 (en) | 2018-07-12 | 2019-04-09 | Infineon Technologies Austria Ag | Pole-zero tracking compensation network for voltage regulators |
| CN108964448A (en) * | 2018-08-27 | 2018-12-07 | 重庆西南集成电路设计有限责任公司 | A kind of power generation circuit |
| CN112445262A (en) * | 2019-09-04 | 2021-03-05 | 辰芯科技有限公司 | Low-dropout voltage stabilizing circuit supporting multi-path direct parallel output, operation method and power supply device thereof |
| CN112445262B (en) * | 2019-09-04 | 2022-05-10 | 辰芯科技有限公司 | Low-dropout voltage stabilizing circuit supporting multi-path direct parallel output, operation method and power supply device thereof |
| CN113342108A (en) * | 2021-06-08 | 2021-09-03 | 成都华微电子科技有限公司 | Parallel operational amplifier zero compensation circuit |
| CN113342108B (en) * | 2021-06-08 | 2022-09-06 | 成都华微电子科技股份有限公司 | Parallel operational amplifier zero compensation circuit |
| CN114167938A (en) * | 2021-10-12 | 2022-03-11 | 广东赛微微电子股份有限公司 | Power management chip, linear voltage stabilizing circuit and bias current compensation method thereof |
| CN115113681A (en) * | 2022-07-22 | 2022-09-27 | 北京智芯微电子科技有限公司 | Load regulation rate compensation circuit, voltage stabilizing circuit, device and chip |
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