CN108549451A - High pressure areas coefficient interior power supply circuit - Google Patents
High pressure areas coefficient interior power supply circuit Download PDFInfo
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- CN108549451A CN108549451A CN201810498926.6A CN201810498926A CN108549451A CN 108549451 A CN108549451 A CN 108549451A CN 201810498926 A CN201810498926 A CN 201810498926A CN 108549451 A CN108549451 A CN 108549451A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
This application discloses a kind of High pressure areas coefficient interior power supply circuits, belong to Analogous Integrated Electronic Circuits technical field.The High pressure areas coefficient internal electric source using both NMOS tube and PMOS tube conducting when gate source voltage Vgs polarity on the contrary, and Zener diode breakdown after stabilizing voltage characteristic so that supply voltage V of the circuit to internal low-voltage moduleOUTVDD is followed to change when VDD is relatively low, when VDD is more than the breakdown voltage V of the 5th Zener diodeD5When VOUTIt is fixed as VD5；VOUTIt follows its characteristic changed to reduce the minimum value that VDD makes circuit work normally when VDD is relatively low, expands the application range of circuit, VDD is more than VD5V afterwardsOUTIt is fixed as VD5Characteristic, realize the protection to internal low-voltage module.
Description
Technical field
The application belongs to electronic technology field, is related to Analogous Integrated Electronic Circuits technical field, particularly relates to a kind of high
Press driving chip interior power supply circuit.
Background technology
High pressure IC (integrated circuit) chip is the driving element by low pressure digital control logic and high pressure transformation
The circuit being integrated on the same disk.High pressure IC chip simplifies the complexity of power circuit, makes its volume, weight and price
Etc. be greatly reduced.In numerous high pressure IC chips, with the development of designing technique, high drive class chip is in intelligence
Energy switch, automotive electronics and FPD etc. have extensive purposes, market potential huge.
Usual high drive class chip operating voltage input range lies prostrate to be several to tens volts, and in view of the unlatching of metal-oxide-semiconductor
The characteristics such as threshold voltage and conducting resistance require the analog- and digital- module of chip interior to select low-voltage device.Therefore it is required that
Chip interior must have a special module handled external input voltage to be powered to internal low-voltage device,
The area for increasing entire chip in this way, improves product cost.
In conventional high-tension chip interior, usually by VDD (external high pressure input), through LDO, (low pressure difference linearity is steady as shown in Figure 1
Depressor) processing after to chip interior low-voltage module power.Since operational amplifier A 0 need to be used, loop compensation can be related to
Increase circuit complexity.Simultaneously in such structure, chip interior low-voltage module power supply (VOUT) it is fixed value so that external input
The minimum value of VDD is limited, shown in following formula (1), limits the application range of chip.
Invention content
The purpose of the application, aiming at above-mentioned conventional high-tension chip interior power circuit, there are complicated and to outside
The problem of input minimum value requires, proposes a kind of novel high-pressure driving chip interior power supply circuit.
The technical solution of the application：A kind of High pressure areas coefficient interior power supply circuit, the High pressure areas coefficient internal electric source
Circuit includes the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the
Seven NMOS tubes, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube,
One resistance, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th electricity
Resistance, the tenth resistance, the first Zener diode, the second Zener diode, third Zener diode, the 4th Zener diode, the 5th
Zener diode, the first PNP triode, the second PNP triode, the first NPN triode, the second NPN triode, the first capacitance,
Second capacitance and third capacitance, wherein：
The drain terminal of first NMOS tube connects the first end of first resistor, and the grid end of the first NMOS tube meets the ports EN, the first NMOS
The source of pipe connects the drain terminal of the second NMOS tube；The drain terminal of second NMOS tube connects the grid end of the second NMOS tube, the source of the second NMOS tube
Terminate GND；The drain terminal of third NMOS tube connects the grid end of third NMOS tube, and the grid end of third NMOS tube connects the first of the 5th resistance
End, the source of third NMOS tube meet GND；The drain terminal of 4th NMOS tube connects the first end of the 7th resistance, the grid end of the 4th NMOS tube
The grid end of third NMOS tube is connect, the source of the 4th NMOS tube meets GND；The drain terminal of 5th NMOS tube connects the first end of the 8th resistance,
The grid end of 5th NMOS tube connects the drain terminal of the 5th NMOS tube, and the source of the 5th NMOS tube meets GND；The drain terminal of 6th NMOS tube connects
The grid end of the drain terminal of five PMOS tube, the 6th NMOS tube connects the grid end of third NMOS tube, and the source of the 6th NMOS tube meets GND；7th
The drain terminal of NMOS tube meets VDD, and the grid end of the 7th NMOS tube connects the first end of the second capacitance, and the source of the 7th NMOS tube meets VOUT；
The drain terminal of first PMOS tube connects the first end of the 4th resistance, and the grid end of the first PMOS tube connects the leakage of the first PMOS tube
End, the source of the first PMOS tube meet VDD；The drain terminal of second PMOS tube connects the second end of the 5th resistance, the grid end of the second PMOS tube
The grid end of the first PMOS tube is connect, the source of the second PMOS tube meets VDD；The drain terminal of third PMOS tube connects the source of the 4th PMOS tube,
The grid end of third PMOS tube connects the grid end of the first PMOS tube, and the source of third PMOS tube connects the first end of the 9th resistance；4th
The drain terminal of PMOS tube connects the second end of the 8th resistance, and the grid end of the 4th PMOS tube connects the second end of the 7th resistance, the 4th PMOS tube
Source connect the anode of the second Zener diode；The drain terminal of 5th PMOS tube connects the drain terminal of the 6th NMOS tube, the 5th PMOS tube
Grid end connects the drain terminal of third PMOS tube, and the source of the 5th PMOS tube meets VDD；The drain terminal of 6th PMOS tube meets VOUT, the 6th PMOS
The grid end of pipe connects the drain terminal of the 5th PMOS tube, and the source of the 6th PMOS tube meets VDD；
The base stage of second the first PNP triode of termination of first resistor, first the first NMOS tube of termination of first resistor
Drain terminal；First termination VDD of second resistance, the emitter of second the second PNP triode of termination of second resistance；3rd resistor
First termination VDD, the source of second the first PMOS tube of termination of 3rd resistor；First the first PMOS tube of termination of the 4th resistance
Drain terminal, the collector of second the second NPN triode of termination of the 4th resistance；The leakage of second the second PMOS tube of termination of the 5th resistance
End, the drain terminal of the first termination third NMOS tube of the 5th resistance；The transmitting of first the second NPN triode of termination of the 6th resistance
Pole, the second termination GND of the 6th resistance；The grid end of second the 4th PMOS tube of termination of the 7th resistance, the first end of the 7th resistance
Connect the drain terminal of the 4th NMOS tube；The drain terminal of second the 4th PMOS tube of termination of the 8th resistance, the first termination the 5th of the 8th resistance
The drain terminal of NMOS tube；Second termination VDD of the 9th resistance, the source of the first termination third PMOS tube of the 9th resistance；Tenth electricity
The drain terminal of first the 4th PMOS tube of termination of resistance, the grid end of the second the 7th NMOS tube of termination of the tenth resistance；
The second end of the 7th resistance of positive termination of first Zener diode, the negative terminal of the first Zener diode meet VDD；Second
The drain terminal of the positive termination third PMOS tube of Zener diode, the negative terminal of the second Zener diode meet VDD；Third Zener diode
The drain terminal of the 5th PMOS tube of positive termination, the negative terminal of third Zener diode meet VDD；The positive termination GND of 4th Zener diode, the
The negative terminal of four Zener diodes connects the first end of the first capacitance；The positive termination GND of 5th Zener diode, the 5th Zener diode
Negative terminal connect the source of the 7th NMOS tube；
The collector of first PNP triode connects the drain terminal of the first NMOS tube, and the base stage of the first PNP triode connects first resistor
Second end, the emitter of the first PNP triode meets VDD；The collector of second PNP triode connects the collection of the first NPN triode
The base stage of electrode, the second PNP triode connects the first end of first resistor, and the emitter of the second PNP triode connects first resistor
Second end；The collector of first NPN triode connects the base stage of the first NPN triode, and the base stage of the first NPN triode connects second
The emitter of the base stage of NPN triode, the first NPN triode meets GND；The collector of second NPN triode connects the 4th resistance
Second end, the base stage of the second NPN triode connect the collector of the second PNP triode, and the emitter of the second NPN triode connects the 6th
The first end of resistance；
The drain terminal of first the 4th PMOS tube of termination of the first capacitance, the second termination GND of the first capacitance；The of second capacitance
The grid end of one the 7th NMOS tube of termination, the second termination GND of the second capacitance；First termination VOUT of third capacitance, third capacitance
Second termination GND.
Optionally, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th
NMOS tube, the 7th NMOS tube, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th
PMOS tube is the high pressure resistant pipe of drain terminal, the first PNP triode, the second PNP triode, the first NPN triode, tri- poles the 2nd NPN
Pipe is the high pressure resistant triodes of VCE, and VCE is the difference of collector and transmitting extreme pressure.
Optionally, first resistor is identical with the resistance value of second resistance.
Beneficial effects of the present invention are：Its Vgs (gate source voltage) polarity in conducting using both NMOS tube and PMOS tube
On the contrary, and Zener diode breakdown after stabilizing voltage characteristic so that VOUT(supply voltage of the circuit to internal low-voltage module) exists
VDD is followed to change when VDD is relatively low, when VDD is more than VD5V when (breakdown voltage of the 5th Zener diode)OUTIt is fixed as VD5；VOUT
Its characteristic changed is followed to reduce the minimum value that VDD makes circuit work normally when VDD is relatively low, expand circuit applies model
It encloses.VDD is more than VD5V afterwardsOUTIt is fixed as VD5Characteristic, realize the protection to internal low-voltage module.
It should be understood that above general description and following detailed description is merely exemplary, this can not be limited
Invention.
Description of the drawings
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the present invention
Example, and be used to explain the principle of the present invention together with specification.
Fig. 1 is the circuit diagram of the low-voltage module of conventional high-tension chip interior setting；
Fig. 2 is the circuit diagram of the High pressure areas coefficient interior power supply circuit provided in the application section Example；
Fig. 3 is the waveform diagram that power circuit is provided in the application section Example in normal work.
Specific implementation mode
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent and the consistent all embodiments of the present invention.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects being described in detail in claims, of the invention.
Fig. 2 is the circuit diagram of the High pressure areas coefficient interior power supply circuit provided in the application section Example, the high pressure
Driving chip interior power supply circuit includes the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube
MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the first PMOS tube MP1, the second PMOS tube MP2,
Three PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, first resistor R1, second resistance R2,
3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9,
Tenth resistance R10, the first Zener diode D1, the second Zener diode D2, third Zener diode D3, the 4th Zener diode
D4, the 5th Zener diode D5, the first PNP triode QPNP1, the second PNP triode QPNP2, the first NPN triode QNPN1,
Second NPN triode QNPN2, the first capacitance C1, the second capacitance C2 and third capacitance C3, the connection relation between each device is such as
Under：
The drain terminal of first NMOS tube MN1 connects the first end of first resistor R1, and the grid end of the first NMOS tube MN1 connects the ports EN,
The source of first NMOS tube MN1 connects the drain terminal of the second NMOS tube MN2；The drain terminal of second NMOS tube MN2 connects the second NMOS tube MN2's
The source of grid end, the second NMOS tube MN2 meets GND；The drain terminal of third NMOS tube MN3 connects the grid end of third NMOS tube MN3, third
The grid end of NMOS tube MN3 connects the first end of the 5th resistance R5, and the source of third NMOS tube MN3 meets GND；4th NMOS tube MN4's
Drain terminal connects the first end of the 7th resistance R7, and the grid end of the 4th NMOS tube MN4 connects the grid end of third NMOS tube MN3, the 4th NMOS tube
The source of MN4 meets GND；The drain terminal of 5th NMOS tube MN5 connects the first end of the 8th resistance R8, and the grid end of the 5th NMOS tube MN5 connects
The source of the drain terminal of 5th NMOS tube MN5, the 5th NMOS tube MN5 meets GND；The drain terminal of 6th NMOS tube MN6 connects the 5th PMOS tube
The grid end of the drain terminal of MP5, the 6th NMOS tube MN6 connects the grid end of third NMOS tube MN3, and the source of the 6th NMOS tube MN6 meets GND；
The drain terminal of 7th NMOS tube MN7 meets VDD, and the grid end of the 7th NMOS tube MN7 connects the first end of the second capacitance C2, the 7th NMOS tube
The source of MN7 meets VOUT.
The drain terminal of first PMOS tube MP1 connects the first end of the 4th resistance R4, and the grid end of the first PMOS tube MP1 meets the first PMOS
The source of the drain terminal of pipe MP1, the first PMOS tube MP1 meets VDD；The drain terminal of second PMOS tube MP2 connects the second end of the 5th resistance R5,
The grid end of second PMOS tube MP2 connects the grid end of the first PMOS tube MP1, and the source of the second PMOS tube MP2 meets VDD；Third PMOS tube
The drain terminal of MP3 connects the source of the 4th PMOS tube MP4, and the grid end of third PMOS tube MP3 connects the grid end of the first PMOS tube MP1, third
The source of PMOS tube MP3 connects the first end of the 9th resistance R9；The drain terminal of 4th PMOS tube MP4 connects the second end of the 8th resistance R8,
The grid end of 4th PMOS tube MP4 connects the second end of the 7th resistance R7, and the source of the 4th PMOS tube MP4 meets the second Zener diode D2
Anode；The drain terminal of 5th PMOS tube MP5 connects the drain terminal of the 6th NMOS tube MN6, and the grid end of the 5th PMOS tube MP5 meets the 3rd PMOS
The source of the drain terminal of pipe MP3, the 5th PMOS tube MP5 meets VDD；The drain terminal of 6th PMOS tube MP6 meets VOUT, the 6th PMOS tube MP6
Grid end connect the drain terminal of the 5th PMOS tube MP5, the source of the 6th PMOS tube MP6 meets VDD.
The base stage of second the first PNP triode QPNP1 of termination of first resistor R1, the first termination first of first resistor R1
The drain terminal of NMOS tube MN1；Second the second PNP triode of termination of the first termination VDD, second resistance R2 of second resistance R2
The emitter of QPNP2；The source of second the first PMOS tube MP1 of termination of the first termination VDD, 3rd resistor R3 of 3rd resistor R3
End；The drain terminal of first the first PMOS tube MP1 of termination of 4th resistance R4, second the second NPN triode of termination of the 4th resistance R4
The collector of QNPN2；The drain terminal of second the second PMOS tube MP2 of termination of 5th resistance R5, the first termination the of the 5th resistance R5
The drain terminal of three NMOS tube MN3；The emitter of first the second NPN triode QNPN2 of termination of 6th resistance R6, the 6th resistance R6's
Second termination GND；The grid end of the second the 4th PMOS tube MP4 of termination of 7th resistance R7, the first termination the 4th of the 7th resistance R7
The drain terminal of NMOS tube MN4；The drain terminal of the second the 4th PMOS tube MP4 of termination of 8th resistance R8, the first termination of the 8th resistance R8
The drain terminal of 5th NMOS tube MN5；The first termination third PMOS tube MP3 of the second termination VDD, the 9th resistance R9 of 9th resistance R9
Source；The drain terminal of the first the 4th PMOS tube MP4 of termination of tenth resistance R10, the second the 7th NMOS of termination of the tenth resistance R10
The grid end of pipe MN7.
The second end of the 7th resistance R7 of positive termination of first Zener diode D1, the negative terminal of the first Zener diode D1 connect
VDD；The drain terminal of the positive termination third PMOS tube MP3 of second Zener diode D2, the negative terminal of the second Zener diode D2 meet VDD；
The drain terminal of the 5th PMOS tube MP5 of positive termination of third Zener diode D3, the negative terminal of third Zener diode D3 meet VDD；4th
The positive termination GND of Zener diode D4, the negative terminal of the 4th Zener diode D4 connect the first end of the first capacitance C1；5th Zener two
The positive termination GND of pole pipe D5, the negative terminal of the 5th Zener diode D5 connect the source of the 7th NMOS tube MN7.
The collector of first PNP triode QPNP1 connects the drain terminal of the first NMOS tube MN1, the first PNP triode QPNP1's
Base stage connects the second end of first resistor R1, and the emitter of the first PNP triode QPNP1 meets VDD；Second PNP triode QPNP2's
Collector connects the collector of the first NPN triode QNPN1, and the base stage of the second PNP triode QPNP2 connects the first of first resistor R1
End, the emitter of the second PNP triode QPNP2 connect the second end of first resistor R1；The collector of first NPN triode QNPN1
The base stage of the first NPN triode QNPN1 is connect, the base stage of the first NPN triode QNPN1 connects the base of the second NPN triode QNPN2
The emitter of pole, the first NPN triode QNPN1 meets GND；The collector of second NPN triode QNPN2 connects the of the 4th resistance R4
Two ends, the base stage of the second NPN triode QNPN2 meet the collector of the second PNP triode QPNP2, the second NPN triode QNPN2
Emitter connect the first end of the 6th resistance R6.
The drain terminal of the first the 4th PMOS tube MP4 of termination of first capacitance C1, the second termination GND of the first capacitance C1；Second
The grid end of the first the 7th NMOS tube MN7 of termination of capacitance C2, the second termination GND of the second capacitance C2；The first of third capacitance C3
Terminate VOUT, the second termination GND of third capacitance C3.
Optionally, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th
NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube
MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6 are the high pressure resistant pipe LDMOS of drain terminal, the first PNP tri-
Pole pipe QPNP1, the second PNP triode QPNP2, the first NPN triode QNPN1, the second NPN triode QNPN2 are the resistance to height of VCE
It is the difference of collector and transmitting extreme pressure to press triode, VCE.
Optionally, first resistor R1 is identical with the resistance value of second resistance R2.
The operation principle of the application is：
First NMOS tube MN1, the second NMOS tube MN2, first resistor R1, second resistance R2, the first PNP triode QPNP1,
Second PNP triode QPNP2 and the first NPN triode QNPN1 constitute biasing module.The resistance of first resistor R1 and second resistance R2
Be worth it is equal, if value be Rbias, then as EN port voltages (VEN) circuit starts just when meeting following formula (2), (3) and (4) condition
Often work.
VEN≥Vgs(MN1)+Vgs(MN2) (2)
Wherein VEB(QPNP2)Represent the emitter and collector pressure difference of the second PNP triode QPNP2, μnRepresent N-type metal-oxide-semiconductor
Channel electron mobility, CoxMetal-oxide-semiconductor grid oxygen layer thickness is represented,WithRespectively represent the first NMOS tube MN1 with
The breadth length ratio of second NMOS tube MN2, VthnRepresent N-type metal-oxide-semiconductor threshold voltage.
Assuming that the first Zener diode D1, the second Zener diode D2, third Zener diode D3, the 4th Zener diode
Burning voltage after D4 and the 5th Zener diode D5 breakdown, VD1、VD2、VD3、VD4And VD5It is equal, if value is VD。
1., as VDD≤VDWhen, the first Zener diode D1 is in open-circuit condition, the 4th PMOS tube MP4 grid voltages
It is pulled to GND by current source MN4.By adjusting the 4th PMOS tube MP4's and the 5th NMOS tube MN5
The resistance value of breadth length ratio and the 8th resistance R8 so that Vs (MP4) (MP4 source voltage terminals) meets group (5) formula always,
Then the 5th PMOS tube MP5 is off state, passes through the 6th PMOS tube MP6 grid electricity of current source MN6 effects
Pressure is GND.To there is VOUT=VDD.
VDD-Vs(MP4)＜ | Vthp| (5)
Wherein VthpFor PMOS tube threshold voltage.
2., as VDD ＞ VDWhen, the first both ends Zener diode D1 pressure difference is fixed as VD, adjust third PMOS tube MP3
Breadth length ratio and the 9th resistance R9 resistance values so that Vsg(MP5)＞ | Vthp|Vsg(MP5)For the 5th PMOS tube MP5 sources and grid
End
Pressure difference), then the 6th PMOS tube MP6 grid voltages are pulled to VDD, and the 6th PMOS tube MP6 is closed.
Simultaneously to the 7th NMOS tube MN7 grid voltages (Vg(MN7)) have：
Vg(MN7)=Vgs(MN5)+IMP3·R8 (6)
IMP3Represent the electric current for flowing through third PMOS tube MP3.6th PMOS tube MP6 and the 7th NMOS tube MN7 is adjustment pipe,
Breadth length ratio is larger.Therefore when as VDD ＞ VDWhen, VOUT ≈ Vg(MN7)-Vthn。
In conclusion High pressure areas coefficient interior power supply circuit provided by the present application, as VDD≤VDWhen so that VOUTIt follows
VDD changes, requirement when reducing circuit normal work to minimum VDD；As VDD ＞ VDWhen, VOUTIt is fixed as VD5, realize pair
The protection of internal low-voltage module.And amplifier is not present in the application circuit, without considering loop stability sex chromosome mosaicism, circuit structure letter
It is single.
Those skilled in the art will readily occur to its of the present invention after considering specification and putting into practice the invention invented here
Its embodiment.This application is intended to cover the present invention any variations, uses, or adaptations, these modifications, purposes or
Person's adaptive change follows the general principle of the present invention and includes the common knowledge in the art that the present invention does not invent
Or conventional techniques.The description and examples are only to be considered as illustrative, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be understood that the invention is not limited in the precision architectures for being described above and being shown in the accompanying drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present invention is limited only by the attached claims.
Claims (3)
1. a kind of High pressure areas coefficient interior power supply circuit, which is characterized in that the High pressure areas coefficient interior power supply circuit packet
Include the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS
Pipe, the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first electricity
Resistance, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance,
Ten resistance, the first Zener diode, the second Zener diode, third Zener diode, the 4th Zener diode, the 5th Zener two
Pole pipe, the first PNP triode, the second PNP triode, the first NPN triode, the second NPN triode, the first capacitance, the second electricity
Appearance and third capacitance, wherein：
The drain terminal of first NMOS tube connects the first end of the first resistor, and the grid end of first NMOS tube connects the ports EN,
The source of first NMOS tube connects the drain terminal of second NMOS tube；The drain terminal of second NMOS tube meets the 2nd NMOS
The source of the grid end of pipe, second NMOS tube meets GND；The drain terminal of the third NMOS tube connects the grid of the third NMOS tube
End, the grid end of the third NMOS tube connect the first end of the 5th resistance, and the source of the third NMOS tube meets GND；It is described
The drain terminal of 4th NMOS tube connects the first end of the 7th resistance, and the grid end of the 4th NMOS tube connects the third NMOS tube
The source of grid end, the 4th NMOS tube meets GND；The drain terminal of 5th NMOS tube meets the first end of the 8th resistance, institute
The grid end for stating the 5th NMOS tube connects the drain terminal of the 5th NMOS tube, and the source of the 5th NMOS tube meets GND；Described 6th
The drain terminal of NMOS tube connects the drain terminal of the 5th PMOS tube, and the grid end of the 6th NMOS tube connects the grid of the third NMOS tube
End, the source of the 6th NMOS tube meet GND；The drain terminal of 7th NMOS tube meets VDD, and the grid end of the 7th NMOS tube connects
The source of the first end of second capacitance, the 7th NMOS tube meets VOUT；
The drain terminal of first PMOS tube connects the first end of the 4th resistance, and the grid end of first PMOS tube connects described first
The source of the drain terminal of PMOS tube, first PMOS tube meets VDD；The drain terminal of second PMOS tube connects the of the 5th resistance
Two ends, the grid end of second PMOS tube connect the grid end of first PMOS tube, and the source of second PMOS tube meets VDD；Institute
The drain terminal for stating third PMOS tube connects the source of the 4th PMOS tube, and the grid end of the third PMOS tube connects first PMOS tube
Grid end, the source of the third PMOS tube connects the first end of the 9th resistance；The drain terminal of 4th PMOS tube connects described
The grid end of the second end of 8th resistance, the 4th PMOS tube connects the second end of the 7th resistance, the 4th PMOS tube
Source connects the anode of second Zener diode；The drain terminal of 5th PMOS tube meets the drain terminal of the 6th NMOS tube, institute
The grid end for stating the 5th PMOS tube connects the drain terminal of the third PMOS tube, and the source of the 5th PMOS tube meets VDD；Described 6th
The drain terminal of PMOS tube meets VOUT, and the grid end of the 6th PMOS tube connects the drain terminal of the 5th PMOS tube, the 6th PMOS tube
Source meet VDD；
The base stage of second termination first PNP triode of the first resistor, described in the first termination of the first resistor
The drain terminal of first NMOS tube；First termination VDD of the second resistance, the second termination the 2nd PNP of the second resistance
The emitter of triode；First termination VDD of the 3rd resistor, the second termination first PMOS tube of the 3rd resistor
Source；The drain terminal of first termination first PMOS tube of the 4th resistance, described in the second termination of the 4th resistance
The collector of second NPN triode；The drain terminal of second termination second PMOS tube of the 5th resistance, the 5th resistance
The first termination third NMOS tube drain terminal；The transmitting of first termination second NPN triode of the 6th resistance
Pole, the second termination GND of the 6th resistance；The grid end of second termination the 4th PMOS tube of the 7th resistance, it is described
The drain terminal of first termination the 4th NMOS tube of the 7th resistance；Second termination the 4th PMOS tube of the 8th resistance
Drain terminal, the drain terminal of the first the 5th NMOS tube of termination of the 8th resistance；Second termination VDD of the 9th resistance, described the
The source of the first termination third PMOS tube of nine resistance；The leakage of first termination the 4th PMOS tube of the tenth resistance
End, the grid end of the second termination the 7th NMOS tube of the tenth resistance；
The second end for just terminating the 7th resistance of first Zener diode, the negative terminal of first Zener diode connect
VDD；The drain terminal for just terminating the third PMOS tube of second Zener diode, the negative terminal of second Zener diode connect
VDD；The drain terminal for just terminating the 5th PMOS tube of the third Zener diode, the negative terminal of the third Zener diode connect
VDD；The positive termination GND of 4th Zener diode, the negative terminal of the 4th Zener diode connect the of first capacitance
One end；The positive termination GND of 5th Zener diode, the negative terminal of the 5th Zener diode connect the 7th NMOS tube
Source；
The collector of first PNP triode connects the drain terminal of first NMOS tube, and the base stage of first PNP triode connects
The emitter of the second end of the first resistor, first PNP triode meets VDD；The collector of second PNP triode
The collector of first NPN triode is connect, the base stage of second PNP triode meets the first end of the first resistor, institute
The emitter for stating the second PNP triode connects the second end of the first resistor；The collector of first NPN triode connects described
The base stage of first NPN triode, the base stage of first NPN triode connect the base stage of second NPN triode, and described first
The emitter of NPN triode meets GND；The collector of second NPN triode connects the second end of the 4th resistance, and described
The base stage of two NPN triodes connects the collector of second PNP triode, and the emitter of second NPN triode connects described
The first end of 6th resistance；
The drain terminal of first termination the 4th PMOS tube of first capacitance, the second termination GND of first capacitance；It is described
The grid end of first termination the 7th NMOS tube of the second capacitance, the second termination GND of second capacitance；The third capacitance
First termination VOUT, the third capacitance second termination GND.
2. High pressure areas coefficient interior power supply circuit according to claim 1, which is characterized in that first NMOS tube,
Second NMOS tube, the third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, institute
State the 7th NMOS tube, first PMOS tube, second PMOS tube, the third PMOS tube, the 4th PMOS tube, described
5th PMOS tube, the 6th PMOS tube are the high pressure resistant pipe of drain terminal, first PNP triode, tri- poles the 2nd PNP
Pipe, first NPN triode, second NPN triode are the high pressure resistant triodes of VCE, and the VCE is collector and hair
The difference of emitter-base bandgap grading pressure.
3. High pressure areas coefficient interior power supply circuit according to claim 1, which is characterized in that the first resistor and institute
The resistance value for stating second resistance is identical.
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| CN111541432A (en) * | 2020-05-15 | 2020-08-14 | 中国电子科技集团公司第五十八研究所 | Error amplifier circuit for dynamic negative bias application |
| CN111555615A (en) * | 2020-05-11 | 2020-08-18 | 中国电子科技集团公司第五十八研究所 | Frequency regulating circuit suitable for buck-boost converter |
| CN113190075A (en) * | 2021-04-21 | 2021-07-30 | 电子科技大学 | Wide input range's digital power supply Capless LDO |
| CN113342109A (en) * | 2021-06-18 | 2021-09-03 | 电子科技大学 | Low dropout regulator with maximum current limiting function |
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| CN111555615A (en) * | 2020-05-11 | 2020-08-18 | 中国电子科技集团公司第五十八研究所 | Frequency regulating circuit suitable for buck-boost converter |
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| CN111541432A (en) * | 2020-05-15 | 2020-08-14 | 中国电子科技集团公司第五十八研究所 | Error amplifier circuit for dynamic negative bias application |
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| CN113342109A (en) * | 2021-06-18 | 2021-09-03 | 电子科技大学 | Low dropout regulator with maximum current limiting function |
| CN113342109B (en) * | 2021-06-18 | 2022-04-22 | 电子科技大学 | Low dropout regulator with maximum current limiting function |
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