CN106020317B - A kind of current foldback circuit of low pressure difference linear voltage regulator - Google Patents
A kind of current foldback circuit of low pressure difference linear voltage regulator Download PDFInfo
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- CN106020317B CN106020317B CN201610362624.7A CN201610362624A CN106020317B CN 106020317 B CN106020317 B CN 106020317B CN 201610362624 A CN201610362624 A CN 201610362624A CN 106020317 B CN106020317 B CN 106020317B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
Abstract
The invention discloses a kind of current foldback circuit of low pressure difference linear voltage regulator; it is connected with low pressure difference linear voltage regulator and overcurrent protection is carried out to it; described low pressure difference linear voltage regulator includes voltage input end, power tube, driving voltage end, voltage output end; the current foldback circuit of the low pressure difference linear voltage regulator includes sampling pipe; current comparison circuit; overcurrent protection execution circuit, the output end of overcurrent protection execution circuit is connected with driving voltage end.A kind of circuit structure of the current foldback circuit of low pressure difference linear voltage regulator of the present invention is simple; it is that excessively stream can be achieved to judge without using comparator; and sample rate current is flowed to outside chip with output current; with not flowing to chip; therefore smaller chip ground terminal quiescent current can be achieved under various output currents, the quiescent dissipation of chip is significantly reduced.The present invention can be widely applied to low pressure difference linear voltage regulator field as a kind of current foldback circuit of low pressure difference linear voltage regulator.
Description
Technical field
The present invention relates to low pressure difference linear voltage regulator field, the overcurrent protection electricity of especially a kind of low pressure difference linear voltage regulator
Road.
Background technology
With developing rapidly for integrated circuit, the market of power supply and power management chip is more and more wide.Low pressure difference linearity
Voltage-stablizer is used as a kind of structure of power management, the important seat in occuping market.It is used as core device in low pressure difference linear voltage regulator
The power tube of part, with the weaker ability for bearing short-time overload.When assembling because of excessively stream power tube self-energy in work,
Easily cause avalanche breakdown and damage device.Therefore need to design current foldback circuit in actual applications, it is ensured that power device
Reliably, stably work.Because low pressure difference linear voltage regulator is generally used in the electric power system of portable type electronic product, so will
Seeking the power consumption of low pressure difference linear voltage regulator sufficiently small must could extend power-on time.Protected as the excessively stream in embedded functional circuit
Protection circuit, except providing reliable circuit protection function, its additional power consumption also must be as far as possible small.
In using PMOS as the low pressure difference linear voltage regulator of power tube, common current foldback circuit is to utilize a sampling
Pipe is with the electric current on certain proportion sampled power pipe, and the sample rate current is multiplied with resistance to be obtained one and be directly proportional to output current
Voltage, then the voltage and reference voltage are compared, the grid of power tube are controlled by logic circuit, reduce power tube
Grid-source voltage Vgs, so that the output current of power tube is limited in into some value.
With reference to Fig. 1, Fig. 1 is a kind of typical low pressure difference linear voltage regulator current foldback circuit.The PMOS power of voltage-stablizer
Pipe M1 source electrode connects input voltage VIN, drains and meets output voltage VO UT, and grid and PMOS sampling pipes M2 grid connect common drive
Dynamic voltage Vdrive, PMOS M3 and M4 are connected into current-mirror structure, it is ensured that and PMOS power tube M1 and PMOS sampling pipes M2 drain electrode-
Source voltage Vds is equal, so as to ensure the high accuracy of sample rate current.Current source I1 provides bias current, resistance for PMOS M3
The product of R1 and sample rate current is compared by comparator with reference voltage V REF, then controls Vdrive by logic circuit.When
When output current is more than certain value, Vdrive is drawn high, so as to realize overcurrent protection function.Sample rate current and output in this method
Electric current is directly proportional, and all by sampling resistor R1 with flowing to chip, therefore as output current increases, the static state of chip ground terminal
Electric current also increases, and adds the quiescent dissipation of chip.
The content of the invention
In order to solve the above-mentioned technical problem, compare it is an object of the invention to provide a kind of utilization electric current and realize overcurrent protection
The current foldback circuit of low pressure difference linear voltage regulator, the current foldback circuit can reduce the quiescent dissipation of chip.
The technical solution adopted in the present invention is：A kind of current foldback circuit of low pressure difference linear voltage regulator, with low voltage difference
Linear voltage regulator is connected and overcurrent protection is carried out to it, and described low pressure difference linear voltage regulator includes voltage input end, source electrode
The power tube being connected with voltage input end, the driving voltage end being connected with the grid of power tube, the drain electrode phase with power tube
The voltage output end of connection,
The current foldback circuit of the low pressure difference linear voltage regulator includes grid, drain electrode and the power tube of grid and power tube
The sampling pipe that is respectively connected with of drain electrode, first input end is connected with voltage input end, the source of the second input and sampling pipe
The current comparison circuit that pole is connected, the overcurrent protection execution circuit that input is connected with the output end of current comparison circuit,
The output end of overcurrent protection execution circuit is connected with driving voltage end.
Further, the current comparison circuit includes first resistor, second resistance, the first PNP pipe, the second PNP pipe, is
First PNP pipe and the second PNP pipe provide 1:The bias current circuit of 1 bias current, the upper end of the first resistor with
The upper end of second resistance is connected, the upper end of the second resistance as current comparison circuit first input end, described first
The lower end of resistance is used as the second input of current comparison circuit, the emitter stage of the lower end of the first resistor and the first PNP pipe
It is connected, the base stage of first PNP pipe is connected with the base stage of the second PNP pipe, the base stage and colelctor electrode of first PNP pipe
It is connected, the emitter stage of second PNP pipe and the lower end of second resistance are connected, and the colelctor electrode of second PNP pipe is used as electricity
The output end of comparison circuit is flowed, the first output end of the bias current circuit is connected with the colelctor electrode of the first PNP pipe, it is described inclined
The second output end for putting current circuit is connected with the colelctor electrode of the second PNP pipe.
Further, the overcurrent protection execution circuit includes the current collection at the first bias current end, grid and the second PNP pipe
The first NPN that the first NMOS tube that pole is connected, the second NMOS tube, the first PMOS, emitter stage are connected with driving voltage end
Pipe, the drain electrode of first NMOS tube is connected with the first bias current end, the source electrode and the 2nd NMOS of first NMOS tube
The source electrode of pipe is connected, and the grid of second NMOS tube is connected with the drain electrode of the first NMOS tube, second NMOS tube
Grid is connected with the grid of the first PMOS, and the drain electrode of second NMOS tube is connected with the drain electrode of the first PMOS, institute
The drain electrode for stating the second NMOS tube is connected with the base stage of the first NPN pipes, the colelctor electrodes of the first NPN pipes and the first PMOS
Source electrode is connected, and the source electrode of first PMOS is connected with voltage input end.
Further, the bias current circuit includes the second bias current end, biased electrical pressure side, drain electrode and the second biasing
The 5th NMOS that the 3rd NMOS tube that current terminal is connected, the 4th NMOS tube, drain electrode are connected with the colelctor electrode of the first PNP pipe
The source of the 7th NMOS tube, source electrode and the first NMOS tube that pipe, the 6th NMOS tube, drain electrode are connected with the colelctor electrode of the second PNP pipe
The 8th NMOS tube that pole is connected, the source electrode of the 3rd NMOS tube is connected with the drain electrode of the 4th NMOS tube, and the described 4th
The grid of NMOS tube is connected with the second bias current end, and the grid of the 3rd NMOS tube is connected with biased electrical pressure side, institute
The grid for stating the 3rd NMOS tube is connected with the grid of the 5th NMOS tube, the source electrode of the 5th NMOS tube and the 6th NMOS tube
Drain electrode is connected, and the grid of the 6th NMOS tube is connected with the grid of the 4th NMOS tube, the grid of the 6th NMOS tube
It is connected with the grid of the 8th NMOS tube, the drain electrode of the 8th NMOS tube is connected with the source electrode of the 7th NMOS tube, described
The grid of seven NMOS tubes is connected with the grid of the 5th NMOS tube, the 4th NMOS tube, the 6th NMOS tube, the 8th NMOS tube
Source ground.
Further, the power tube and sampling pipe are the proportional PMOS of breadth length ratio.
The beneficial effects of the invention are as follows：A kind of sampling pipe of the current foldback circuit of low pressure difference linear voltage regulator of the present invention is adopted
Sample output current, current comparison circuit realizes that excessively stream judges by way of electric current compares, and overcurrent protection execution circuit was realized
Stream protection, circuit structure of the invention is simple, is that excessively stream can be achieved to judge without using comparator, and by by sampling pipe and work(
The drain electrode of rate pipe is connected on voltage output end VOUT so that sample rate current is flowed to outside chip with output current, does not flow to chip
Ground, therefore smaller chip ground terminal quiescent current can be achieved under various output currents, significantly reduce the quiet of chip
State power consumption.
Brief description of the drawings
The embodiment to the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is the circuit theory diagrams of prior art；
Fig. 2 is a kind of circuit theory diagrams of the current foldback circuit of low pressure difference linear voltage regulator of the invention；
Fig. 3 is an a kind of physical circuit schematic diagram of the current foldback circuit of low pressure difference linear voltage regulator of the invention.
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.
A kind of current foldback circuit of low pressure difference linear voltage regulator, is connected with low pressure difference linear voltage regulator and it is carried out
Overcurrent protection, with reference to Fig. 2, Fig. 2 is a kind of circuit theory diagrams of the current foldback circuit of low pressure difference linear voltage regulator of the invention, institute
The low pressure difference linear voltage regulator stated include the power tube MP that voltage input end VIN, source electrode be connected with voltage input end VIN, with
Driving voltage end Vdrive that power tube MP grid is connected, the voltage output end being connected with power tube MP drain electrode
VOUT,
The current foldback circuit of the low pressure difference linear voltage regulator includes grid, drain electrode and the power of grid and power tube MP
The sampling pipe MS that pipe MP drain electrode is respectively connected with, first input end is connected with voltage input end VIN, the second input is with adopting
The current comparison circuit that sample pipe MS source electrode is connected, the overcurrent protection that input is connected with the output end of current comparison circuit
Execution circuit, the output end of overcurrent protection execution circuit is connected with driving voltage end Vdrive.
Sample rate current Isample is simultaneously delivered to current comparison circuit by sampling pipe MS sampled output currents IOUT, and electric current compares
Circuit is by comparing sample rate current Isample and predetermined current size to produce different data signals, the different number
Word signal inputs overcurrent protection execution circuit, and when sample rate current Isample is less than predetermined current, overcurrent protection execution circuit is not
Conducting；When sample rate current Isample is more than predetermined current, the conducting of overcurrent protection execution circuit makes power tube MP grid voltage
Increase, so that the output current IO UT for limiting low pressure difference linear voltage regulator continues to increase, realizes overcurrent protection.The present invention is by inciting somebody to action
Sampling pipe MS and power tube MP drain electrode is connected on voltage output end VOUT so that sample rate current Isample and output current
IOUT is flowed to outside chip, chip is not flow to, therefore the achievable smaller ground terminal Static Electro under various output currents
Stream, significantly reduces the quiescent dissipation of chip.
As the further improvement of technical scheme, with reference to Fig. 2, Fig. 2 is a kind of mistake of low pressure difference linear voltage regulator of the invention
Flow protection circuit circuit theory diagrams, the current comparison circuit include first resistor R1, second resistance R2, the first PNP pipe Q1,
Second PNP pipe Q2, it is that the first PNP pipe Q1 and the second PNP pipe Q2 provide 1:The bias current circuit of 1 bias current, institute
The upper end for stating first resistor R1 is connected with second resistance R2 upper end, and the upper end of the second resistance R2 is more electric as electric current
The first input end on road, the lower end of the first resistor R1 is used as the second input of current comparison circuit, the first resistor
R1 lower end is connected with the first PNP pipe Q1 emitter stage, the base stage of the first PNP pipe Q1 and the second PNP pipe Q2 base stage
It is connected, the base stage of the first PNP pipe Q1 is connected with colelctor electrode, the emitter stage and second resistance of the second PNP pipe Q2
R2 lower end connection, the colelctor electrode of the second PNP pipe Q2 is used as the output end of current comparison circuit, the bias current circuit
The first output end 1 be connected with the first PNP pipe Q1 colelctor electrode, the second output end 2 of the bias current circuit and the 2nd PNP
Pipe Q2 colelctor electrode connection.
In the present embodiment, output current IO UT flows to voltage output end from voltage input end VIN by power tube MP
VOUT, sampling pipe MS obtain sample rate current Isample, Isample=IOUT/ with certain proportion n sampled output current IOUT
n.Sample rate current Isample produces pressure drop Vsample=Isample*R1 when flowing through resistance R1.First PNP pipe Q1 and the 2nd PNP
Pipe Q2 constitutes PNP mirror image pipes, and bias current circuit provides bias current for PNP mirror image pipes.When Iout is smaller, Vsample
Smaller, the A point voltages VA in Fig. 2 is higher, and the B point voltages VB in Fig. 2 is also higher, therefore the second PNP pipe Q2 base-emitter
Voltage VBE is smaller, and the second PNP pipe Q2 collector current IC is also smaller, when the second PNP pipe Q2 collector current IC is less than partially
When putting the bias current of current circuit generation, the C points output low level in Fig. 2, overcurrent protection execution circuit is not turned on, not shadow
Ring Vdrive state；With IOUT increase, Vsample increases, and the A point voltages VA in Fig. 2 reduces, the B point voltages in Fig. 2
VB also reduces, the second PNP pipe Q2 base emitter voltage VBE increases, the second PNP pipe Q2 collector current IC increases, when
When second PNP pipe Q2 collector current IC is more than the bias current that bias current circuit is produced, the high electricity of C points output in Fig. 2
Flat, simultaneously output voltage draws high Vdrive to the conducting of overcurrent protection execution circuit, reduction power tube MP grid-source voltage VGS,
So as to limit output current IO UT continuation increase, play a part of overcurrent protection.
In the above-mentioned course of work, because sample rate current Isample is flowed to by sampling pipe MS and voltage output end VOUT
Outside piece, therefore do not increase the ground terminal quiescent current of chip, reduce the quiescent dissipation of chip.
As the further improvement of technical scheme, the power tube MP and sampling pipe MS are the proportional PMOS of breadth length ratio
Pipe.So, sampling pipe MS can be achieved with certain proportion n sampled power pipes MP electric current, i.e. output current IO UT.Certain ratio
Example n is the ratio between power tube MP and sampling pipe MS breadth length ratio.
As the further improvement of technical scheme, with reference to Fig. 3, Fig. 3 is a kind of mistake of low pressure difference linear voltage regulator of the invention
Flow protection circuit a physical circuit schematic diagram, the overcurrent protection execution circuit include the first bias current end Ib1, grid with
The first NMOS tube N1, the second NMOS tube N2, the first PMOS M1, emitter stage and drive that second PNP pipe Q2 colelctor electrode is connected
The first NPN pipe Q3 that dynamic voltage end Vdrive is connected, the drain electrode of the first NMOS tube N1 and the first bias current end Ib1 phases
Connection, the source electrode of the first NMOS tube N1 is connected with the second NMOS tube N2 source electrode, the grid of the second NMOS tube N2
Drain electrode with the first NMOS tube N1 is connected, and the grid of the second NMOS tube N2 is connected with the first PMOS M1 grid,
The drain electrode of the second NMOS tube N2 is connected with the first PMOS M1 drain electrode, the drain electrode and first of the second NMOS tube N2
NPN pipes Q3 base stage is connected, and the colelctor electrode of the first NPN pipes Q3 is connected with the first PMOS M1 source electrode, and described
One PMOS M1 source electrode is connected with voltage input end VIN.
In the present embodiment, when the second PNP pipe Q2 collector current IC is less than the biased electrical that bias current circuit is produced
C points in stream, Fig. 3 are low level, and the first NMOS tube N1 is output as high level, the first PMOS M1 and the second NMOS tube N2 compositions
Phase inverter output low level, the first NPN pipes Q3 shut-off, driving voltage end Vdrive signal is not influenceed；As the second PNP pipe Q2
Collector current IC when being more than the bias current that bias current circuit is produced, the C points in Fig. 3 are changed into high level from low level,
First NPN pipes Q3 outputs are changed into the phase inverter output high level of low level, the first PMOS M1 and the second NMOS tube N2 compositions, the
One NPN pipes Q3 is turned on, and is drawn high power tube MP driving voltage by the first NPN pipes Q3 base emitter voltage VBE, is subtracted
Small power tube MP grid-source voltage VGS, continues to increase, realizes overcurrent protection so as to limit output current IO UT.
As the further improvement of technical scheme, with reference to Fig. 3, Fig. 3 is a kind of mistake of low pressure difference linear voltage regulator of the invention
A physical circuit schematic diagram of protection circuit is flowed, the bias current circuit includes the second bias current end Ib2, biased electrical pressure side
The 3rd NMOS tube N3, the 4th NMOS tube N4, drain electrode and the first PNP that Vbias, drain electrode are connected with the second bias current end Ib2
The 5th NMOS tube N5 that pipe Q1 colelctor electrode is connected, the 6th NMOS tube N6, drain electrode are connected with the second PNP pipe Q2 colelctor electrode
The 7th NMOS tube N7, source electrode the 8th NMOS tube N8, the 3rd NMOS tube N3 that are connected with the first NMOS tube N1 source electrode
Source electrode be connected with the 4th NMOS tube N4 drain electrode, the grid of the 4th NMOS tube N4 and the second bias current end Ib2 phases
Connection, the grid of the 3rd NMOS tube N3 is connected with biased electrical pressure side Vbias, the grid of the 3rd NMOS tube N3 and the
Five NMOS tube N5 grid is connected, and the source electrode of the 5th NMOS tube N5 is connected with the 6th NMOS tube N6 drain electrode, described
6th NMOS tube N6 grid is connected with the 4th NMOS tube N4 grid, the grid and the 8th NMOS of the 6th NMOS tube N6
Pipe N8 grid is connected, and the drain electrode of the 8th NMOS tube N8 is connected with the 7th NMOS tube N7 source electrode, and the described 7th
NMOS tube N7 grid is connected with the 5th NMOS tube N5 grid, the 4th NMOS tube N4, the 6th NMOS tube N6, the 8th
NMOS tube N8 source ground.
In the present embodiment, the 3rd NMOS tube N3 and the 4th NMOS tube N4, the 5th NMOS tube N5 and the 6th NMOS tube N6,
Seven NMOS tube N7 and the 8th NMOS tube N8 composition cascode structures are that the first PNP pipe Q1 and the second PNP pipe Q2 are provided accurately
1:1 bias current.
Above is the preferable implementation to the present invention is illustrated, but the invention is not limited to the implementation
Example, those skilled in the art can also make a variety of equivalent variations or replace on the premise of without prejudice to spirit of the invention
Change, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (5)
1. a kind of current foldback circuit of low pressure difference linear voltage regulator, is connected with low pressure difference linear voltage regulator and it was carried out
Stream protection, described low pressure difference linear voltage regulator include voltage input end, the power tube that source electrode is connected with voltage input end, with
Driving voltage end that the grid of power tube is connected, the voltage output end being connected with the drain electrode of power tube, it is characterised in that
The current foldback circuit of the low pressure difference linear voltage regulator includes grid, drain electrode and the leakage of power tube of grid and power tube
The sampling pipe that pole is respectively connected with, outside sample rate current pio chip, will reduce the quiescent dissipation of chip, first input end and electricity
Pressure input is connected, the current comparison circuit that the second input is connected with the source electrode of sampling pipe, and input is compared with electric current
The overcurrent protection execution circuit that the output end of circuit is connected, the output end of overcurrent protection execution circuit is connected with driving voltage end
Connect.
2. a kind of current foldback circuit of low pressure difference linear voltage regulator according to claim 1, it is characterised in that the electricity
Flow comparison circuit include first resistor, second resistance, the first PNP pipe, the second PNP pipe, be first PNP pipe and the 2nd PNP
Pipe provides 1:The bias current circuit of 1 bias current, the upper end of the first resistor is connected with the upper end of second resistance, institute
The upper end of second resistance is stated as the first input end of current comparison circuit, the lower end of the first resistor is more electric as electric current
Second input on road, the lower end of the first resistor is connected with the emitter stage of the first PNP pipe, the base of first PNP pipe
Pole is connected with the base stage of the second PNP pipe, and the base stage of first PNP pipe is connected with colelctor electrode, the hair of second PNP pipe
The lower end connection of emitter-base bandgap grading and second resistance, the colelctor electrode of second PNP pipe as current comparison circuit output end, it is described partially
The first output end for putting current circuit is connected with the colelctor electrode of the first PNP pipe, the second output end of the bias current circuit with
The colelctor electrode connection of second PNP pipe.
3. a kind of current foldback circuit of low pressure difference linear voltage regulator according to claim 2, it is characterised in that the mistake
Stream protection execution circuit includes the first NMOS tube that the first bias current end, grid be connected with the colelctor electrode of the second PNP pipe, the
The first NPN pipes that two NMOS tubes, the first PMOS, emitter stage are connected with driving voltage end, the drain electrode of first NMOS tube
It is connected with the first bias current end, the source electrode of first NMOS tube is connected with the source electrode of the second NMOS tube, described second
The grid of NMOS tube is connected with the drain electrode of the first NMOS tube, the grid of second NMOS tube and the grid phase of the first PMOS
Connection, the drain electrode of second NMOS tube is connected with the drain electrode of the first PMOS, the drain electrode and first of second NMOS tube
The base stage of NPN pipes is connected, and the colelctor electrode of the first NPN pipes is connected with the source electrode of the first PMOS, the first PMOS
The source electrode of pipe is connected with voltage input end.
4. the current foldback circuit of a kind of low pressure difference linear voltage regulator according to claim 3, it is characterised in that described inclined
Put the 3rd NMOS that current circuit is connected including the second bias current end, biased electrical pressure side, drain electrode with the second bias current end
Pipe, the 4th NMOS tube, the 5th NMOS tube being connected with the colelctor electrode of the first PNP pipe that drains, the 6th NMOS tube, drain electrode and second
The 8th NMOS tube that the 7th NMOS tube that the colelctor electrode of PNP pipe is connected, source electrode are connected with the source electrode of the first NMOS tube, it is described
The source electrode of 3rd NMOS tube is connected with the drain electrode of the 4th NMOS tube, the grid of the 4th NMOS tube and the second bias current end
It is connected, the grid of the 3rd NMOS tube is connected with biased electrical pressure side, the grid and the 5th NMOS of the 3rd NMOS tube
The grid of pipe is connected, and the source electrode of the 5th NMOS tube is connected with the drain electrode of the 6th NMOS tube, the 6th NMOS tube
Grid is connected with the grid of the 4th NMOS tube, and the grid of the 6th NMOS tube is connected with the grid of the 8th NMOS tube, institute
The drain electrode for stating the 8th NMOS tube is connected with the source electrode of the 7th NMOS tube, the grid of the 7th NMOS tube and the 5th NMOS tube
Grid is connected, the 4th NMOS tube, the 6th NMOS tube, the source ground of the 8th NMOS tube.
5. a kind of current foldback circuit of low pressure difference linear voltage regulator according to any one of Claims 1-4, its feature exists
In the power tube and sampling pipe are the proportional PMOS of breadth length ratio.
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| CN201610362624.7A CN106020317B (en) | 2016-05-26 | 2016-05-26 | A kind of current foldback circuit of low pressure difference linear voltage regulator |
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| CN201610362624.7A CN106020317B (en) | 2016-05-26 | 2016-05-26 | A kind of current foldback circuit of low pressure difference linear voltage regulator |
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| CN106020317B true CN106020317B (en) | 2017-09-29 |
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| CN107085448B (en) * | 2017-06-26 | 2018-09-11 | 中国电子科技集团公司第五十八研究所 | Include the low pressure difference linear voltage regulator LDO circuit of overcurrent protection |
| CN108768360A (en) * | 2018-08-22 | 2018-11-06 | 苏州华芯微电子股份有限公司 | A kind of current foldback circuit |
| CN109765957A (en) * | 2019-01-07 | 2019-05-17 | 上海奥令科电子科技有限公司 | A kind of low pressure difference linear voltage regulator |
| CN110377102A (en) * | 2019-07-10 | 2019-10-25 | 深圳市锐能微科技有限公司 | A kind of low-dropout linear voltage-regulating circuit and integrated circuit |
| CN116488621B (en) * | 2023-02-27 | 2023-11-03 | 江苏帝奥微电子股份有限公司 | Wide voltage domain level comparison circuit suitable for high-voltage LDO |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| ITTO20030533A1 (en) * | 2003-07-10 | 2005-01-11 | Atmel Corp | PROCEDURE AND CIRCUIT FOR CURRENT LIMITATION IN |
| US7602162B2 (en) * | 2005-11-29 | 2009-10-13 | Stmicroelectronics Pvt. Ltd. | Voltage regulator with over-current protection |
| US20080030177A1 (en) * | 2006-08-01 | 2008-02-07 | Hung-I Chen | Soft-start circuit of linear voltage regulator and method thereof |
| CN100589058C (en) * | 2007-12-27 | 2010-02-10 | 北京中星微电子有限公司 | Current limitation circuit as well as voltage regulator and DC-DC converter including the same |
| TWI357204B (en) * | 2008-09-25 | 2012-01-21 | Advanced Analog Technology Inc | A low drop out regulator with over-current protect |
| US8169202B2 (en) * | 2009-02-25 | 2012-05-01 | Mediatek Inc. | Low dropout regulators |
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