CN113157042A - Quick start voltage stabilizing circuit with bias priority intervention - Google Patents
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- CN113157042A CN113157042A CN202110545019.4A CN202110545019A CN113157042A CN 113157042 A CN113157042 A CN 113157042A CN 202110545019 A CN202110545019 A CN 202110545019A CN 113157042 A CN113157042 A CN 113157042A
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
本发明提出了一种带偏置级优先干预的快速启动稳压电路，可在输入供电电压瞬时上电时快速启动从而进入正常稳压工作状态，其特点是，输入的供电电压通过N(N>1)级梯度降压环节、偏置级启动环节、偏置级环节、尾稳压输出环节、偏置级输出环节进行处理，最终在得到稳定的输出供电电压的同时可以为其它集成电路模块提供初步的基准电压和偏置电流。本发明采用模块化设计增加N级梯度降压环节避免了外部高压对内部电路的损害，同时转化为低压范围供电利于电路性能优化，提高了宽范围大电压领域应用的能力，偏置级环节优先干预尾稳压输出环节在提高了启动速度的同时保证了尾稳压输出环节的精确度。
The present invention proposes a fast-start voltage-stabilizing circuit with bias-level priority intervention, which can start quickly when the input power supply voltage is instantaneously powered on to enter a normal voltage-stabilizing working state, and is characterized in that the input power supply voltage passes through N(N >1) The step gradient step-down link, the bias stage start-up link, the bias stage link, the tail voltage regulator output link, and the bias stage output link are processed, and finally a stable output power supply voltage can be obtained for other integrated circuit modules. Provides preliminary reference voltage and bias current. The invention adopts a modular design to increase the N-level gradient step-down link to avoid the damage to the internal circuit caused by the external high voltage, and at the same time converts into a low-voltage range power supply to optimize circuit performance, and improves the ability to apply in a wide range and large voltage field, and the bias level link is given priority. Intervening the tail voltage regulator output link improves the start-up speed and at the same time ensures the accuracy of the tail voltage regulator output link.
Description
Technical Field
The invention belongs to the field of analog integrated circuits, relates to a rapid start voltage stabilizing circuit, and particularly relates to a rapid start voltage stabilizing circuit with bias priority intervention.
Background
With the continuous development of personal consumer electronics, communication equipment and automotive electronics, higher requirements are put forward on the rapid start of the voltage stabilizing circuit and the performances of the stability, accuracy and the like of the output voltage of the voltage stabilizing circuit at the internal power supply end. The voltage stabilizing circuit can be divided into electronic voltage stabilization, electromagnetic conversion voltage stabilization and digital control voltage stabilization. The simple electronic voltage stabilizing circuit can be obtained by connecting a resistor and a diode in series, and the voltage on the diode only slightly changes when the input current changes, so that the purpose of outputting stable voltage is achieved, but the accuracy of the output voltage is not high. Then, an electronic voltage regulator circuit with a negative feedback structure is further developed on the basis of simple electronic voltage regulation, the actual feedback voltage and the fixed reference voltage are compared firstly, the error value is amplified and then sent to a voltage regulation element, and the output is regulated to reduce the error value, so that a negative feedback control loop is formed. The accuracy of voltage control can be further improved by increasing the open loop gain but the stability of the system is reduced, so that a trade-off between stability and response speed to variations is required. The electromagnetic conversion type voltage stabilization is generally mainly applied to an alternating current voltage stabilizing circuit, and a magnetic element is used for performing electromagnetic conversion to complete final voltage stabilization output. The digital control type voltage stabilization belongs to an active control type system, the working principle of the digital control type voltage stabilization system is the same as that of a general electronic voltage stabilizing circuit, but the system enters an active detection and control structure. The digital control type voltage stabilizing circuit comprises a diode, a capacitor, a resistor, a potentiometer and a microcontroller, can be integrated in a small PCB or further highly integrated in a chip, is generally matched with a detected target to form positive and quick sensor feedback parameters for positive adjustment, and quickly provides stable output power supply voltage for a target circuit or equipment. Due to the diversification and enrichment of the application fields of various electronic products, the higher voltage input scene becomes a factor that must be considered nowadays. On the other hand, the improvement of the overall starting speed of the electronic product is bound and depends on the starting speed of the voltage stabilizing circuit at the internal power supply end to a great extent.
For example: referring to fig. 1, a patent application with publication number CN 107656570 a and name "a soft start voltage stabilizing circuit" discloses a soft start voltage stabilizing circuit mainly composed of a transformer T, a diode rectifier U, a triode VT4, a resistor R3, a resistor R4, a capacitor C1, a capacitor C4, a diode D2, a diode D3, a soft start processing circuit, a source constant current driving circuit and a delay start circuit. Wherein, a capacitor C1 with the positive output end of the rectifier U connected and the negative output end of the diode rectifier U connected, a soft start processing circuit respectively connected with the positive electrode and the negative electrode of the capacitor C1, a capacitor C4 with the positive electrode connected with the soft start processing circuit and the negative electrode connected with the negative electrode of the capacitor C1, a resistor R3 with one end connected with the positive electrode of the capacitor C4 and the other end connected with the base electrode of the triode VT4, a diode D2 with the P electrode connected with the negative electrode of the capacitor C4 and the N electrode connected with the emitter electrode of the triode VT4, a delay start circuit respectively connected with the emitter electrode of the triode VT4 and the P electrode of the diode D2, and a source constant current driving circuit respectively connected with the negative electrode of the capacitor C1 and the delay start circuit, and diode D3 whose P pole is connected with delay starting circuit and N pole is connected with collector of triode VT4 through resistor R4; the two ends of a primary side inductance coil of the transformer T form a power supply input end, one input end of the diode rectifier U is connected with the non-homonymous end of a secondary side inductance coil of the transformer T, and the other input end of the diode rectifier U is connected with the homonymous end of the secondary side inductance coil of the transformer T; the N-pole of the diode D3 is connected to the soft start processing circuit. The method for starting the rear-stage circuit or equipment by mainly using the transformer T, the diode rectifier U, the triode VT4 and other elements to generate the stable output voltage value at a slower speed in a starting process after the input power supply voltage is electrified can avoid the high-voltage damage of the input power supply voltage to the internal circuit to a certain extent, but the stable output voltage is longer in establishment time due to the existence of the slower starting process, so that the working effect of the rear-stage circuit or equipment is limited; meanwhile, the application of the circuit designed by the method is limited because the internal circuit uses a transformer element, and further integration is difficult to realize.
The following steps are repeated: referring to fig. 2, application publication No. CN 112135394 a, entitled "a constant current LED driving circuit capable of voltage-dropping", discloses a constant current LED driving circuit capable of voltage-dropping, which includes an input circuit, a voltage-boosting/dropping circuit, an output circuit and a control circuit, wherein the voltage-boosting/dropping circuit includes a voltage-boosting voltage-stabilizing circuit and a voltage-dropping voltage-stabilizing circuit, the input circuit is connected with the voltage-boosting/dropping circuit, the voltage-boosting/dropping circuit is connected with the output circuit, the output circuit is connected with an LED lamp, the LED lamp is connected with the control circuit, and the control circuit is connected with the voltage-boosting/dropping circuit. The voltage reduction and stabilization circuit comprises a second MOS tube, a first diode and a second inductor, wherein a first pin to a third pin of the second MOS tube are connected with one ends of the input circuit and the eighth resistor, a fourth pin of the second MOS tube is connected with the control circuit and the other end of the eighth resistor respectively, a fifth pin to an eighth pin of the second MOS tube are connected with one end of the first diode and one end of the second inductor, the other end of the second inductor is connected with the voltage boost and stabilization circuit, and the other end of the first diode is grounded. The invention mainly uses MOS tube, diode and inductance to form the voltage stabilizing output circuit, because there is no transformer element in it, it is beneficial to optimize the circuit structure further and realize high integration, but because there is no voltage reducing protection structure of input power supply voltage in it, the voltage stabilizing output circuit designed by the invention is difficult to be applied to higher input power supply voltage and is limited; meanwhile, the voltage stabilizing output circuit formed by the MOS tube, the diode, the inductor and other elements in the internal circuit has no feedback control structure, so that the output voltage has low accuracy and poor stability, and the application of the voltage stabilizing circuit designed by the method is limited.
Disclosure of Invention
The invention aims to solve the technical problem of providing a rapid start voltage stabilizing circuit with wide voltage input range, high output accuracy, high output stability and high start speed aiming at the defects of the prior art.
The technical problem to be solved by the invention is realized by the following technical scheme: a fast start voltage stabilizing circuit with bias priority intervention can be started quickly when input power supply voltage is electrified instantly so as to enter a normal voltage stabilizing working state.
The invention specifically comprises an N (N >1) grade gradient voltage reduction link 1, an offset grade starting link 2, an offset grade link 3, a tail voltage stabilization output link 4 and an offset grade output link 5, wherein: the N-level gradient voltage reduction link 1 is configured to perform multi-level voltage reduction processing on the input power supply voltage VIN; the first output end outputs a 1 st-stage voltage reduction signal V1; the second output end outputs an Nth-stage buck signal VN; the bias level starting link 2 is used for starting the bias level link 3 to enable the bias level link 3 to be rapidly separated from a static state of zero current, and the input end of the bias level starting link is connected with a level 1 buck signal V1; the power supply is provided with two output ends, wherein the first output end outputs a starting voltage A, and the second output end outputs a starting voltage B; the bias stage link 3 is used for quickly generating a reference voltage VB and is provided with three input ends and two output ends, the first input end is connected with a 1 st-stage buck signal V1, the second input end is connected with a starting voltage A, the third input end is connected with a starting voltage B, the output end of the first output end outputs a bias voltage VB and is connected to the tail voltage stabilization output link 4, and the output end of the second output end outputs a bias voltage VB2 and is connected to the bias stage output link 5; the tail voltage stabilization output link 4 is used for generating stable output power supply voltage and is provided with four input ends and an output end, wherein the first input end is connected with a 1 st-level voltage reduction signal V1, the second input end is connected with an Nth-level voltage reduction signal VN, the third input end is connected with a bias voltage VB, and the fourth input end is connected with a starting voltage A; the output end is used as a first output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a supply voltage VOUT; the bias stage output link 5 is used for generating an output reference voltage VBO and a bias current IBO, and is provided with three input ends and two output ends, wherein the first input end is connected with a starting voltage a, the second input end is connected with a 1 st-stage step-down signal V1, and the third input end is connected with a bias voltage VB 2; the first output end is used as a second output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the reference voltage VBO, and the second output end is used as a third output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the bias current IBO.
The N-level gradient buck link 1 includes N (N >1) voltage dividing resistors, namely a first voltage dividing resistor RS1, a second voltage dividing resistor RS2, an nth voltage dividing resistor RSN, N buck NMOS transistors, namely a first buck NMOS 1, a second buck NMOS transistor MNS2, an nth buck NMOS transistor MNSN, and three buck diodes, namely a first buck diode Z1, a second buck diode Z2, and a third buck diode Z3; wherein: the N voltage-reducing NMOS tubes MNS 1-MNSN are sequentially connected in series, the drain electrode of a first voltage-reducing NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first voltage-reducing NMOS tube MNS1 is connected with the drain electrode of a second voltage-reducing NMOS tube MNS2 and serves as the first output end of the N-level gradient voltage-reducing link 1, and a 1 st-level voltage-reducing signal V1 is output, the source electrode of the second voltage-reducing NMOS tube MNS2 is connected with the drain electrode of a third voltage-reducing NMOS tube MNS3, the same goes, the like, the source electrode MNSN-1 of the N-1 voltage-reducing NMOS tube is connected with the drain electrode of the N-level voltage-reducing NMOS tube MNSN, and the source electrode of the N-level voltage-reducing NMOS tube MNSN serves as the second output end of the N-level gradient voltage-reducing link 1, and the N-level voltage-reducing signal VN is output; the N voltage-dividing resistors RS 1-RSN are sequentially connected in series to form a series circuit, one end of a first voltage-dividing resistor RS1 is connected with the drain electrode of a first voltage-reducing NMOS tube MNS1, the common end of the first voltage-dividing resistor RS1 and the common end of a second voltage-dividing resistor RS2 are connected with the grid electrode of a first voltage-reducing NMOS tube MNS1, the common end of a second voltage-dividing resistor RS2 and the common end of a third voltage-dividing resistor RS3 are connected with the grid electrode of a second voltage-reducing NMOS tube MNS2, the same way, and so on, the common end of an N-1 voltage-dividing resistor RSN-1 and the common end of an N voltage-dividing resistor RSN are connected with the grid electrode of an N-1 voltage-reducing NMOS tube MNSN-1, and the other end of the N voltage-dividing resistor RSN is connected with the grid electrode of an N voltage-reducing NMOS tube MNN; the three voltage-stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage-stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage-reducing NMOS tube, the positive end of the first voltage-stabilizing diode Z1 is connected with the negative end of the second voltage-stabilizing diode Z2, the positive end of the second voltage-stabilizing diode Z2 is connected with the negative end of the third voltage-stabilizing diode Z3, and the positive end of the third voltage-stabilizing diode Z3 is connected with GND.
The bias stage starting link 2 comprises a resistor seventh resistor R7, and two NPN transistors, namely a tenth NPN transistor Q10 and an eleventh NPN transistor Q11; wherein: one end of the seventh resistor R7 serving as an input end of the bias stage starting link 2 is connected to the 1 st-stage buck signal V1, the other end of the seventh resistor R7 is connected to a base of the tenth NPN transistor Q10 and a collector of the eleventh NPN transistor Q11, an emitter of the tenth NPN transistor Q10 and an emitter of the eleventh NPN transistor Q11 are both connected to GND, and a collector of the tenth NPN transistor Q10 serving as a first output end of the bias stage starting link 2 outputs the starting voltage a; the base of the eleventh NPN transistor Q11 is used as the second output terminal of the bias stage starting link 2 to output the starting voltage B.
The bias stage link 3 includes four resistors, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, two NPN transistors, a twelfth NPN transistor Q12 and a thirteenth NPN transistor Q13, nine PMOS transistors, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-third PMOS transistor MP23, and six NMOS transistors, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth transistor MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor MN 15; wherein: the source electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the first input end serving as the bias stage link 3 and connected with the 1 st-stage buck signal V1, the grid electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the drain electrode of the eighteenth PMOS tube MP18, and the drain electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP 3538 are respectively connected with the source electrodes of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 to form a PMOS cascode current mirror; gates of seventeenth PMOS tubes MP17 to twenty-seventh PMOS tubes MP20 are connected and serve as a second input end of the bias stage link 3 to be connected with a starting voltage A, drains of the seventeenth PMOS tubes MP17 are connected with a starting voltage B through an eighth resistor R8, drains of eighteenth PMOS tubes MP18 are connected with the starting voltage A through a ninth resistor R9, drains of the nineteenth PMOS tubes MP19 are connected with drains of fourteenth NMOS tubes MN14, and drains of the twentieth PMOS tubes MP20 are connected with drains of a twelfth NMOS tube MN 12; the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11 and to the drain of the tenth NMOS transistor MN10, the drain of the tenth NMOS transistor MN10 is connected to the start voltage B as the third input terminal of the bias stage link 3, and the source thereof is connected to the collector of the twelfth NPN transistor Q12; the drain electrode of the eleventh NMOS tube MN11 is connected with the starting voltage A; the bases of the twelfth NPN transistor Q12 and the thirteenth NPN transistor Q13 are connected to the collector of the twelfth NPN transistor Q12, the emitter of the twelfth NPN transistor Q12 is connected to GND, and the emitter of the thirteenth NPN transistor Q13 is connected to GND through the tenth resistor R10; the gates of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are connected with each other and to the drain of a twelfth NMOS transistor MN12, the source of the twelfth NMOS transistor MN12 is connected with the drain of the twenty-third PMOS transistor MP23, and the gate and the drain of the twenty-third PMOS transistor MP23 are both connected to GND; the drain electrode of the thirteenth NMOS transistor MN13 is connected with the 1 st-stage buck signal V1 through the eleventh resistor R11, the source electrode of the thirteenth NMOS transistor MN 3578 is connected with the drain electrode of the fifteenth NMOS transistor MN15 and serves as the first output end of the biasing stage link 3 to output the biasing voltage VB; sources of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are both connected to GND, gates of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are connected and serve as a second output end of the bias stage link 3 to output bias voltage VB2, and a drain of the fourteenth NMOS transistor MN14 is connected with a gate of the fourteenth NMOS transistor.
The tail voltage stabilization output link 4 comprises four resistors, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, four PNP tubes, a first PNP tube Q1, a second PNP tube Q2, a fourth PNP tube Q4, a fifth PNP tube Q5, five NPN tubes, a third NPN tube Q3, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9, nine PMOS tubes, a first PMOS tube MP9, a second PMOS tube MP9, a third PMOS tube MP9, a fourth PMOS tube MP9, a fifth PMOS tube MP9, a sixth PMOS tube MP9, a seventh PMOS tube MP9, an eighth PMOS tube MP9, a ninth PMOS tube MP9, seven NMOS tubes, a third NMOS tube MN9, a fourth NMOS tube MN9, a fifth NMOS tube MN9, a sixth NMOS tube MN9, an eighth NMOS tube MN9, a ninth NMOS tube MN9, and a ninth NMOS tube MN 9; wherein: the first PNP tube Q1 and the second PNP tube Q2 form a current mirror structure, the emitters of the first PNP tube Q1 and the second PNP tube Q2 are both connected with the Nth-level buck signal VN, the bases of the first PNP tube VN 1 and the second PNP tube Q2 are connected with the collector of the first PNP tube Q1, the collector of the second PNP tube Q2 is connected with the base of the third NPN tube Q3, the collector of the third NPN tube Q3 serving as the second input end of the tail voltage stabilization output link 4 is connected with the Nth-level buck signal VN, and the emitter of the third NPN tube Q3 is connected with the voltage signal VC 1; sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are all connected to GND, and gates of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to form a current mirror structure; the drain electrode of a third NMOS tube MN3 is connected with the grid electrode of the third NMOS tube and is used as a fourth input end of the tail voltage stabilization output link 4 to be connected with the starting voltage A, the drain electrode of a fourth NMOS tube MN4 is connected with the collector electrode of a first PNP tube Q1, the drain electrode of a fifth NMOS tube MN5 is connected with the collector electrode of a second PNP tube Q2, and the drain electrode of a sixth NMOS tube MN6 is connected with a first PMOS tube MP 1; the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are all connected with an Nth-stage voltage reduction signal VN, and the grid electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to form a current mirror structure; the drain electrode of a first PMOS tube MP1 is connected with the grid electrode of the first PMOS tube MP1, the drain electrode of a second PMOS tube MP2 is connected with the drain electrode of a seventh NMOS tube MN7, the drain electrode of a third PMOS tube MP3 is connected with the collector electrode of a sixth NPN tube Q6, the drain electrode of a fourth PMOS tube MP4 is connected with the emitter electrode of the fourth NPN tube Q4 through a third resistor R3, and the drain electrode of a fifth PMOS tube MP5 is connected with the collector electrode of a ninth NPN tube Q9; the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and the grid electrode of the eighth NMOS transistor MN8, and the source electrode of the seventh NMOS transistor MN7 is connected with GND; the fourth PNP transistor Q4 and the fifth PNP transistor Q5 form a differential pair transistor input, the base of the fourth PNP transistor Q4 is used as the third input end of the tail voltage stabilization output link 4 to be connected with the bias voltage VB, and the collector of the fourth PNP transistor Q8926 is connected with the collector of the eighth NPN transistor Q8; the base electrode of the fifth PNP tube Q5 is connected with the feedback voltage VFB, the collector electrode of the fifth PNP tube Q5 is connected with the collector electrode of the seventh NPN tube Q7, and the emitter electrode of the fifth PNP tube Q5 is connected with the drain electrode of the fourth PMOS tube MP4 through a fourth resistor R4; bases of the sixth NPN tube Q6 and the seventh NPN tube Q7 are connected to form a current mirror structure, and emitters of the current mirror structure are connected to GND; a collector of a sixth NPN tube Q6 is connected with a base electrode of the sixth NPN tube Q6; the sources of the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are both connected with the Nth-stage voltage reduction signal VN, and the gates thereof are connected to form a current mirror structure; the drain of the sixth PMOS tube MP6 is connected with the grid thereof, and the drain of the sixth PMOS tube MP6 is connected with the drain of the ninth NMOS tube MN9 and is connected with a voltage signal VC 1; the gates of the eighth NPMOS transistor MP8 and the ninth NMOS transistor MN9 are connected with each other and the drain of the seventh NMOS transistor MN 7; the drain of the eighth NPMOS transistor MP8 is connected to the drain of the sixth PMOS transistor MP6, and the source thereof is connected to the collector of the seventh NPN transistor Q7; the source electrode of the ninth NMOS transistor MN9 is connected with the collector electrode of the eighth NPN transistor Q8; the bases of the eighth NPN tube Q8 and the ninth NPN tube Q9 are connected to form a current mirror structure, and the emitters of the current mirror structure are connected to GND; a collector of the ninth NPN tube Q9 is connected with a base electrode of the ninth NPN tube Q9; the gate of the eighth PMOS transistor MP8 is connected to the voltage signal VC1, the drain thereof is connected to GND, and the source thereof is connected to the nth step-down signal VN; the gate of the ninth PMOS transistor MP9 is connected to the nth-stage step-down signal VN, the source thereof is connected to the 1 st-stage step-down signal V1 as the first input terminal of the tail voltage-stabilized output link 4, and the drain thereof is used as the output terminal of the tail voltage-stabilized output link 4 to output the supply voltage VOUT; the fifth resistor R5 and the sixth resistor R6 are connected in series and bridged between the drain of the ninth PMOS transistor MP9 and GND, and the common end of the fifth resistor R5 and the sixth resistor R6 is connected with the feedback voltage VFB.
The bias stage output link 5 comprises two resistors, namely a twelfth resistor R12, a thirteenth resistor R13, a fourteenth PNP transistor Q14, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, and a sixteenth NMOS transistor MN 16; wherein: the sources of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected, the second input end of the bias stage output link 5 is connected with the 1 st-stage buck signal V1, and the gates of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected with the drain of the bias stage output link 5; the drain of a fourteenth PMOS tube MP14 is connected with the source of the twenty-first PMOS tube MP21, and the drain of a fifteenth PMOS tube MP15 is connected with the source of the twenty-second PMOS tube MP 22; the gates of the twenty-first PMOS transistor MP21 and the twenty-second PMOS transistor MP22 are connected, the first input end of the bias stage output link 5 is connected to the starting voltage a, the drain of the twenty-first PMOS transistor MP21 is used as the third output end of the bias stage output link 5, and the bias current IBO is output; the drain of the twenty-second PMOS transistor MP22 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the emitter of the fourteenth PNP transistor Q14 through the thirteenth resistor R13; a common end of the twelfth resistor R12 and the thirteenth resistor R13 serves as a second output end of the bias stage output link 5 and outputs a reference voltage VBO; the base electrode and the collector electrode of the fourteenth PNP tube Q14 are both connected to GND; the drain of the sixteenth NMOS transistor MN16 is connected to the drain of the sixteenth PMOS transistor MP16, the gate of the sixteenth NMOS transistor MN16 is connected to the bias voltage VB2 as the third input terminal of the bias stage output link 5, and the source of the sixteenth NMOS transistor MN16 is connected to GND.
Compared with the prior art, the invention has the following advantages:
1. because the invention adopts the modular design, the bias stage starting link 2 is used for quickly starting the bias stage 3, and a micro-current source structure consisting of triodes or transistors is adopted for quickly generating the positive temperature current, and the bias voltage VB is output to the tail voltage stabilization output link 4, so that the tail voltage stabilization output link can quickly and stably work, and further the stable power supply voltage VOUT is obtained. The circuit complexity is reduced, and the working efficiency of the whole circuit system is improved.
2. Because the design combining N-level gradient voltage reduction and tail voltage stabilization is adopted, after the input high voltage is reduced to a low voltage range, the circuit can be designed by adopting a lower voltage-resistant device, meanwhile, the indexes of precision, stability and the like of the output voltage VOUT are ensured, the high-voltage input protection and output performance of the circuit are considered, the optimization of the circuit performance is favorably realized, and the circuit layout area is reduced.
3. Because the invention adopts the design of combining the bias priority intervention and the tail voltage stabilization, the bias level link 3 preferably intervenes the tail voltage stabilization output link 4, the starting speed is improved, simultaneously, the precision and the stability of the output voltage VOUT of the tail voltage stabilization output link 4 are ensured, and meanwhile, the bias level output link 5 can provide reference voltage and bias current for other circuits to quickly start other circuits.
Drawings
FIG. 1 is a schematic diagram illustrating an overall structure of a soft start voltage regulator circuit according to the patent application with application publication number CN 107656570A;
FIG. 2 is a schematic diagram of a buck regulator circuit according to the patent application published under the number CN 112135394A;
FIG. 3 is a functional block diagram of the present invention;
FIG. 4 is a schematic diagram of a specific circuit with a two-stage gradient buck link 1 and a tail regulated output link 4 according to a first embodiment of the present invention;
fig. 5 is a schematic diagram of a specific circuit principle of the bias stage starting link 2, the bias stage link 3 and the bias stage output link 5 in the first embodiment of the present invention.
FIG. 6 is a schematic diagram of a specific circuit with a four-stage gradient buck link 1 and a tail regulated output link 4 according to a second embodiment of the present invention;
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
Referring to fig. 3, the invention provides a fast start voltage stabilizing circuit with bias level priority intervention, comprising an N (N >1) level gradient voltage reducing link 1, a bias level start link 2, a bias level link 3, a tail voltage stabilizing output link 4, and a bias level output link 5, wherein:
the N-level gradient voltage reduction link 1 is configured to perform multi-level voltage reduction processing on the input power supply voltage VIN; the first output end outputs a 1 st-stage voltage reduction signal V1; the second output end outputs an Nth-stage buck signal VN; in the N-stage gradient voltage-reducing link 1, the supply voltage VIN at the input end can be derived from voltages generated by other circuit modules in the chip, or can be directly derived from a voltage input by an external pin of the chip, wherein the voltage value range of VIN can cover 10V-100V.
The bias level starting link 2 is used for starting the bias level link 3 to enable the bias level link 3 to be rapidly separated from a static state of zero current, and the input end of the bias level starting link is connected with a level 1 buck signal V1; the power supply is provided with two output ends, wherein the first output end outputs a starting voltage A, and the second output end outputs a starting voltage B;
the bias stage link 3 is used for quickly generating a reference voltage VB and is provided with three input ends and two output ends, the first input end is connected with a 1 st-stage buck signal V1, the second input end is connected with a starting voltage A, the third input end is connected with a starting voltage B, the output end of the first output end outputs a bias voltage VB and is connected to the tail voltage stabilization output link 4, and the output end of the second output end outputs a bias voltage VB2 and is connected to the bias stage output link (5);
the tail voltage stabilizing output link 4 is used for generating stable output power supply voltage, and is provided with four input ends and an output end, wherein the first input end is connected with a 1 st-level voltage reducing signal V1, the second input end is connected with an Nth-level voltage reducing signal VN, the third input end is connected with a bias voltage VB, the fourth input end is connected with a starting voltage A, and the input current IA of the fourth input end is the bias current of the module; the output end is used as a first output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a supply voltage VOUT;
the bias stage output link 5 is used for generating an output reference voltage VBO and a bias current IBO, and is provided with three input ends and two output ends, wherein the first input end is connected with a starting voltage a, the second input end is connected with a 1 st-stage step-down signal V1, and the third input end is connected with a bias voltage VB 2; the first output end is used as a second output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the reference voltage VBO, and the second output end is used as a third output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the bias current IBO.
Example 1
Referring to fig. 4, as a first preference, N of the N-stage gradient buck link 1 is 2, that is, the two-stage gradient buck link includes 2 voltage dividing resistors, a first voltage dividing resistor RS1, a second voltage dividing resistor RS2, 2 buck NMOS transistors, a first buck NMOS transistor MNS1, a second buck NMOS transistor MNS2, and three voltage stabilizing diodes, a first voltage stabilizing diode Z1, a second voltage stabilizing diode Z2, and a third voltage stabilizing diode Z3; wherein:
the 2 voltage reduction NMOS tubes MNS 1-MNS 2 are sequentially connected in series, the drain electrode of the first voltage reduction NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first voltage reduction NMOS tube MNS1 is connected with the drain electrode of the second voltage reduction NMOS tube MNS2 and serves as the first output end of the N-level gradient voltage reduction link 1 and outputs a 1-level voltage reduction signal V1, and the source electrode of the second voltage reduction NMOS tube MNS2 serves as the second output end of the two-level gradient voltage reduction link 1 and outputs a 2-level voltage reduction signal V2;
the 2 voltage-dividing resistors RS 1-RS 2 are sequentially connected in series to form a series circuit, one end of the first voltage-dividing resistor RS1 is connected with the drain electrode of the first voltage-reducing NMOS tube MNS1, the common end of the first voltage-dividing resistor RS1 and the second voltage-dividing resistor RS2 is connected with the grid electrode of the first voltage-reducing NMOS tube MNS1, and the other end of the second voltage-dividing resistor RS2 is connected with the grid electrode of the 2 nd voltage-reducing NMOS tube MNS 2;
the three voltage-stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage-stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage-reducing NMOS tube, the positive end of the first voltage-stabilizing diode Z1 is connected with the negative end of the second voltage-stabilizing diode Z2, the positive end of the second voltage-stabilizing diode Z2 is connected with the negative end of the third voltage-stabilizing diode Z3, and the positive end of the third voltage-stabilizing diode Z3 is connected with GND.
The tail voltage stabilizing output link 4 adopts an operational amplifier negative feedback voltage stabilizing structure and uses a bias voltage VB and a bias current IA for preferential intervention to ensure the generation speed and the accuracy of the final output power supply voltage VOUT of the rapid start voltage stabilizing circuit with the preferential intervention of the bias level, and comprises four resistors, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, four PNP tubes, a first PNP tube Q1, a second PNP tube Q2, a fourth PNP tube Q4, a fifth PNP tube Q5, five NPN tubes, a third NPN tube Q3, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9, a ninth PMOS tube first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP2, a sixth PMOS tube MP 56, a seventh PMOS tube MP 5953, an eighth PMOS tube MP 8427, a fifth PMOS tube MN 368658, a ninth NMOS 36368672, a seventh PMOS 36 8, a seventh PMOS tube MN 368672, a ninth NMOS 36368672 and a seventh PMOS 368672, A sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN 9; wherein:
the first PNP tube Q1 and the second PNP tube Q2 form a current mirror structure, the emitters of the first PNP tube Q1 and the second PNP tube Q2 are both connected with the Nth-level buck signal VN, the bases of the first PNP tube VN 1 and the second PNP tube Q2 are connected with the collector of the first PNP tube Q1, the collector of the second PNP tube Q2 is connected with the base of the third NPN tube Q3, the second input end of the collector of the third NPN tube Q3 serving as a tail voltage stabilization output link (4) is connected with the Nth-level buck signal VN, and the emitter of the third NPN tube Q3 is connected with a voltage signal VC 1;
sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are all connected to GND, and gates of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to form a current mirror structure; the drain electrode of the third NMOS tube MN3 is connected with the gate electrode thereof, the fourth input end of the third NMOS tube MN3 serving as a tail voltage stabilization output link (4) is connected with a starting voltage A, the input current of the input end is bias current IA, the drain electrode of the fourth NMOS tube MN4 is connected with the collector electrode of a first PNP tube Q1, the drain electrode of the fifth NMOS tube MN5 is connected with the collector electrode of a second PNP tube Q2, and the drain electrode of the sixth NMOS tube MN6 is connected with a first PMOS tube MP 1;
the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are all connected with an Nth-stage voltage reduction signal VN, and the grid electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to form a current mirror structure; the drain electrode of a first PMOS tube MP1 is connected with the grid electrode of the first PMOS tube MP1, the drain electrode of a second PMOS tube MP2 is connected with the drain electrode of a seventh NMOS tube MN7, the drain electrode of a third PMOS tube MP3 is connected with the collector electrode of a sixth NPN tube Q6, the drain electrode of a fourth PMOS tube MP4 is connected with the emitter electrode of the fourth NPN tube Q4 through a third resistor R3, and the drain electrode of a fifth PMOS tube MP5 is connected with the collector electrode of a ninth NPN tube Q9;
the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and the grid electrode of the eighth NMOS transistor MN8, and the source electrode of the seventh NMOS transistor MN7 is connected with GND;
the fourth PNP tube Q4 and the fifth PNP tube Q5 form a differential pair tube input, the base electrode of the fourth PNP tube Q4 is used as the third input end of the tail voltage stabilization output link (4) to be connected with the bias voltage VB, and the collector electrode of the fourth PNP tube Q8926 is connected with the collector electrode of the eighth NPN tube Q8; the base electrode of the fifth PNP tube Q5 is connected with the feedback voltage VFB, the collector electrode of the fifth PNP tube Q5 is connected with the collector electrode of the seventh NPN tube Q7, and the emitter electrode of the fifth PNP tube Q5 is connected with the drain electrode of the fourth PMOS tube MP4 through a fourth resistor R4;
bases of the sixth NPN tube Q6 and the seventh NPN tube Q7 are connected to form a current mirror structure, and emitters of the current mirror structure are connected to GND; a collector of a sixth NPN tube Q6 is connected with a base electrode of the sixth NPN tube Q6;
the sources of the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are both connected with the Nth-stage voltage reduction signal VN, and the gates thereof are connected to form a current mirror structure; the drain of the sixth PMOS tube MP6 is connected with the grid thereof, and the drain of the sixth PMOS tube MP6 is connected with the drain of the ninth NMOS tube MN9 and is connected with a voltage signal VC 1;
the gates of the eighth NPMOS transistor MP8 and the ninth NMOS transistor MN9 are connected with each other and the drain of the seventh NMOS transistor MN 7; the drain of the eighth NPMOS transistor MP8 is connected to the drain of the sixth PMOS transistor MP6, and the source thereof is connected to the collector of the seventh NPN transistor Q7; the source electrode of the ninth NMOS transistor MN9 is connected with the collector electrode of the eighth NPN transistor Q8;
the bases of the eighth NPN tube Q8 and the ninth NPN tube Q9 are connected to form a current mirror structure, and the emitters of the current mirror structure are connected to GND; a collector of the ninth NPN tube Q9 is connected with a base electrode of the ninth NPN tube Q9;
the gate of the eighth PMOS transistor MP8 is connected to the voltage signal VC1, the drain thereof is connected to GND, and the source thereof is connected to the nth step-down signal VN;
the gate of the ninth PMOS transistor MP9 is connected to the nth-stage step-down signal VN, the source thereof is connected to the 1 st-stage step-down signal V1 as the first input terminal of the tail voltage-stabilized output link 4, and the drain thereof is used as the output terminal of the tail voltage-stabilized output link 4 to output the supply voltage VOUT;
the fifth resistor R5 and the sixth resistor R6 are connected in series and bridged between the drain of the ninth PMOS transistor MP9 and GND, and the common end of the fifth resistor R5 and the sixth resistor R6 is connected with the feedback voltage VFB.
Referring to fig. 5, the bias stage starting link 2 includes a seventh resistor R7, and a tenth NPN transistor Q10 and an eleventh NPN transistor Q11; wherein:
one end of the seventh resistor R7 is connected to the 1 st-level buck signal V1, the other end of the seventh resistor R7 is connected to the base of the tenth NPN transistor Q10 and the collector of the eleventh NPN transistor Q11, both the emitter of the tenth NPN transistor Q10 and the emitter of the eleventh NPN transistor Q11 are connected to GND, the drain of the tenth NPN transistor Q10 and the gate of the eleventh NPN transistor Q11 output a start voltage a and a start voltage B, respectively, and the current of the start voltage a corresponding to the a node is the bias current IA.
The bias stage link 3 comprises four resistors, namely an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11, two NPN transistors, namely a twelfth NPN transistor Q12 and a thirteenth NPN transistor Q13, nine PMOS transistors, namely a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20 and a twenty-third PMOS transistor MP23, and six NMOS transistors, namely a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14 and a fifteenth NMOS transistor MN 15; wherein:
the source electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the first input end serving as the bias stage link 3 and connected with the 1 st-stage buck signal V1, the grid electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the drain electrode of the eighteenth PMOS tube MP18, and the drain electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP 3538 are respectively connected with the source electrodes of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 to form a PMOS cascode current mirror structure; gates of seventeenth PMOS tubes MP17 to twenty-seventh PMOS tubes MP20 are connected and serve as a second input end of the bias stage link 3 to be connected with a starting voltage A, drains of the seventeenth PMOS tubes MP17 are connected with a starting voltage B through an eighth resistor R8, drains of eighteenth PMOS tubes MP18 are connected with the starting voltage A through a ninth resistor R9, drains of the nineteenth PMOS tubes MP19 are connected with drains of fourteenth NMOS tubes MN14, and drains of the twentieth PMOS tubes MP20 are connected with drains of a twelfth NMOS tube MN 12;
the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11 and to the drain of the tenth NMOS transistor MN10, the drain of the tenth NMOS transistor MN10 is connected to the start voltage B as the third input terminal of the bias stage link 3, and the source thereof is connected to the collector of the twelfth NPN transistor Q12; the drain electrode of the eleventh NMOS tube MN11 is connected with the starting voltage A; the bases of the twelfth NPN transistor Q12 and the thirteenth NPN transistor Q13 are connected to the collector of the twelfth NPN transistor Q12, the emitter of the twelfth NPN transistor Q12 is connected to GND, and the emitter of the thirteenth NPN transistor Q13 is connected to GND through the tenth resistor R10; the gates of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are connected with each other and to the drain of a twelfth NMOS transistor MN12, the source of the twelfth NMOS transistor MN12 is connected with the drain of the twenty-third PMOS transistor MP23, and the gate and the drain of the twenty-third PMOS transistor MP23 are both connected to GND; the drain electrode of the thirteenth NMOS transistor MN13 is connected with the 1 st-stage buck signal V1 through the eleventh resistor R11, the source electrode of the thirteenth NMOS transistor MN 3578 is connected with the drain electrode of the fifteenth NMOS transistor MN15 and serves as the first output end of the biasing stage link 3 to output the biasing voltage VB; sources of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are both connected to GND, gates of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are connected and serve as a second output end of the bias stage link 3 to output bias voltage VB2, and a drain of the fourteenth NMOS transistor MN14 is connected with a gate of the fourteenth NMOS transistor.
In the bias stage link 3, a micro-current source structure composed of triodes or transistors is adopted to quickly generate the positive temperature current, the current value and the temperature coefficient of the positive temperature current can be modified by adjusting the number ratio of the triodes or the transistors and the resistance value of a micro-current source resistor, and in the embodiment, the bias current IA corresponding to the node A is taken to be 0.25 uA. In addition, the positive temperature current is taken as the leakage current of a thirteenth NMOS transistor MN13 located in the saturation region, and the voltage value and the temperature coefficient of the gate-source voltage of the NMOS transistor are modified by adjusting the width-to-length ratio parameter of the NMOS transistor, so as to be taken as the output of the bias voltage VB of the bias stage link 3, where in this embodiment, the bias voltage VB is taken as 2.5V.
The bias level output link 5 is used for processing the bias voltage VB and the bias current IA provided by the bias level link 3 to generate the finally output bias voltage VBO and the bias current IBO of the rapid start voltage stabilizing circuit with the bias level priority intervention designed by the invention; the circuit comprises two resistors, namely a twelfth resistor R12, a thirteenth resistor R13, a PNP tube, a fourteenth PNP tube Q14, five PMOS tubes, namely a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a sixteenth PMOS tube MP16, a twenty-first PMOS tube MP21, a twenty-second PMOS tube MP22 and an NMOS tube, namely a sixteenth NMOS tube MN 16; wherein: the sources of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected, the second input end of the bias stage output link 5 is connected with the 1 st-stage buck signal V1, and the gates of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected with the drain of the bias stage output link 5; the drain of a fourteenth PMOS tube MP14 is connected with the source of the twenty-first PMOS tube MP21, and the drain of a fifteenth PMOS tube MP15 is connected with the source of the twenty-second PMOS tube MP 22; the gates of the twenty-first PMOS transistor MP21 and the twenty-second PMOS transistor MP22 are connected, the first input end of the bias stage output link 5 is connected to the starting voltage a, the drain of the twenty-first PMOS transistor MP21 is used as the third output end of the bias stage output link 5, and the bias current IBO is output; the drain of the twenty-second PMOS transistor MP22 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the emitter of the fourteenth PNP transistor Q14 through the thirteenth resistor R13; a common end of the twelfth resistor R12 and the thirteenth resistor R13 serves as a second output end of the bias stage output link 5 and outputs a reference voltage VBO; the base electrode and the collector electrode of the fourteenth PNP tube Q14 are both connected to GND; the drain of the sixteenth NMOS transistor MN16 is connected to the drain of the sixteenth PMOS transistor MP16, the gate of the sixteenth NMOS transistor MN16 is connected to the bias voltage VB2 as the third input terminal of the bias stage output link 5, and the source of the sixteenth NMOS transistor MN16 is connected to GND.
The working principle of the invention is as follows:
referring to fig. 4, in this embodiment, there are two specific circuit portions of the N-stage gradient buck link 1 and the tail regulator output link 4 in this embodiment. In the embodiment, the functions of the N-level gradient buck link 1 are mainly realized by high-voltage tubes MNS1 and MNS2, zener diodes Z1, Z2 and Z3, and large resistors RS1 and RS 2. The stable voltage value (reverse breakdown voltage value) of a single voltage-stabilizing tube from Z1 to Z3 is 5.8V, so that under the condition that R1, R2 and Z1 to Z3 are connected in series for voltage stabilization, voltage which is three times of the stable voltage value (reverse breakdown voltage value) of the voltage-stabilizing tube is generated at the negative electrode of Z1, and the voltage is about 17.4V; the resistance values of R1 and R2 which are selected and used are both 550 kilo ohms by calculating and matching with the rated current and rated voltage parameters of the voltage regulator tube. The extreme values of the gate-source voltage, the drain-source voltage and the voltage between the drain terminal and the reference ground of the high-voltage tube MNS1 and MNS2 are analyzed in terms of voltage resistance selection and circuit device protection. The source terminal voltage of the MNS2 is about 16V, and when VIN is up to 100V, half of the voltage difference value between the drain source of MNS1 and the drain source of MNS2 is applied, and is about 42V; meanwhile, considering that the limit values of the drain terminal voltages of the MNS1 and the MNS2 are 100V and 58V respectively, the MNS1 is selected to be a high-voltage 100V device, and the MN2 is selected to be a high-voltage 60V device.
Referring to fig. 4, in this embodiment, the tail regulator output link 4 adopts an operational amplifier structure to improve the precision and stability of voltage reduction and regulation, and the high-voltage tubes MN 3-MN 6 and the high-voltage tubes MP 1-MP 5 are typical NMOS and PMOS basic current mirror structures, respectively. Q1-Q3 are starting circuits of operational amplifier structures, VOUT is not established when the circuit is just powered on, the feedback voltage is very low and is approximately close to the reference ground voltage, the collector voltage of Q5 is very high, the output control voltage VC1 is very low after passing through a current mirror load formed by MP6 and MP7, and the abnormal state can cause the grid voltage of MP9 to be very low, so that the working state of MP9 deviates from the normal state. Therefore, a starting circuit composed of Q1-Q3 is needed, Q1 and Q2 form a typical current mirror structure, the base voltage of Q3 is fixed to be the power supply voltage VN, the Vec voltage of Q2 is reduced, then when the circuit is just powered on and the control voltage VC1 is very low, Vbe of Q3 is far greater than the conducting voltage, and at the moment, the emitter (control voltage VC1) of Q3 is pulled high; when the operational amplifier structure enters a normal working state, the control voltage VC1 reaches a constant high voltage value and is dynamically adjusted within a certain range, and when the Vbe of Q3 is not more than the conduction voltage, the operational amplifier structure enters a cut-off region to be turned off, so that the operational amplifier structure is started.
Referring to fig. 5, there are three specific circuits of the bias stage starting link 2, the bias stage link 3 and the bias stage output link 5 in this embodiment. MN 14-MN 16 are typical NMOS basic current mirror structures, and MP 10-MP 16 and high-voltage tubes MP 17-MP 22 are mirror tubes and cascode tubes in the PMOS cascode current mirror structures respectively.
Referring to fig. 5, the bias level enable link 2 in this embodiment includes Q10, Q11 and a resistor R7, when the circuit starts to power up, a cascode loop structure formed by MP10, MP11, MP16, MP17, MN10, MN11, Q12 and Q13 is not related to the supply voltage V1, that is, all transistors in the two branches can maintain a stable state before power up after the supply voltage V1 is powered up, so that the branches on both sides of the loop transmit zero current and always keep an infinite steady state and cannot be enabled, and therefore, the enable circuit of the bias level enable link 2 in this embodiment helps the circuit to get rid of the stable state.
Example 2
Referring to fig. 6, as a second preferred option, N of the N-level gradient buck link 1 is 4, that is, the 4-level gradient buck link includes 4 voltage dividing resistors, namely a first voltage dividing resistor RS1, a second voltage dividing resistor RS2, an integral voltage dividing resistor RS4, 4 buck NMOS transistors, namely a first buck NMOS transistor MNS1, a second buck NMOS transistor MNS2, an integral voltage dividing resistor MNS4, and three zener diodes, namely a first zener diode Z1, a second zener diode Z2, and a third zener diode Z3; wherein:
the 4 step-down NMOS tubes MNS 1-MNS 4 are sequentially connected in series, the drain electrode of the first step-down NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first step-down NMOS tube MNS1 is connected with the drain electrode of the second step-down NMOS tube MNS2 and serves as the first output end of the 4-level gradient step-down link 1, and a 1-level step-down signal V1 is output, the source electrode of the second step-down NMOS tube MNS2 is connected with the drain electrode of the third step-down NMOS tube MNS3, the same goes, the like, the source electrode of the 3 rd step-down NMOS tube MNS3 is connected with the drain electrode of the 4 th step-down NMOS tube MNS4, and the source electrode of the 4 th step-down NMOS tube MNS4 serves as the second output end of the 4-level gradient step-down link 1, and the 4-level step-down signal V4 is output;
the 4 voltage-dividing resistors RS 1-RS 4 are sequentially connected in series to form a series circuit, one end of a first voltage-dividing resistor RS1 is connected with the drain electrode of a first voltage-reducing NMOS tube MNS1, the common end of the first voltage-dividing resistor RS1 and a second voltage-dividing resistor RS2 is connected with the grid electrode of a first voltage-reducing NMOS tube MNS1, the common end of a second voltage-dividing resistor RS2 and a third voltage-dividing resistor RS3 is connected with the grid electrode of a second voltage-reducing NMOS tube MNS2, the same goes true, the common end of a 3 rd voltage-dividing resistor RS3 and a 3 rd voltage-dividing resistor RS4 is connected with the grid electrode of a 3 rd voltage-reducing NMOS tube MNS3, and the other end of the 3 rd voltage-dividing resistor RS3 is connected with the grid electrode of an Nth voltage-reducing NMOS tube MNS 3;
the three voltage-stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage-stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage-reducing NMOS tube, the positive end of the first voltage-stabilizing diode Z1 is connected with the negative end of the second voltage-stabilizing diode Z2, the positive end of the second voltage-stabilizing diode Z2 is connected with the negative end of the third voltage-stabilizing diode Z3, and the positive end of the third voltage-stabilizing diode Z3 is connected with GND.
The other modules are the same as those in embodiment 1. The selection of the stage number N of the N-stage gradient voltage reduction link 1 is determined according to the range of the specific input voltage VIN and the actual situation, and N >1 may be selected.
The above examples only show two specific embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
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| CN113311899A (en) * | 2021-08-02 | 2021-08-27 | 四川蕊源集成电路科技有限公司 | Voltage regulator |
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| CN113157042B (en) | 2022-12-02 |
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