CN113157042B

CN113157042B - Quick start voltage stabilizing circuit with bias priority intervention

Info

Publication number: CN113157042B
Application number: CN202110545019.4A
Authority: CN
Inventors: 来新泉; 王瑞东; 赵壮; 刘晨; 周磊磊
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2022-12-02
Anticipated expiration: 2041-05-19
Also published as: CN113157042A

Abstract

The invention provides a rapid start voltage stabilizing circuit with bias priority intervention, which can be rapidly started when input power supply voltage is instantly electrified so as to enter a normal voltage stabilizing working state, and is characterized in that the input power supply voltage is processed through an N (N > 1) level gradient voltage reduction link, a bias level starting link, a bias level link, a tail voltage stabilizing output link and a bias level output link, and finally, the stable output power supply voltage is obtained while primary reference voltage and bias current can be provided for other integrated circuit modules. According to the invention, the modular design is adopted to increase the N-level gradient voltage reduction link, so that the damage of external high voltage to an internal circuit is avoided, meanwhile, the N-level gradient voltage reduction link is converted into a low-voltage range for power supply, the circuit performance optimization is facilitated, the application capability of a wide-range large-voltage field is improved, and the accuracy of the tail voltage stabilization output link is ensured while the starting speed is improved by the biasing level link to preferentially intervene the tail voltage stabilization output link.

Description

Quick start voltage stabilizing circuit with bias priority intervention

Technical Field

The invention belongs to the field of analog integrated circuits, relates to a rapid start voltage stabilizing circuit, and particularly relates to a rapid start voltage stabilizing circuit with bias priority intervention.

Background

With the continuous development of personal consumer electronics, communication equipment and automotive electronics, higher requirements are put forward on the rapid start of the voltage stabilizing circuit and the stability, accuracy and other performances of the output voltage of the voltage stabilizing circuit at the internal power supply end thereof. The voltage stabilizing circuit can be divided into electronic voltage stabilization, electromagnetic conversion voltage stabilization and digital control voltage stabilization. The simple electronic voltage stabilizing circuit can be obtained by connecting a resistor and a diode in series, and the voltage on the diode only slightly changes when the input current changes, so that the purpose of outputting stable voltage is achieved, but the accuracy of the output voltage is not high. Then, an electronic voltage stabilizing circuit with a negative feedback structure is further developed on the basis of simple electronic voltage stabilization, an actual feedback voltage and a fixed reference voltage are compared, an error value is amplified and then sent to a voltage stabilizing element, and an output is regulated to reduce the error value, so that a negative feedback control loop is formed. The accuracy of voltage control can be further improved by increasing the open loop gain but the stability of the system is reduced, so that a trade-off between stability and response speed to variations is required. The electromagnetic conversion type voltage stabilization is generally mainly applied to an alternating current voltage stabilizing circuit, and a magnetic element is used for performing electromagnetic conversion to complete final voltage stabilization output. The digital control type voltage stabilization belongs to an active control type system, the working principle of the digital control type voltage stabilization system is the same as that of a general electronic voltage stabilizing circuit, but the system enters an active detection and control structure. The digital control type voltage stabilizing circuit comprises a diode, a capacitor, a resistor, a potentiometer and a microcontroller, can be integrated in a small PCB or further highly integrated in a chip, is generally matched with a detected target to form positive and quick sensor feedback parameters for positive adjustment, and quickly provides stable output power supply voltage for a target circuit or equipment. Due to the diversification and enrichment of the application fields of various electronic products, the higher voltage input scene becomes a factor that must be considered nowadays. On the other hand, the improvement of the overall starting speed of the electronic product is bound and depends on the starting speed of the voltage stabilizing circuit at the internal power supply end to a great extent.

For example: referring to fig. 1, the patent application with application publication No. CN 10765656570A and titled "a soft start voltage stabilizing circuit" discloses a soft start voltage stabilizing circuit mainly composed of a transformer T, a diode rectifier U, a triode VT4, a resistor R3, a resistor R4, a capacitor C1, a capacitor C4, a diode D2, a diode D3, a soft start processing circuit, a source constant current driving circuit and a delay start circuit. The high-voltage switch comprises a capacitor C1, a soft start processing circuit, a resistor R3, a diode D2, a delay starting circuit, a source constant current driving circuit and a diode D3, wherein the positive output end of the rectifier U is connected, the negative output end of the rectifier U is connected with the negative output end of the diode rectifier U, the soft start processing circuit is respectively connected with the positive electrode and the negative electrode of the capacitor C1, the capacitor C4 is connected with the positive electrode and the negative electrode of the capacitor C1, the positive electrode is connected with the soft start processing circuit, the negative electrode is connected with the negative electrode of the capacitor C1, the capacitor C4 is connected with the negative electrode of the capacitor C1, the negative electrode is connected with the negative electrode of the capacitor C4, the diode D2 is connected with the negative electrode of the capacitor C1, the P electrode is connected with the emitting electrode of the triode VT4, the delay starting circuit is respectively connected with the emitting electrode of the triode VT4, the delay starting circuit is connected with the P electrode of the diode D3, and the P electrode is connected with the collector of the triode VT4 through the resistor R4; the two ends of a primary side inductance coil of the transformer T form a power supply input end, one input end of the diode rectifier U is connected with the non-homonymous end of a secondary side inductance coil of the transformer T, and the other input end of the diode rectifier U is connected with the homonymous end of the secondary side inductance coil of the transformer T; the N pole of the diode D3 is connected with the soft start processing circuit. The method for starting the rear-stage circuit or equipment by mainly using the transformer T, the diode rectifier U, the triode VT4 and other elements to generate the stable output voltage value at a slower speed through a starting process after the input power supply voltage is electrified can avoid the high-voltage damage of the input power supply voltage to the internal circuit to a certain extent, but the stable output voltage is longer in establishment time due to the existence of the slower starting process, so that the working effect of the rear-stage circuit or equipment is limited; meanwhile, the application of the circuit designed by the method is limited because the internal circuit uses a transformer element, and further integration is difficult to realize.

The following steps are repeated: referring to fig. 2, the application publication No. CN 112135394A, entitled "a constant current LED driving circuit capable of voltage boosting and voltage dropping", discloses a constant current LED driving circuit capable of voltage boosting and voltage dropping, which includes an input circuit, a voltage boosting/reducing circuit, an output circuit and a control circuit, where the voltage boosting/reducing circuit includes a voltage boosting and stabilizing circuit and a voltage reducing and stabilizing circuit, the input circuit is connected with the voltage boosting/reducing circuit, the voltage boosting/reducing circuit is connected with the output circuit, the output circuit is connected with an LED lamp, the LED lamp is connected with the control circuit, and the control circuit is connected with the voltage boosting/reducing circuit. The voltage reduction and stabilization circuit comprises a second MOS tube, a first diode and a second inductor, wherein a first pin to a third pin of the second MOS tube are connected with one ends of the input circuit and the eighth resistor, a fourth pin of the second MOS tube is connected with the control circuit and the other end of the eighth resistor respectively, a fifth pin to an eighth pin of the second MOS tube are connected with one end of the first diode and one end of the second inductor, the other end of the second inductor is connected with the voltage boost and stabilization circuit, and the other end of the first diode is grounded. The invention mainly uses MOS tube, diode and inductance to form the voltage stabilizing output circuit, because there is no transformer element in it, it is beneficial to optimize the circuit structure further and realize high integration, but because there is no voltage reducing protection structure of input power supply voltage in it, the voltage stabilizing output circuit designed by the invention is difficult to be applied to higher input power supply voltage and is limited; meanwhile, because the internal circuit uses a voltage stabilizing output circuit formed by MOS (metal oxide semiconductor) transistors, diodes, inductors and other elements and has no feedback control structure, the output voltage has low accuracy and poor stability, so that the application of the voltage stabilizing circuit designed by the method is limited.

Disclosure of Invention

The invention aims to solve the technical problem of providing a rapid start voltage stabilizing circuit with wide voltage input range, high output accuracy, high output stability and high start speed aiming at the defects of the prior art.

The technical problem to be solved by the invention is realized by the following technical scheme: a fast start voltage stabilizing circuit with bias priority intervention can be started quickly when input power supply voltage is electrified instantly so as to enter a normal voltage stabilizing working state.

The invention specifically comprises an N (N > 1) grade gradient voltage reduction link 1, an offset grade starting link 2, an offset grade link 3, a tail voltage stabilization output link 4 and an offset grade output link 5, wherein: the N (N > 1) level gradient voltage reduction link 1 is used for carrying out multi-level voltage reduction processing on an input power supply voltage VIN; the first output end outputs a 1 st-level buck signal V1; the second output end outputs an Nth-stage buck signal VN; the bias level starting link 2 is used for starting the bias level link 3 to enable the bias level link 3 to be rapidly separated from a static state of zero current, and the input end of the bias level starting link is connected with a 1 st level voltage reduction signal V1; the power supply is provided with two output ends, wherein the first output end outputs a starting voltage A, and the second output end outputs a starting voltage B; the bias stage link 3 is used for rapidly generating a bias voltage VB and is provided with three input ends and two output ends, the first input end is connected with a 1 st-stage buck signal V1, the second input end is connected with a starting voltage A, the third input end is connected with a starting voltage B, the first output end outputs the bias voltage VB and is connected to the tail voltage stabilization output link 4, and the second output end outputs the bias voltage VB2 and is connected to the bias stage output link 5; the tail voltage stabilization output link 4 is used for generating stable output power supply voltage and is provided with four input ends and an output end, wherein the first input end is connected with a 1 st-level buck signal V1, the second input end is connected with an Nth-level buck signal VN, the third input end is connected with a bias voltage VB, and the fourth input end is connected with a starting voltage A; the output end is used as a first output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a supply voltage VOUT; the bias stage output link 5 is used for generating an output reference voltage VBO and a bias current IBO, and is provided with three input ends and two output ends, wherein the first input end is connected with a starting voltage a, the second input end is connected with a 1 st stage buck signal V1, and the third input end is connected with a bias voltage VB2; the first output end is used as a second output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the reference voltage VBO, and the second output end is used as a third output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the bias current IBO.

The N-level gradient buck link 1 comprises N (N > 1) divider resistors, namely a first divider resistor RS1, a second divider resistor RS2, an Nth divider resistor RSN, N buck NMOS tubes, namely a first buck NMOS tube MNS1, a second buck NMOS tube MNS2, an Nth buck NMOS tube MNSN, three voltage-stabilizing diodes, namely a first voltage-stabilizing diode Z1, a second voltage-stabilizing diode Z2 and a third voltage-stabilizing diode Z3; wherein: the N voltage-reducing NMOS tubes MNS 1-MNSN are sequentially connected in series, the drain electrode of the first voltage-reducing NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first voltage-reducing NMOS tube MNS1 is connected with the drain electrode of the second voltage-reducing NMOS tube MNS2 and serves as the first output end of the N-level gradient voltage-reducing link 1, and a 1 st voltage-reducing signal V1 is output, the source electrode of the second voltage-reducing NMOS tube MNS2 is connected with the drain electrode of the third voltage-reducing NMOS tube MNS3, so on, the source electrode MNSN-1 of the N-1 voltage-reducing NMOS tube MNSN is connected with the drain electrode of the N-level voltage-reducing NMOS tube MNSN, and the source electrode of the N-level voltage-reducing NMOS tube MNSN serves as the second output end of the N-level gradient voltage-reducing link 1, and an N-level voltage-reducing signal VN is output; the N voltage-dividing resistors RS 1-RSN are sequentially connected in series to form a series circuit, one end of a first voltage-dividing resistor RS1 is connected with the drain electrode of a first voltage-dividing NMOS tube MNS1, the common end of the first voltage-dividing resistor RS1 and a second voltage-dividing resistor RS2 is connected with the grid electrode of the first voltage-dividing NMOS tube MNS1, the common end of a second voltage-dividing resistor RS2 and a third voltage-dividing resistor RS3 is connected with the grid electrode of a second voltage-dividing NMOS tube MNS2, so forth, the common end of an N-1 voltage-dividing resistor RSN-1 and an N voltage-dividing resistor RSN is connected with the grid electrode of an N-1 voltage-dividing NMOS tube MNSN, and the other end of the N voltage-dividing resistor RSN is connected with the grid electrode of an N voltage-dividing NMOS tube MNSN; the three voltage stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage reducing NMOS tube, the positive end of the first voltage stabilizing diode Z1 is connected with the negative end of the second voltage stabilizing diode Z2, the positive end of the second voltage stabilizing diode Z2 is connected with the negative end of the third voltage stabilizing diode Z3, and the positive end of the third voltage stabilizing diode Z3 is connected with GND.

The bias stage starting link 2 comprises a seventh resistor R7, a tenth NPN transistor Q10 and an eleventh NPN transistor Q11; wherein: one end of the seventh resistor R7 serving as an input end of the bias stage starting link 2 is connected to the 1 st-level buck signal V1, the other end of the seventh resistor R is connected to a base of the tenth NPN transistor Q10 and a collector of the eleventh NPN transistor Q11, an emitter of the tenth NPN transistor Q10 and an emitter of the eleventh NPN transistor Q11 are both connected to GND, and a collector of the tenth NPN transistor Q10 serving as a first output end of the bias stage starting link 2 outputs a starting voltage a; the base of the eleventh NPN transistor Q11 serves as the second output terminal of the bias stage starting link 2 to output the starting voltage B.

The bias stage link 3 includes four resistors, namely an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, two NPN transistors, namely, a twelfth NPN transistor Q12 and a thirteenth NPN transistor Q13, nine PMOS transistors, namely, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-third PMOS transistor MP23, and six NMOS transistors, namely, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor MN15; wherein: the tenth PMOS transistor MP10 to the thirteenth PMOS transistor MP13 have sources connected to the first input terminal serving as the bias stage link 3 and connected to the 1 st buck signal V1, gates connected to the drain of the eighteenth PMOS transistor MP18, and drains connected to the sources of the seventeenth PMOS transistor MP17 to the twentieth PMOS transistor MP20, respectively, to form a PMOS cascode current mirror structure; the gates of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 are connected and serve as the second input end of the bias stage link 3 to be connected with the starting voltage A, the drain of the seventeenth PMOS tube MP17 is connected with the starting voltage B through an eighth resistor R8, the drain of the eighteenth PMOS tube MP18 is connected with the starting voltage A through a ninth resistor R9, the drain of the nineteenth PMOS tube MP19 is connected with the drain of the fourteenth NMOS tube MN14, and the drain of the twentieth PMOS tube MP20 is connected with the drain of the twelfth NMOS tube MN 12; the tenth NMOS transistor MN10 is connected with the gate of the eleventh NMOS transistor MN11 and is connected to the drain of the tenth NMOS transistor MN10, the drain of the tenth NMOS transistor MN10 is connected with the starting voltage B as the third input end of the bias stage link 3, and the source of the tenth NMOS transistor MN10 is connected with the collector of a twelfth NPN transistor Q12; the drain electrode of the eleventh NMOS tube MN11 is connected with the starting voltage A, and the source electrode of the eleventh NMOS tube MN is connected with the collector electrode of the thirteenth NPN tube Q13; the bases of the twelfth NPN transistor Q12 and the thirteenth NPN transistor Q13 are connected to the collector of the twelfth NPN transistor Q12, the emitter of the twelfth NPN transistor Q12 is connected to GND, and the emitter of the thirteenth NPN transistor Q13 is connected to GND through the tenth resistor R10; the gates of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are connected and are connected to the drain of the twelfth NMOS transistor MN12, the source of the twelfth NMOS transistor MN12 is connected with the source of the twenty-third PMOS transistor MP23, and the gate and the drain of the twenty-third PMOS transistor MP23 are both connected to GND; the drain electrode of the thirteenth NMOS transistor MN13 is connected with the 1 st-stage buck signal V1 through the eleventh resistor R11, and the source electrode thereof is connected with the drain electrode of the fifteenth NMOS transistor MN15 and serves as the first output end of the bias stage link 3 to output a bias voltage VB; sources of the fourteenth NMOS tube MN14 and the fifteenth NMOS tube MN15 are connected to GND, gates of the fourteenth NMOS tube MN14 and the fifteenth NMOS tube MN15 are connected and used as a second output end of the bias stage link 3 to output bias voltage VB2, and a drain of the fourteenth NMOS tube MN14 is connected with a gate of the fourteenth NMOS tube.

The tail voltage stabilization output link 4 comprises four resistors, namely a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, four PNP tubes, namely a first PNP tube Q1, a second PNP tube Q2, a fourth PNP tube Q4 and a fifth PNP tube Q5, five NPN tubes, namely a third NPN tube Q3, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8 and a ninth NPN tube Q9, nine PMOS tubes, namely a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8 and a ninth PMOS tube MP9, seven NMOS tubes, namely a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth PMOS tube MN8 and a ninth NMOS tube MN9; wherein: the first PNP tube Q1 and the second PNP tube Q2 form a current mirror structure, the emitting electrodes of the first PNP tube Q1 and the second PNP tube Q2 are connected with the Nth-stage buck signal VN, the base electrodes of the first PNP tube Q1 and the second PNP tube Q2 are connected with the collector electrode of the first PNP tube Q1, the collector electrode of the second PNP tube Q2 is connected with the base electrode of the third NPN tube Q3, the second input end of the collector electrode of the third NPN tube Q3 serving as a tail voltage stabilization output link 4 is connected with the Nth-stage buck signal VN, and the emitting electrode of the third NPN tube Q3 is connected with a voltage signal VC1; the sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are all connected to GND, and the grids thereof are connected to form a current mirror structure; the drain electrode of a third NMOS tube MN3 is connected with the grid electrode of the third NMOS tube and is used as a fourth input end of the tail voltage stabilization output link 4 to be connected with the starting voltage A, the drain electrode of a fourth NMOS tube MN4 is connected with the collector electrode of a first PNP tube Q1, the drain electrode of a fifth NMOS tube MN5 is connected with the collector electrode of a second PNP tube Q2, and the drain electrode of a sixth NMOS tube MN6 is connected with a first PMOS tube MP1; the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are all connected with the Nth-stage voltage reduction signal VN, and the grid electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to form a current mirror structure; the drain electrode of the first PMOS tube MP1 is connected with the grid electrode of the first PMOS tube MP1, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the seventh NMOS tube MN7, the drain electrode of the third PMOS tube MP3 is connected with the collector electrode of the sixth NPN tube Q6, the drain electrode of the fourth PMOS tube MP4 is connected with the emitter electrode of the fourth PNP tube Q4 through a third resistor R3, and the drain electrode of the fifth PMOS tube MP5 is connected with the collector electrode of the ninth NPN tube Q9; the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and is connected with the grid electrode of the eighth NMOS transistor MN8, and the source electrode of the seventh NMOS transistor MN7 is connected with GND; the fourth PNP tube Q4 and the fifth PNP tube Q5 form a differential pair tube input, the base electrode of the fourth PNP tube Q4 serving as a third input end of the tail voltage stabilization output link 4 is connected with a bias voltage VB, and the collector electrode of the fourth PNP tube Q4 is connected with the collector electrode of the eighth NPN tube Q8; the base electrode of the fifth PNP tube Q5 is connected with the feedback voltage VFB, the collector electrode of the fifth PNP tube Q5 is connected with the collector electrode of the seventh NPN tube Q7, and the emitter electrode of the fifth PNP tube Q5 is connected with the drain electrode of the fourth PMOS tube MP4 through a fourth resistor R4; bases of the sixth NPN tube Q6 and the seventh NPN tube Q7 are connected to form a current mirror structure, and emitters of the current mirror structure are connected to GND; a collector of a sixth NPN tube Q6 is connected with a base electrode of the sixth NPN tube; the source electrodes of the sixth PMOS pipe MP6 and the seventh PMOS pipe MP7 are connected with the Nth-stage voltage reduction signal VN, and the grid electrodes of the sixth PMOS pipe MP6 and the seventh PMOS pipe MP7 are connected to form a current mirror structure; the drain electrode of a sixth PMOS tube MP6 is connected with the grid electrode of the sixth PMOS tube MP6, and the drain electrode of a seventh PMOS tube MP7 is connected with the drain electrode of a ninth NMOS tube MN9 and is connected with a voltage signal VC1; the gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are connected and connected with the drain of the seventh NMOS transistor MN 7; the drain electrode of the eighth NMOS transistor MN8 is connected with the drain electrode of the sixth PMOS transistor MP6, and the source electrode of the eighth NMOS transistor MN8 is connected with the collector electrode of the seventh NPN transistor Q7; the source electrode of the ninth NMOS tube MN9 is connected with the collector electrode of the eighth NPN tube Q8; the bases of the eighth NPN tube Q8 and the ninth NPN tube Q9 are connected to form a current mirror structure, and the emitters of the current mirror structure are connected to GND; a collector of the ninth NPN tube Q9 is connected with a base electrode of the ninth NPN tube; the gate of the eighth PMOS tube MP8 is connected with the voltage signal VC1, the drain of the eighth PMOS tube MP8 is connected with GND, and the source of the eighth PMOS tube MP8 is connected with the Nth-level buck signal VN; the ninth PMOS transistor MP9 has a gate connected to the nth step-down signal VN, a source connected to the 1 st step-down signal V1 as the first input terminal of the tail regulator output link 4, and a drain outputting the supply voltage VOUT as the output terminal of the tail regulator output link 4; the fifth resistor R5 and the sixth resistor R6 are connected in series and bridged between the drain of the ninth PMOS transistor MP9 and GND, and the common end of the fifth resistor R5 and the sixth resistor R6 is connected with the feedback voltage VFB.

The bias stage output link 5 comprises two resistors, namely a twelfth resistor R12, a thirteenth resistor R13, a fourteenth PNP transistor Q14, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22 and a sixteenth NMOS transistor MN16; wherein: the source electrodes of the fourteenth to sixteenth PMOS transistors MP14 to MP16 are connected and a second input terminal of the bias stage output link 5 is connected to the 1 st stage buck signal V1, and the gate electrodes thereof are connected to the drain electrode of the sixteenth PMOS transistor MP 16; the drain electrode of a fourteenth PMOS tube MP14 is connected with the source electrode of the twenty-first PMOS tube MP21, and the drain electrode of a fifteenth PMOS tube MP15 is connected with the source electrode of the twenty-second PMOS tube MP 22; the gates of the twenty-first PMOS tube MP21 and the twenty-second PMOS tube MP22 are connected and used as the first input end of the bias stage output link 5 to be connected with the starting voltage A, and the drain of the twenty-first PMOS tube MP21 is used as the third output end of the bias stage output link 5 and outputs the bias current IBO; the drain of the twenty-second PMOS transistor MP22 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the emitter of the fourteenth PNP transistor Q14 through the thirteenth resistor R13; a common end of the twelfth resistor R12 and the thirteenth resistor R13 serves as a second output end of the bias stage output link 5, and outputs a reference voltage VBO; the base electrode and the collector of the fourteenth PNP tube Q14 are connected to GND; the drain of the sixteenth NMOS transistor MN16 is connected to the drain of the sixteenth PMOS transistor MP16, the gate of the sixteenth NMOS transistor MN16 is connected to the bias voltage VB2 as the third input terminal of the bias stage output link 5, and the source of the sixteenth NMOS transistor MN16 is connected to GND.

Compared with the prior art, the invention has the following advantages:

1. the invention adopts the modularized design, uses the bias stage starting link 2 to quickly start the bias stage 3, adopts the micro-current source structure consisting of triodes or transistors to quickly generate the positive temperature current, and outputs the bias voltage VB to the tail voltage stabilizing output link 4, so that the tail voltage stabilizing output link can quickly and stably work, and further obtains the stable power supply voltage VOUT. The circuit complexity is reduced, and the working efficiency of the whole circuit system is improved.

2. Because the design combining N-level gradient voltage reduction and tail voltage stabilization is adopted, after the input high voltage is reduced to a low voltage range, the circuit can be designed by adopting a lower voltage-resistant device, the indexes of precision, stability and the like of output voltage VOUT are ensured, the high-voltage input protection and output performance of the circuit are considered, the optimization of the circuit performance is favorably realized, and the circuit layout area is reduced.

3. Because the invention adopts the design of combining bias priority intervention and tail voltage stabilization, the bias level link 3 preferably intervenes the tail voltage stabilization output link 4, thereby improving the starting speed and simultaneously ensuring the precision and the stability of the output voltage VOUT of the tail voltage stabilization output link 4, and simultaneously, the bias level output link 5 can provide reference voltage and bias current for other circuits to quickly start other circuits.

Drawings

FIG. 1 is a schematic diagram of an overall structure of a soft-start voltage stabilizing circuit in the patent application with application publication number CN 107656570A;

FIG. 2 is a schematic diagram of a buck regulator circuit according to application publication No. CN 112135394A;

FIG. 3 is a functional block diagram of the present invention;

FIG. 4 is a schematic diagram of a specific circuit with a two-stage gradient buck link 1 and a tail regulated output link 4 according to a first embodiment of the present invention;

fig. 5 is a schematic diagram of a specific circuit principle of the bias stage starting link 2, the bias stage link 3 and the bias stage output link 5 in the first embodiment of the present invention.

FIG. 6 is a schematic diagram of a specific circuit with a four-stage gradient buck link 1 and a tail regulated output link 4 according to a second embodiment of the present invention;

Detailed Description

The invention is described in further detail below with reference to the figures and the specific embodiments.

Referring to fig. 3, the invention provides a fast start voltage stabilizing circuit with bias priority intervention, comprising an N (N > 1) level gradient buck link 1, a bias level start link 2, a bias level link 3, a tail voltage stabilizing output link 4, and a bias level output link 5, wherein:

the N-stage gradient voltage reduction link 1 is configured to perform multi-stage voltage reduction processing on an input power supply voltage VIN; the first output end outputs a 1 st-level buck signal V1; the second output end outputs an Nth-stage buck signal VN; in the N-stage gradient voltage-reducing link 1, the supply voltage VIN at the input end can be derived from voltages generated by other circuit modules in the chip, or can be directly derived from a voltage input by an external pin of the chip, wherein the voltage value range of VIN can cover 10V-100V.

The bias stage starting link 2 is used for starting the bias stage link 3 to enable the bias stage link 3 to be rapidly separated from a static state of zero current, and the input end of the bias stage starting link is connected with the 1 st stage buck signal V1; the power supply is provided with two output ends, wherein the first output end outputs a starting voltage A, and the second output end outputs a starting voltage B;

the bias stage link 3 is used for rapidly generating a bias voltage VB and is provided with three input ends and two output ends, the first input end is connected with a 1 st-stage buck signal V1, the second input end is connected with a starting voltage A, the third input end is connected with a starting voltage B, the first output end outputs the bias voltage VB and is connected to the tail voltage stabilization output link 4, and the second output end outputs the bias voltage VB2 and is connected to the bias stage output link (5);

the tail voltage stabilization output link 4 is used for generating stable output power supply voltage, and is provided with four input ends and an output end, wherein the first input end is connected with a 1 st-stage step-down signal V1, the second input end is connected with an N-stage step-down signal VN, the third input end is connected with a bias voltage VB, the fourth input end is connected with a starting voltage A, and the input current IA of the fourth input end is the bias current of the module; the output end is used as a first output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a supply voltage VOUT;

the bias stage output link 5 is used for generating an output reference voltage VBO and a bias current IBO, and is provided with three input ends and two output ends, wherein the first input end is connected with a starting voltage a, the second input end is connected with a 1 st-stage buck signal V1, and the third input end is connected with a bias voltage VB2; the first output end is used as a second output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the reference voltage VBO, and the second output end is used as a third output end of the whole rapid start voltage stabilizing circuit with the bias level priority intervention and outputs the bias current IBO.

Example 1

Referring to fig. 4, as a first preferred option, N of the N-stage gradient buck link 1 is 2, that is, the two-stage gradient buck link includes 2 voltage-dividing resistors, namely, a first voltage-dividing resistor RS1 and a second voltage-dividing resistor RS2,2 voltage-dividing NMOS transistors, namely, a first voltage-dividing NMOS transistor MNS1 and a second voltage-dividing NMOS transistor MNS2, and three voltage-stabilizing diodes, namely, a first voltage-stabilizing diode Z1, a second voltage-stabilizing diode Z2, and a third voltage-stabilizing diode Z3; wherein:

the 2 voltage reduction NMOS tubes MNS 1-MNS 2 are sequentially connected in series, the drain electrode of the first voltage reduction NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first voltage reduction NMOS tube MNS1 is connected with the drain electrode of the second voltage reduction NMOS tube MNS2 and serves as the first output end of the N-stage gradient voltage reduction link 1 and outputs a 1-stage voltage reduction signal V1, and the source electrode of the second voltage reduction NMOS tube MNS2 serves as the second output end of the two-stage gradient voltage reduction link 1 and outputs a 2-stage voltage reduction signal V2;

the 2 voltage dividing resistors RS 1-RS 2 are sequentially connected in series to form a series circuit, one end of the first voltage dividing resistor RS1 is connected with the drain electrode of the first voltage-reducing NMOS tube MNS1, the common end of the first voltage dividing resistor RS1 and the second voltage dividing resistor RS2 is connected with the grid electrode of the first voltage-reducing NMOS tube MNS1, and the other end of the second voltage dividing resistor RS2 is connected with the grid electrode of the second voltage-reducing NMOS tube MNS 2;

the three voltage stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage reducing NMOS tube, the positive end of the first voltage stabilizing diode Z1 is connected with the negative end of the second voltage stabilizing diode Z2, the positive end of the second voltage stabilizing diode Z2 is connected with the negative end of the third voltage stabilizing diode Z3, and the positive end of the third voltage stabilizing diode Z3 is connected with GND.

The tail voltage stabilization output link 4 adopts an operational amplifier negative feedback voltage stabilization structure and uses a bias voltage VB and a bias current IA for preferential intervention to ensure the generation speed and the accuracy of the final output power supply voltage VOUT of the rapid start voltage stabilization circuit with the bias level preferential intervention, and comprises four resistors, namely a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, four PNP tubes, namely a first PNP tube Q1, a second PNP tube Q2, a fourth PNP tube Q4 and a fifth PNP tube Q5, five NPN tubes, namely a third NPN tube Q3, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth PMOS tube Q8 and a ninth PMOS tube Q9, nine PMOS tubes, namely a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a seventh PMOS tube MP9, a third PMOS tube MP3, a fourth PMOS tube MN4, a fifth PMOS tube NMOS 5, a ninth PMOS tube NMOS 5, a seventh PMOS tube MN6, a seventh PMOS tube MN8, a ninth PMOS tube MN9, a ninth NMOS 5, a seventh PMOS tube NMOS 9, a seventh PMOS tube NMOS 5, a sixth PMOS tube MN4, a seventh PMOS tube NMOS 5, a seventh PMOS tube NMOS 9, a sixth PMOS tube NMOS 5, a fifth NMOS 5, a sixth PMOS tube NMOS 9; wherein:

the first PNP tube Q1 and the second PNP tube Q2 form a current mirror structure, the emitting electrodes of the first PNP tube Q1 and the second PNP tube Q2 are connected with the Nth-level buck signal VN, the base electrodes of the first PNP tube Q1 and the second PNP tube Q2 are connected with the collector electrode of the first PNP tube Q1, the collector electrode of the second PNP tube Q2 is connected with the base electrode of the third NPN tube Q3, the second input end of the collector electrode of the third NPN tube Q3 serving as a tail voltage stabilization output link (4) is connected with the Nth-level buck signal VN, and the emitting electrode of the third NPN tube Q3 is connected with the voltage signal VC1;

the sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are all connected to GND, and the grids thereof are connected to form a current mirror structure; the drain electrode of the third NMOS tube MN3 is connected with the grid electrode of the third NMOS tube and is used as a fourth input end of the tail voltage stabilization output link (4) to be connected with the starting voltage A, the input current of the input end is bias current IA, the drain electrode of the fourth NMOS tube MN4 is connected with the collector electrode of the first PNP tube Q1, the drain electrode of the fifth NMOS tube MN5 is connected with the collector electrode of the second PNP tube Q2, and the drain electrode of the sixth NMOS tube MN6 is connected with the first PMOS tube MP1;

the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are all connected with the Nth-stage buck signal VN, and the grid electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to form a current mirror structure; the drain electrode of a first PMOS (P-channel metal oxide semiconductor) tube MP1 is connected with the grid electrode of the first PMOS tube MP1, the drain electrode of a second PMOS tube MP2 is connected with the drain electrode of a seventh NMOS (N-channel metal oxide semiconductor) tube MN7, the drain electrode of a third PMOS tube MP3 is connected with the collector electrode of a sixth NPN (negative-positive-negative) tube Q6, the drain electrode of a fourth PMOS tube MP4 is connected with the emitter electrode of a fourth PNP tube Q4 through a third resistor R3, and the drain electrode of a fifth PMOS tube MP5 is connected with the collector electrode of a ninth NPN tube Q9;

the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode and is connected with the grid electrode of the eighth NMOS transistor MN8, and the source electrode of the seventh NMOS transistor MN7 is connected with GND;

the fourth PNP tube Q4 and the fifth PNP tube Q5 form a differential pair tube input, the base electrode of the fourth PNP tube Q4 is used as a third input end of the tail voltage stabilization output link (4) to be connected with a bias voltage VB, and the collector electrode of the fourth PNP tube Q4 is connected with the collector electrode of the eighth NPN tube Q8; the base electrode of the fifth PNP tube Q5 is connected with the feedback voltage VFB, the collector electrode of the fifth PNP tube Q5 is connected with the collector electrode of the seventh NPN tube Q7, and the emitter electrode of the fifth PNP tube Q5 is connected with the drain electrode of the fourth PMOS tube MP4 through a fourth resistor R4;

bases of the sixth NPN tube Q6 and the seventh NPN tube Q7 are connected to form a current mirror structure, and emitters of the current mirror structure are connected to GND; a collector of a sixth NPN tube Q6 is connected with a base electrode of the sixth NPN tube Q6;

the source electrodes of the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are both connected with the Nth-level voltage reduction signal VN, and the grid electrodes thereof are connected to form a current mirror structure; the drain electrode of a sixth PMOS tube MP6 is connected with the grid electrode of the sixth PMOS tube MP6, and the drain electrode of a seventh PMOS tube MP7 is connected with the drain electrode of a ninth NMOS tube MN9 and is connected with a voltage signal VC1;

the eighth NMOS transistor MN8 is connected with the ninth NMOS transistor MN9 through the grid electrode and is connected with the drain electrode of the seventh NMOS transistor MN 7; the drain electrode of the eighth NMOS transistor MN8 is connected with the drain electrode of the sixth PMOS transistor MP6, and the source electrode of the eighth NMOS transistor MN8 is connected with the collector electrode of the seventh NPN transistor Q7; the source electrode of the ninth NMOS transistor MN9 is connected with the collector electrode of the eighth NPN transistor Q8;

the bases of the eighth NPN tube Q8 and the ninth NPN tube Q9 are connected to form a current mirror structure, and the emitters of the current mirror structure are connected to GND; a collector of the ninth NPN tube Q9 is connected with a base electrode of the ninth NPN tube;

the gate of the eighth PMOS transistor MP8 is connected with a voltage signal VC1, the drain of the eighth PMOS transistor MP8 is connected with GND, and the source of the eighth PMOS transistor MP8 is connected with an Nth-stage buck signal VN;

the ninth PMOS transistor MP9 has a gate connected to the nth-stage buck signal VN, a source connected to the 1 st-stage buck signal V1 as the first input terminal of the tail regulated output link 4, and a drain outputting the supply voltage VOUT as the output terminal of the tail regulated output link 4;

the fifth resistor R5 and the sixth resistor R6 are connected in series and bridged between the drain electrode of the ninth PMOS tube MP9 and GND, and the common end of the fifth resistor R5 and the sixth resistor R6 is connected with the feedback voltage VFB.

Referring to fig. 5, the bias stage starting link 2 includes a seventh resistor R7, and tenth NPN transistors Q10 and eleventh NPN transistors Q11; wherein:

one end of the seventh resistor R7 is connected to the 1 st-level buck signal V1, the other end of the seventh resistor R is connected to the base of the tenth NPN transistor Q10 and the collector of the eleventh NPN transistor Q11, both the emitter of the tenth NPN transistor Q10 and the emitter of the eleventh NPN transistor Q11 are connected to GND, the drain of the tenth NPN transistor Q10 and the gate of the eleventh NPN transistor Q11 output a start voltage a and a start voltage B, respectively, and the current of the start voltage a corresponding to the node a is the bias current IA.

The bias stage link 3 comprises four resistors, namely an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11, two NPN transistors, namely a twelfth NPN transistor Q12 and a thirteenth NPN transistor Q13, nine PMOS transistors, namely a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20 and a twenty third PMOS transistor MP23, and six NMOS transistors, namely a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14 and a fifteenth NMOS transistor MN15; wherein:

the tenth PMOS transistor MP10 to the thirteenth PMOS transistor MP13 have sources connected to the first input terminal serving as the bias stage link 3 and connected to the 1 st buck signal V1, gates connected to the drain of the eighteenth PMOS transistor MP18, and drains connected to the sources of the seventeenth PMOS transistor MP17 to the twentieth PMOS transistor MP20, respectively, to form a PMOS cascode current mirror structure; the gates of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 are connected and serve as the second input end of the bias stage link 3 to be connected with the starting voltage A, the drain of the seventeenth PMOS tube MP17 is connected with the starting voltage B through an eighth resistor R8, the drain of the eighteenth PMOS tube MP18 is connected with the starting voltage A through a ninth resistor R9, the drain of the nineteenth PMOS tube MP19 is connected with the drain of the fourteenth NMOS tube MN14, and the drain of the twentieth PMOS tube MP20 is connected with the drain of the twelfth NMOS tube MN 12;

the tenth NMOS transistor MN10 is connected with the gate of the eleventh NMOS transistor MN11 and is connected to the drain of the tenth NMOS transistor MN10, the drain of the tenth NMOS transistor MN10 is connected with the starting voltage B as the third input end of the bias stage link 3, and the source of the tenth NMOS transistor MN10 is connected with the collector of a twelfth NPN transistor Q12; the drain electrode of the eleventh NMOS tube MN11 is connected with the starting voltage A; bases of the twelfth NPN tube Q12 and the thirteenth NPN tube Q13 are connected with a collector of the twelfth NPN tube Q12, an emitter of the twelfth NPN tube Q12 is connected with GND, and an emitter of the thirteenth NPN tube Q13 is connected with GND through the tenth resistor R10; the gates of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are connected and are connected to the drain of the twelfth NMOS transistor MN12, the source of the twelfth NMOS transistor MN12 is connected with the source of the twenty-third PMOS transistor MP23, and the gate and the drain of the twenty-third PMOS transistor MP23 are both connected to GND; the drain electrode of the thirteenth NMOS transistor MN13 is connected with the 1 st-level buck signal V1 through the eleventh resistor R11, and the source electrode of the thirteenth NMOS transistor MN is connected with the drain electrode of the fifteenth NMOS transistor MN15 and used as the first output end of the bias stage link 3 to output the bias voltage VB; sources of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are connected to GND, gates of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 are connected and used as a second output end of the bias stage link 3 to output bias voltage VB2, and a drain of the fourteenth NMOS transistor MN14 is connected with a gate of the fourteenth NMOS transistor MN 14.

In the bias stage link 3, a micro-current source structure composed of triodes or transistors is adopted to quickly generate the positive temperature current, the current value and the temperature coefficient of the positive temperature current can be modified by adjusting the number ratio of the triodes or the transistors and the resistance value of a micro-current source resistor, and in the embodiment, the bias current IA corresponding to the node A is taken to be 0.25uA. In addition, the positive temperature current is taken as the leakage current of a thirteenth NMOS transistor MN13 located in the saturation region, and the voltage value and the temperature coefficient of the gate-source voltage of the NMOS transistor are modified by adjusting the width-to-length ratio parameter of the NMOS transistor, so as to be taken as the output of the bias voltage VB of the bias stage link 3, where in this embodiment, the bias voltage VB is taken as 2.5V.

The bias level output link 5 is used for processing the bias voltage VB and the bias current IA provided by the bias level link 3 to generate the bias voltage VBO and the bias current IBO which are finally output by the rapid start voltage stabilizing circuit with the bias level priority intervention and are designed by the invention; the circuit comprises a twelfth resistor R12, a thirteenth resistor R13, a PNP tube, a fourteenth PNP tube Q14, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a sixteenth PMOS tube MP16, a twenty-first PMOS tube MP21, a twenty-second PMOS tube MP22 and a sixteenth NMOS tube MN16; wherein: the source electrodes of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected, the second input end serving as the bias stage output link 5 is connected with the 1 st-stage buck signal V1, and the grid electrodes of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected with the drain electrode of the sixteenth PMOS tube MP 16; the drain electrode of a fourteenth PMOS (P-channel metal oxide semiconductor) tube MP14 is connected with the source electrode of the twenty-first PMOS tube MP21, and the drain electrode of a fifteenth PMOS tube MP15 is connected with the source electrode of the twenty-second PMOS tube MP 22; the gates of the twenty-first PMOS tube MP21 and the twenty-second PMOS tube MP22 are connected and used as the first input end of the bias stage output link 5 to be connected with the starting voltage A, and the drain of the twenty-first PMOS tube MP21 is used as the third output end of the bias stage output link 5 and outputs the bias current IBO; the drain of the twenty-second PMOS transistor MP22 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the emitter of the fourteenth PNP transistor Q14 through the thirteenth resistor R13; a common end of the twelfth resistor R12 and the thirteenth resistor R13 serves as a second output end of the bias stage output link 5, and outputs a reference voltage VBO; the base electrode and the collector electrode of the fourteenth PNP tube Q14 are connected to GND; the drain electrode of the sixteenth NMOS transistor MN16 is connected with the drain electrode of the sixteenth PMOS transistor MP16, the grid electrode of the sixteenth NMOS transistor MN16 is used as the third input end of the bias level output link 5 to be connected with the bias voltage VB2, and the source electrode of the sixteenth NMOS transistor MN16 is connected to GND.

The working principle of the invention is as follows:

referring to fig. 4, in this embodiment, there are two specific circuit portions of the N-stage gradient buck link 1 and the tail regulator output link 4 in this embodiment. In this embodiment, the function of the N-level gradient step-down link 1 is mainly realized by high-voltage tubes MNS1 and MNS2, zener diodes Z1, Z2, and Z3, and large resistors RS1 and RS 2. The stable voltage value (reverse breakdown voltage value) of a single voltage-stabilizing tube of Z1-Z3 is 5.8V, so that under the condition that the R1, the R2 and the Z1-Z3 are connected in series for voltage stabilization, voltage which is three times of the stable voltage value (reverse breakdown voltage value) of the voltage-stabilizing tube can be generated at the negative electrode of the Z1, and the voltage is about 17.4V; the resistance values of R1 and R2 which are selected and used by matching with the rated current and rated voltage parameters of the voltage regulator tube are both 550 kilo-ohm. The extreme values of the gate-source voltage, the drain-source voltage and the voltage between the drain terminal and the reference ground are analyzed in the aspects of voltage resistance selection and circuit device protection of the devices of the high-voltage tubes MNS1 and MNS 2. The source end voltage of MNS2 is about 16V, when VIN is up to 100V, half of the voltage difference value of two voltages is applied between the drain source of MNS1 and the drain source of MNS2, and the voltage difference value is about 42V; meanwhile, considering that the limit values of the drain terminal voltages of the MNS1 and the MNS2 are 100V and 58V, respectively, it is sufficient to select the MNS1 as a high voltage 100V device and the MN2 as a high voltage 60V device.

Referring to fig. 4, in this embodiment, the tail regulator output link 4 adopts an operational amplifier structure to improve the precision and stability of voltage reduction and regulation, and the high-voltage pipes MN3 to MN6 and the high-voltage pipes MP1 to MP5 are typical NMOS and PMOS basic current mirror structures, respectively. Q1-Q3 are starting circuits of operational amplifier structures, VOUT is not established when the circuit is just powered on, the feedback voltage is very low and is approximately close to the reference ground voltage, so that the collector voltage of Q5 is very high, the output control voltage VC1 is very low after passing through a current mirror load formed by MP6 and MP7, and the abnormal state can cause the grid voltage of MP9 to be very low, so that the working state of MP9 deviates from the normal state. Therefore, a starting circuit composed of Q1-Q3 is needed, Q1 and Q2 form a typical current mirror structure, the base voltage of Q3 is fixed to be the voltage of power supply VN and is reduced by Vec voltage of Q2, then when the circuit is just powered on and the control voltage VC1 is very low, vbe of Q3 is far greater than the conducting voltage, and at the moment, the emitter (control voltage VC 1) of Q3 is pulled high; when the operational amplifier structure enters a normal working state, the control voltage VC1 reaches a constant high voltage value and is dynamically adjusted within a certain range, and when the Vbe of the Q3 is not more than the breakover voltage, the operational amplifier structure enters a cut-off area to be cut off, so that the operational amplifier structure is started.

Referring to fig. 5, there are three specific circuits of the bias stage start-up element 2, the bias stage element 3 and the bias stage output element 5 in this embodiment. MN 14-MN 16 are typical NMOS basic current mirror structures, and MP 10-MP 16 and high-voltage tubes MP 17-MP 22 are mirror tubes and cascode tubes in the PMOS cascode current mirror structures respectively.

Referring to fig. 5, the bias stage starting link 2 in this embodiment includes Q10, Q11 and a resistor R7, when the circuit starts to power up, the cascode loop structure formed by MP10, MP11, MP16, MP17, MN10, MN11, Q12 and Q13 is independent of the supply voltage V1, that is, after the supply voltage V1 is powered up, all transistors of the two branches can maintain a stable state before being powered up, so that branches on both sides of the loop transmit zero current and always maintain an infinite steady state, and cannot start up, and therefore the starting circuit of the bias stage starting link 2 in this embodiment helps the circuit to get rid of the stable state.

Example 2

Referring to fig. 6, as a second preferred option, N of the N-stage gradient buck link 1 is 4, that is, the 4-stage gradient buck link includes 4 voltage-dividing resistors, namely, a first voltage-dividing resistor RS1, a second voltage-dividing resistor RS2,. Ang., a 4-th voltage-dividing resistor RS4, 4 voltage-dividing NMOS transistors, namely, a first voltage-dividing NMOS transistor MNS1, a second voltage-dividing NMOS transistor MNS2,. Ang., a 4-th voltage-dividing NMOS transistor MNS4, and three voltage-stabilizing diodes, namely, a first voltage-stabilizing diode Z1, a second voltage-stabilizing diode Z2, and a third voltage-stabilizing diode Z3; wherein:

the 4 step-down NMOS tubes MNS 1-MNS 4 are sequentially connected in series, the drain electrode of the first step-down NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first step-down NMOS tube MNS1 is connected with the drain electrode of the second step-down NMOS tube MNS2 and serves as the first output end of the 4-level gradient step-down link 1, and outputs a 1-level step-down signal V1, the source electrode of the second step-down NMOS tube MNS2 is connected with the drain electrode of the third step-down NMOS tube MNS3, the process is repeated, the source electrode MNS3 of the 3-level step-down NMOS tube is connected with the drain electrode of the 4-level step-down NMOS tube MNS4, and the source electrode of the 4-level step-down NMOS tube MNS4 serves as the second output end of the 4-level gradient step-down link 1, and outputs a 4-level step-down signal V4;

the 4 voltage dividing resistors RS 1-RS 4 are sequentially connected in series to form a series circuit, one end of a first voltage dividing resistor RS1 is connected with a drain electrode of a first voltage-reducing NMOS tube MNS1, a common end of the first voltage dividing resistor RS1 and a common end of a second voltage dividing resistor RS2 are connected with a grid electrode of the first voltage-reducing NMOS tube MNS1, a common end of the second voltage dividing resistor RS2 and a common end of a third voltage dividing resistor RS3 are connected with a grid electrode of a second voltage-reducing NMOS tube MNS2, and so on, a common end of a 3 rd voltage dividing resistor RS3 and a 3 rd voltage dividing resistor RS4 is connected with a grid electrode of a 3 rd voltage-reducing NMOS tube MNS3, and the other end of the 3 rd voltage dividing resistor RS3 is connected with a grid electrode of an Nth voltage-reducing NMOS tube MNS 3;

The other modules are the same as those in embodiment 1. The selection of the stage number N of the N-stage gradient voltage reduction link 1 is determined according to the range of the specific input voltage VIN and the actual situation, and N >1 may be selected.

The above examples only show two specific embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims

1. The utility model provides a take quick start voltage stabilizing circuit of bias level priority intervention, which comprises N (N > 1) grade gradient step-down link (1), bias level start-up link (2), bias level link (3), tail steady voltage output link (4), bias level output link (5), wherein:

the N (N > 1) level gradient voltage reduction link (1) is used for carrying out multi-level voltage reduction processing on the input power supply voltage VIN; the first output end outputs a 1 st-level buck signal V1; the second output end outputs an Nth-stage buck signal VN; the voltage stabilizing circuit comprises N (N > 1) divider resistors, namely a first divider resistor RS1, a second divider resistor RS2, a voltage-dividing resistor RSN, N voltage-reducing NMOS tubes, namely a first voltage-reducing NMOS tube MNS1, a second voltage-reducing NMOS tube MNS2, a voltage-dividing NMOS tube MNSN, three voltage-stabilizing diodes, namely a first voltage-stabilizing diode Z1, a second voltage-stabilizing diode Z2 and a third voltage-stabilizing diode Z3; wherein:

the N voltage-reducing NMOS tubes MNS 1-MNSN are sequentially connected in series, the drain electrode of the first voltage-reducing NMOS tube MNS1 is connected with an input power supply voltage VIN, the source electrode of the first voltage-reducing NMOS tube MNS1 is connected with the drain electrode of the second voltage-reducing NMOS tube MNS2 and serves as the first output end of the N-level gradient voltage-reducing link (1) and outputs a 1-level voltage-reducing signal V1, the source electrode of the second voltage-reducing NMOS tube MNS2 is connected with the drain electrode of the third voltage-reducing NMOS tube MNS3, the process is repeated, the source electrode MNSN-1 of the N-1 voltage-reducing NMOS tube is connected with the drain electrode of the N-level voltage-reducing NMOS tube MNSN, and the source electrode of the N-level voltage-reducing NMOS tube MNSN serves as the second output end of the N-level gradient voltage-reducing link (1) and outputs an N-level voltage-reducing signal VN;

the N voltage-dividing resistors RS 1-RSN are sequentially connected in series to form a series circuit, one end of a first voltage-dividing resistor RS1 is connected with the drain electrode of a first voltage-dividing NMOS tube MNS1, the common end of the first voltage-dividing resistor RS1 and a second voltage-dividing resistor RS2 is connected with the grid electrode of the first voltage-dividing NMOS tube MNS1, the common end of a second voltage-dividing resistor RS2 and a third voltage-dividing resistor RS3 is connected with the grid electrode of a second voltage-dividing NMOS tube MNS2, so forth, the common end of an N-1 voltage-dividing resistor RSN-1 and an N voltage-dividing resistor RSN is connected with the grid electrode of an N-1 voltage-dividing NMOS tube MNSN, and the other end of the N voltage-dividing resistor RSN is connected with the grid electrode of an N voltage-dividing NMOS tube MNSN;

the three voltage stabilizing diodes Z1-Z3 form a series circuit, the negative end of the first voltage stabilizing diode Z1 is connected with the MNSN grid of the Nth voltage reducing NMOS tube, the positive end of the first voltage stabilizing diode Z1 is connected with the negative end of the second voltage stabilizing diode Z2, the positive end of the second voltage stabilizing diode Z2 is connected with the negative end of the third voltage stabilizing diode Z3, and the positive end of the third voltage stabilizing diode Z3 is connected with GND;

the bias stage starting link (2) is used for starting the bias stage link (3) to enable the bias stage link to be rapidly separated from a static state of zero current, and the input end of the bias stage starting link is connected with a 1 st stage buck signal V1; the power supply is provided with two output ends, wherein the first output end outputs a starting voltage A, and the second output end outputs a starting voltage B; the circuit comprises a seventh resistor R7, a tenth NPN tube Q10 and an eleventh NPN tube Q11 of two NPN tubes; wherein:

one end of the seventh resistor R7 serving as an input end of the bias stage starting link (2) is connected to the 1 st-level buck signal V1, the other end of the seventh resistor R is connected to a base of the tenth NPN transistor Q10 and a collector of the eleventh NPN transistor Q11, an emitter of the tenth NPN transistor Q10 and an emitter of the eleventh NPN transistor Q11 are both connected to GND, and a collector of the tenth NPN transistor Q10 serving as a first output end of the bias stage starting link (2) outputs a starting voltage a; the base electrode of the eleventh NPN tube Q11 is used as the second output end of the bias stage starting link (2) to output a starting voltage B;

the bias stage link (3) is used for quickly generating a bias voltage VB and is provided with three input ends and two output ends, the first input end is connected with a 1 st-stage step-down signal V1, the second input end is connected with a starting voltage A, the third input end is connected with a starting voltage B, the first output end outputs the bias voltage VB and is connected to the tail voltage stabilization output link (4), and the second output end outputs the bias voltage VB2 and is connected to the bias stage output link (5); the high-voltage power supply comprises four resistors, namely an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11, two NPN transistors, namely a twelfth NPN transistor Q12 and a thirteenth NPN transistor Q13, nine PMOS transistors, namely a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20 and a twenty-third PMOS transistor MP23, and six NMOS transistors, namely a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14 and a fifteenth NMOS transistor MN15; wherein:

the source electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the first input end serving as the bias stage link (3) and connected with the 1 st-stage buck signal V1, the grid electrodes of the tenth PMOS tube MP10 to the thirteenth PMOS tube MP13 are connected with the drain electrode of the eighteenth PMOS tube MP18, and the drain electrodes of the tenth PMOS tube MP10 to the twentieth PMOS tube MP20 are respectively connected with the source electrodes of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 to form a PMOS cascode current mirror structure; the gates of the seventeenth PMOS tube MP17 to the twentieth PMOS tube MP20 are connected and serve as the second input end of the bias stage link (3) to be connected with the starting voltage A, the drain of the seventeenth PMOS tube MP17 is connected with the starting voltage B through an eighth resistor R8, the drain of the eighteenth PMOS tube MP18 is connected with the starting voltage A through a ninth resistor R9, the drain of the nineteenth PMOS tube MP19 is connected with the drain of the fourteenth NMOS tube MN14, and the drain of the twentieth PMOS tube MP20 is connected with the drain of the twelfth NMOS tube MN 12;

the tenth NMOS transistor MN10 is connected with the gate electrode of the eleventh NMOS transistor MN11 and is connected to the drain electrode of the tenth NMOS transistor MN10, the drain electrode of the tenth NMOS transistor MN10 serving as the third input end of the biasing stage link (3) is connected with the starting voltage B, and the source electrode of the tenth NMOS transistor MN is connected with the collector electrode of a twelfth NPN transistor Q12; the drain electrode of the eleventh NMOS tube MN11 is connected with the starting voltage A, and the source electrode of the eleventh NMOS tube MN is connected with the collector electrode of the thirteenth NPN tube Q13;

the bases of the twelfth NPN transistor Q12 and the thirteenth NPN transistor Q13 are connected to the collector of the twelfth NPN transistor Q12, the emitter of the twelfth NPN transistor Q12 is connected to GND, and the emitter of the thirteenth NPN transistor Q13 is connected to GND through the tenth resistor R10;

the gates of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are connected and connected to the drain of the twelfth NMOS transistor MN12, the source of the twelfth NMOS transistor MN12 is connected with the source of the twenty-third PMOS transistor MP23, and the gate and the drain of the twenty-third PMOS transistor MP23 are both connected to GND; the drain electrode of the thirteenth NMOS transistor MN13 is connected with the 1 st-stage buck signal V1 through the eleventh resistor R11, and the source electrode of the thirteenth NMOS transistor MN is connected with the drain electrode of the fifteenth NMOS transistor MN15 and used as the first output end of the biasing stage link (3) to output a biasing voltage VB;

sources of the fourteenth NMOS tube MN14 and the fifteenth NMOS tube MN15 are connected to GND, gates of the fourteenth NMOS tube MN14 and the fifteenth NMOS tube MN15 are connected and serve as a second output end of the bias stage link (3) to output bias voltage VB2, and a drain of the fourteenth NMOS tube MN14 is connected with a gate of the fourteenth NMOS tube;

the bias level link (3) adopts a micro-current source structure consisting of triodes or transistors to quickly generate a positive temperature current, and the current value and the temperature coefficient of the positive temperature current can be modified by adjusting the number ratio of the triodes or the transistors and the resistance value of a micro-current source resistor to be used as the bias current output of the bias level link (3);

the bias stage link (3) takes the positive temperature current as the leakage current of the transistor in the saturation region, modifies the voltage value and the temperature coefficient of the gate-source voltage of the transistor by adjusting the width-length ratio parameter of the transistor, and outputs the bias voltage VB of the bias stage link (3);

the tail voltage stabilization output link (4) is used for generating stable output power supply voltage and is provided with four input ends and an output end, wherein the first input end is connected with a 1 st-level buck signal V1, the second input end is connected with an Nth-level buck signal VN, the third input end is connected with a bias voltage VB, and the fourth input end is connected with a starting voltage A; the output end is used as a first output end of the whole quick start voltage stabilizing circuit with bias priority intervention and outputs a supply voltage VOUT; the three-phase NMOS transistor comprises four resistors, namely a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, four PNP transistors, namely a first PNP transistor Q1, a second PNP transistor Q2, a fourth PNP transistor Q4 and a fifth PNP transistor Q5, five NPN transistors, namely a third NPN transistor Q3, a sixth NPN transistor Q6, a seventh NPN transistor Q7, an eighth NPN transistor Q8 and a ninth NPN transistor Q9, nine PMOS transistors, namely a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth transistor MP8 and a ninth PMOS transistor MP9, seven NMOS transistors, namely a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; wherein:

the sources of the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are all connected to GND, and the grids of the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are connected to form a current mirror structure; the drain electrode of the third NMOS tube MN3 is connected with the grid electrode of the third NMOS tube and serves as a fourth input end of the tail voltage stabilization output link (4) to be connected with the starting voltage A, the drain electrode of the fourth NMOS tube MN4 is connected with the collector electrode of the first PNP tube Q1, the drain electrode of the fifth NMOS tube MN5 is connected with the collector electrode of the second PNP tube Q2, and the drain electrode of the sixth NMOS tube MN6 is connected with the first PMOS tube MP1;

the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are all connected with the Nth-stage voltage reduction signal VN, and the grid electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to form a current mirror structure; the drain electrode of the first PMOS tube MP1 is connected with the grid electrode of the first PMOS tube MP1, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the seventh NMOS tube MN7, the drain electrode of the third PMOS tube MP3 is connected with the collector electrode of the sixth NPN tube Q6, the drain electrode of the fourth PMOS tube MP4 is connected with the emitter electrode of the fourth PNP tube Q4 through a third resistor R3, and the drain electrode of the fifth PMOS tube MP5 is connected with the collector electrode of the ninth NPN tube Q9;

the fourth PNP tube Q4 and the fifth PNP tube Q5 form a differential pair tube input, the base electrode of the fourth PNP tube Q4 serving as the third input end of the tail voltage stabilization output link (4) is connected with a bias voltage VB, and the collector electrode of the fourth PNP tube Q4 is connected with the collector electrode of the eighth NPN tube Q8; the base electrode of the fifth PNP tube Q5 is connected with the feedback voltage VFB, the collector electrode of the fifth PNP tube Q5 is connected with the collector electrode of the seventh NPN tube Q7, and the emitter electrode of the fifth PNP tube Q5 is connected with the drain electrode of the fourth PMOS tube MP4 through a fourth resistor R4;

the eighth NMOS transistor MN8 is connected with the ninth NMOS transistor MN9 through the grid electrode and is connected with the drain electrode of the seventh NMOS transistor MN 7; the drain electrode of the eighth NMOS transistor MN8 is connected with the drain electrode of the sixth PMOS transistor MP6, and the source electrode of the eighth NMOS transistor MN8 is connected with the collector electrode of a seventh NPN transistor Q7; the source electrode of the ninth NMOS tube MN9 is connected with the collector electrode of the eighth NPN tube Q8;

the ninth PMOS tube MP9 is connected with the nth-stage voltage reduction signal VN at the grid electrode, the source electrode of the ninth PMOS tube MP9 is used as the first input end of the tail voltage stabilization output link (4) to be connected with the 1 st-stage voltage reduction signal V1, and the drain electrode of the ninth PMOS tube MP9 is used as the output end of the tail voltage stabilization output link (4) to output the supply voltage VOUT;

the fifth resistor R5 and the sixth resistor R6 are connected in series and bridged between the drain electrode of the ninth PMOS tube MP9 and the GND, and the common end of the fifth resistor R5 and the sixth resistor R6 is connected with the feedback voltage VFB;

the bias stage output link (5) is used for generating output reference voltage VBO and bias current IBO, and is provided with three input ends and two output ends, wherein the first input end is connected with starting voltage A, the second input end is connected with a 1 st-stage buck signal V1, and the third input end is connected with bias voltage VB2; the first output end is used as a second output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a reference voltage VBO, and the second output end is used as a third output end of the whole rapid start voltage stabilizing circuit with bias priority intervention and outputs a bias current IBO; the circuit comprises a twelfth resistor R12, a thirteenth resistor R13, a fourteenth PNP transistor Q14, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22 and a sixteenth NMOS transistor MN16, wherein the two resistors are two resistors; wherein:

the source electrodes of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected, the second input end of the bias stage output link (5) is connected with the 1 st-stage buck signal V1, and the grid electrodes of the fourteenth PMOS tube MP14 to the sixteenth PMOS tube MP16 are connected with the drain electrode of the sixteenth PMOS tube MP 16; the drain electrode of a fourteenth PMOS tube MP14 is connected with the source electrode of the twenty-first PMOS tube MP21, and the drain electrode of a fifteenth PMOS tube MP15 is connected with the source electrode of the twenty-second PMOS tube MP 22;

the grids of the twenty-first PMOS tube MP21 and the twenty-second PMOS tube MP22 are connected and are used as the first input end of the bias stage output link (5) to be connected with the starting voltage A, and the drain electrode of the twenty-first PMOS tube MP21 is used as the third output end of the bias stage output link (5) to output a bias current IBO; the drain of the twenty-second PMOS transistor MP22 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the emitter of the fourteenth PNP transistor Q14 through the thirteenth resistor R13; the common end of the twelfth resistor R12 and the thirteenth resistor R13 is used as the second output end of the bias stage output link (5) and outputs a reference voltage VBO; the base electrode and the collector of the fourteenth PNP tube Q14 are connected to GND;

the drain electrode of the sixteenth NMOS transistor MN16 is connected with the drain electrode of the sixteenth PMOS transistor MP16, the grid electrode of the sixteenth NMOS transistor MN16 is used as a bias level output link (5), the third input end of the grid electrode of the sixteenth NMOS transistor is connected with a bias voltage VB2, and the source electrode of the sixteenth NMOS transistor MN16 is connected to GND.