CN113406989A

CN113406989A - Low dropout linear regulator compensation circuit and low dropout linear regulator

Info

Publication number: CN113406989A
Application number: CN202110680509.5A
Authority: CN
Inventors: 李海茵
Original assignee: Dongguan Changgong Microelectronics Co Ltd
Current assignee: Dongguan Changgong Microelectronics Co Ltd
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2021-09-17

Abstract

The circuit comprises a first error amplifier, a first loop and a second loop, wherein the first error amplifier is used for adjusting the output voltage of the compensation circuit of the low dropout linear regulator according to the reference voltage and the output voltage of the compensation circuit of the low dropout linear regulator; the second loop circuit is used for sinking current, when the current is sunk, the second current generating circuit generates second current, and the second current acts on the second compensation circuit, so that the second compensation circuit can adjust second output impedance of the first error amplifier through the second current.

Description

Low dropout linear regulator compensation circuit and low dropout linear regulator

Technical Field

The application relates to the technical field of voltage regulators, in particular to a compensation circuit of a low dropout linear voltage regulator and the low dropout linear voltage regulator.

Background

A Low-Dropout Regulator (LDO) is a dc linear Regulator with input Voltage greater than output Voltage, which has the advantages of fast input/output response and Low noise, and can be applied to power supplies of memories such as DDR (Double Data Rate), DDR2(Double Data Rate 2, second generation Double Data Rate), etc., and memories such as DDR, DDR2, etc. need to be powered by a power supply with strong load capacity, high output accuracy, good transient performance, and capable of sinking/drawing large current. For an LDO capable of sinking/drawing a large current, stability compensation in a full load range is a difficult point of the industry, and a circuit capable of performing stability compensation on the LDO with the sinking/drawing the large current is not available at present.

Disclosure of Invention

The present application is directed to solving at least one of the problems in the prior art. Therefore, the present application provides a compensation circuit for a low dropout regulator, which can compensate the low dropout regulator when the low dropout regulator is sourcing or sinking current.

The application also provides a low dropout regulator comprising the compensation circuit of the low dropout regulator.

An embodiment of a first aspect of the present application provides a compensation circuit for a low dropout linear regulator, including:

the first input end of the first error amplifier is used for accessing a reference voltage, the second input end of the first error amplifier is connected with the output end of the low dropout regulator compensating circuit, and the first error amplifier is used for adjusting the output voltage of the low dropout regulator compensating circuit according to the reference voltage and the output voltage of the low dropout regulator compensating circuit;

a first loop for sourcing current; the first loop comprises a first current generation circuit and a first compensation circuit, wherein a first output end of the first error amplifier is connected with the first current generation circuit through the first compensation circuit, the first current generation circuit is used for generating a first current acting on the first compensation circuit, and the first compensation circuit is used for adjusting the first output impedance of the first error amplifier through the first current;

a second loop for sinking current; the second loop circuit includes a second current generation circuit and a second compensation circuit, the second output terminal of the first error amplifier is connected to the second current generation circuit through the second compensation circuit, the second current generation circuit is configured to generate a second current applied to the second compensation circuit, and the second compensation circuit is configured to adjust the second output impedance of the first error amplifier by the second current.

The compensation circuit of the low dropout linear regulator according to the embodiment of the first aspect of the present application has at least the following beneficial effects: the compensation circuit of the low dropout linear regulator comprises a first error amplifier, a first loop and a second loop, wherein the first error amplifier is used for adjusting the output voltage of the compensation circuit of the low dropout linear regulator according to the reference voltage and the output voltage of the compensation circuit of the low dropout linear regulator, the first loop is used for pulling current, when the current is pulled, a first current is generated by a first current generation circuit and acts on the first compensation circuit, so that the first compensation circuit can adjust the first output impedance of the first error amplifier through the first current to achieve the compensation effect, and the load regulation rate of the output voltage of the compensation circuit of the low dropout linear regulator is improved; the second loop circuit is used for sinking current, when the current is sunk, the second current generating circuit generates second current, and the second current acts on the second compensation circuit, so that the second compensation circuit can adjust second output impedance of the first error amplifier through the second current, compensation effect is achieved, and load regulation rate of output voltage of the low dropout linear regulator compensation circuit is improved.

According to some embodiments of the first aspect of the present application, the first error amplifier comprises a first operational amplifier, a first P-channel field effect transistor, a second P-channel field effect transistor, a third P-channel field effect transistor, and a fourth P-channel field effect transistor;

the non-inverting input end of the first operational amplifier is used as the first input end of the first error amplifier and is used for accessing a reference voltage, the inverting input end of the first operational amplifier is used as the second input end of the first error amplifier and is connected with the output end of the low dropout linear regulator compensating circuit, the first output end of the first operational amplifier is connected with the drain electrode of the first P-channel field effect transistor, and the second output end of the first operational amplifier is connected with the drain electrode of the third P-channel field effect transistor;

the grid electrode of the first P-channel field effect transistor is connected with the grid electrode of the second P-channel field effect transistor, and the grid electrode of the first P-channel field effect transistor is connected with the drain electrode of the first P-channel field effect transistor;

the grid electrode of the third P-channel field effect transistor is connected with the grid electrode of the fourth P-channel field effect transistor, the drain electrode of the third P-channel field effect transistor is connected with the grid electrode of the third P-channel field effect transistor, the drain electrode of the fourth P-channel field effect transistor serves as the second output end of the first error amplifier and is connected with the second compensation circuit, and the drain electrode of the second P-channel field effect transistor serves as the first output end of the first error amplifier and is connected with the first compensation circuit;

and the source electrode of the first P-channel field effect transistor, the source electrode of the second P-channel field effect transistor, the source electrode of the third P-channel field effect transistor and the source electrode of the fourth P-channel field effect transistor are all used for being connected with a first power supply.

According to some embodiments of the first aspect of the present application, the first compensation circuit comprises a first resistor, a first N-channel fet, a second N-channel fet, and a third N-channel fet;

the drain electrode of the first N-channel field effect transistor is respectively connected with the drain electrode of the second P-channel field effect transistor and one end of the first current generating circuit, and the drain electrode of the second N-channel field effect transistor is respectively connected with the drain electrode of the second P-channel field effect transistor and one end of the first current generating circuit through the first resistor; the source electrode of the first N-channel field effect transistor, the source electrode of the second N-channel field effect transistor and the source electrode of the third N-channel field effect transistor are connected with the output end of the low dropout linear voltage regulator compensation circuit, the grid electrode of the first N-channel field effect transistor is connected with the drain electrode of the first N-channel field effect transistor, the grid electrode of the second N-channel field effect transistor is connected with the grid electrode of the third N-channel field effect transistor, the grid electrode of the third N-channel field effect transistor is connected with the drain electrode of the third N-channel field effect transistor, and the drain electrode of the third N-channel field effect transistor is connected with the other end of the first current generation circuit.

According to some embodiments of the first aspect of the present application, the first current generating circuit comprises a second resistor, a third resistor, a fourth N-channel field effect transistor, a fifth N-channel field effect transistor, and a second operational amplifier;

the grid electrode of the fourth N-channel field effect transistor is connected with the drain electrode of the first N-channel field effect transistor, the grid electrode of the fourth N-channel field effect transistor is connected with the drain electrode of the second N-channel field effect transistor through the first resistor, the drain electrode of the fourth N-channel field effect transistor is used for being connected with a second power supply, and the source electrode of the fourth N-channel field effect transistor is connected with the output end of the low dropout linear regulator compensating circuit;

the grid electrode of the fifth N-channel field effect transistor is connected with the grid electrode of the fourth N-channel field effect transistor, the drain electrode of the fifth N-channel field effect transistor is connected with the inverting input end of the second operational amplifier, the drain electrode of the fifth N-channel field effect transistor is used for being connected into the second power supply through the second resistor, the non-inverting input end of the second operational amplifier is used for being connected into the second power supply through the third resistor, and the output end of the second operational amplifier is connected with the drain electrode of the third N-channel field effect transistor.

According to some embodiments of the first aspect of the present application, the second compensation circuit comprises a sixth N-channel FET, a seventh N-channel FET, an eighth N-channel FET, and a fourth resistor, the drain electrode of the sixth N-channel field effect transistor is connected with the second output end of the first error amplifier, the drain electrode of the seventh N-channel field effect transistor is respectively connected with the grid electrode of the sixth N-channel field effect transistor and one end of the second current generating circuit through the fourth resistor, the grid electrode of the sixth N-channel field effect transistor is connected with the drain electrode of the sixth N-channel field effect transistor, the grid electrode of the seventh N-channel field effect transistor is connected with the grid electrode of the eighth N-channel field effect transistor, the drain electrode of the eighth N-channel field effect transistor is respectively connected with the other end of the second current generation circuit and the grid electrode of the eighth N-channel field effect transistor; and the source electrode of the sixth N-channel field effect transistor, the source electrode of the seventh N-channel field effect transistor and the source electrode of the eighth N-channel field effect transistor are all grounded.

According to some embodiments of the first aspect of the present application, the second current generation circuit includes a ninth N-channel fet, a tenth N-channel fet, and a third operational amplifier, a drain of the ninth N-channel fet is connected to the output of the low dropout linear regulator compensation circuit, a source of the ninth N-channel fet is grounded, a gate of the ninth N-channel fet is connected to a gate of the tenth N-channel fet, a gate of the ninth N-channel fet is connected to a drain of the seventh N-channel fet through the fourth resistor, a source of the tenth N-channel fet is grounded, a drain of the tenth N-channel fet is connected to the inverting input of the third operational amplifier, and a non-inverting input of the third operational amplifier is connected to the output of the low dropout linear regulator compensation circuit, and the output end of the third operational amplifier is connected with the drain electrode of the eighth N-channel field effect transistor.

According to some embodiments of the first aspect of the present application, the second operational amplifier comprises a fourth operational amplifier, an eleventh N-channel field effect transistor, a twelfth N-channel field effect transistor, a thirteenth N-channel field effect transistor, a fourteenth N-channel field effect transistor, a fifth P-channel field effect transistor, a sixth P-channel field effect transistor, and a first current source;

the non-inverting input end of the fourth operational amplifier is used as the non-inverting input end of the second operational amplifier, the inverting input end of the fourth operational amplifier is used as the inverting input end of the second operational amplifier, the non-inverting input end of the fourth operational amplifier is further connected with the drain electrode of the eleventh N-channel field effect transistor, the output end of the fourth operational amplifier is connected with the gate electrode of the eleventh N-channel field effect transistor, and the gate electrode of the eleventh N-channel field effect transistor is connected with the gate electrode of the twelfth N-channel field effect transistor;

a grid electrode of the thirteenth N-channel field effect transistor is connected with a drain electrode of the thirteenth N-channel field effect transistor, a grid electrode of the thirteenth N-channel field effect transistor is connected with a grid electrode of the fourteenth N-channel field effect transistor, a drain electrode of the fourteenth N-channel field effect transistor is connected with a drain electrode of the fifth P-channel field effect transistor, a drain electrode of the fifth P-channel field effect transistor is connected with a grid electrode of the fifth P-channel field effect transistor, a grid electrode of the fifth P-channel field effect transistor is connected with a grid electrode of the sixth P-channel field effect transistor, and a drain electrode of the sixth P-channel field effect transistor serves as an output end of the second operational amplifier;

the output end of the first current source (A1) is respectively connected with the drain electrode of the twelfth N-channel field effect transistor (MN8) and the drain electrode of the thirteenth N-channel field effect transistor (MN 9); the output terminal of the first current source (a1) is further connected between the gate of the thirteenth N-channel fet (MN9) and the gate of the fourteenth N-channel fet (MN 10);

the input end of the first current source, the source electrode of the fifth P-channel field effect transistor and the source electrode of the sixth P-channel field effect transistor are all used for being connected to the first power supply;

and the source electrode of the eleventh N-channel field effect transistor, the source electrode of the twelfth N-channel field effect transistor, the source electrode of the thirteenth N-channel field effect transistor and the source electrode of the fourteenth N-channel field effect transistor are all grounded.

According to some embodiments of the first aspect of the present application, the third operational amplifier comprises a fifth operational amplifier, a seventh P-channel field effect transistor, an eighth P-channel field effect transistor, a ninth P-channel field effect transistor, a tenth P-channel field effect transistor, a fifteenth N-channel field effect transistor, a sixteenth N-channel field effect transistor, a seventeenth N-channel field effect transistor, an eighteenth N-channel field effect transistor, a nineteenth N-channel field effect transistor, a second current source;

a non-inverting input terminal of the fifth operational amplifier is used as a non-inverting input terminal of the third operational amplifier, a non-inverting input terminal of the fifth operational amplifier is connected with a source electrode of the fifteenth N-channel field effect transistor, an output terminal of the fifth operational amplifier is connected with a gate electrode of the fifteenth N-channel field effect transistor, and a drain electrode of the fifteenth N-channel field effect transistor is connected with a drain electrode of the seventh P-channel field effect transistor, a gate electrode of the seventh P-channel field effect transistor, and a gate electrode of the eighth P-channel field effect transistor;

the drain electrode of the seventeenth N-channel field effect transistor is connected with the output end of the second current source;

the source electrode of the seventh P-channel field effect transistor, the source electrode of the eighth P-channel field effect transistor, the source electrode of the ninth P-channel field effect transistor, the source electrode of the tenth P-channel field effect transistor and the input end of the second current source are all connected to the first power supply;

a grid electrode of the sixteenth N-channel field effect transistor is connected with a drain electrode of the sixteenth N-channel field effect transistor, a drain electrode of the eighth P-channel field effect transistor and a grid electrode of the seventeenth N-channel field effect transistor, a drain electrode of the seventeenth N-channel field effect transistor is connected with a drain electrode of the eighteenth N-channel field effect transistor, a grid electrode of the eighteenth N-channel field effect transistor and a grid electrode of the nineteenth N-channel field effect transistor, a drain electrode of the nineteenth N-channel field effect transistor is connected with a drain electrode of the ninth P-channel field effect transistor, a grid electrode of the ninth P-channel field effect transistor and a grid electrode of the tenth P-channel field effect transistor, and a drain electrode of the tenth P-channel field effect transistor serves as an output end of the third operational amplifier;

and the source electrode of the sixteenth N-channel field effect transistor, the source electrode of the seventeenth N-channel field effect transistor, the source electrode of the eighteenth N-channel field effect transistor and the source electrode of the nineteenth N-channel field effect transistor are all grounded.

According to some embodiments of the first aspect of the present application, the load circuit further includes a load circuit, the load circuit includes a load capacitor and a load resistor, the load capacitor and the load resistor are connected in parallel, one end of the load resistor is connected to the output end of the compensation circuit of the low dropout linear regulator, and the other end of the load resistor is grounded.

In a second aspect of the present application, there is provided a low dropout regulator including the compensation circuit of the low dropout regulator according to any embodiment of the first aspect of the present application.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

Additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic diagram of a compensating circuit of a low dropout regulator in the related art;

FIG. 2 is a schematic diagram of a compensation circuit of a low dropout linear regulator according to some embodiments of the first aspect of the present application;

FIG. 3 is a schematic diagram of an internal circuit of the second operational amplifier of FIG. 2;

fig. 4 is a schematic diagram of an internal circuit of the third operational amplifier in fig. 2.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, if there are first and second described only for the purpose of distinguishing technical features, it is not understood that relative importance is indicated or implied or that the number of indicated technical features or the precedence of the indicated technical features is implicitly indicated or implied.

In the description of the present application, unless otherwise expressly limited, terms such as set, mounted, connected and the like should be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the terms in the present application by combining the detailed contents of the technical solutions.

In the related art, referring to fig. 1, fig. 1 is a schematic structural diagram of a compensation circuit of a low dropout regulator in the related art. The compensation circuit of the low dropout linear regulator in the related art comprises a second error amplifier, wherein the second error amplifier comprises an operational amplifier AMP4, a P-channel field effect transistor M4, a P-channel field effect transistor M5, a P-channel field effect transistor M6 and a P-channel field effect transistor M7; the compensating circuit of the low dropout linear regulator in the related art further comprises an N-channel field effect transistor M3, an N-channel field effect transistor M2, an N-channel field effect transistor M1 and an N-channel field effect transistor M0; the compensating circuit of the low dropout regulator in the related art further comprises a capacitor C1 and a resistor R3. The first output end of the operational amplifier AMP4 is connected with the drain electrode of the P-channel field effect transistor M4, the second output end of the operational amplifier AMP4 is connected with the drain electrode of the P-channel field effect transistor M6, the non-inverting input end of the operational amplifier AMP4 is connected with the reference voltage VREF, the inverting input end of the operational amplifier AMP4 is connected with the output end V0 of the low dropout regulator compensation circuit, the source electrode of the P-channel field effect transistor M4, the source electrode of the P-channel field effect transistor M5, the source electrode of the P-channel field effect transistor M6 and the source electrode of the P-channel field effect transistor M7 are all connected with a first power supply VCC, the gate electrode of the P-channel field effect transistor M4 is connected with the drain electrode of the P-channel field effect transistor M4 and the gate electrode of the P-channel field effect transistor M5, the drain electrode of the P-channel field effect transistor M6 is connected with the gate electrode of the P-channel field effect transistor M6 and the gate electrode of the P-channel field effect transistor M7, the drain electrode of the P-channel field effect transistor M7 is connected with the drain electrode of the N-channel field effect transistor M1, The grid electrode of the N-channel field effect transistor M1 and the grid electrode of the N-channel field effect transistor M0 are connected; the source electrode of the N-channel field effect transistor M1, the source electrode of the N-channel field effect transistor M0 and the source electrode of the N-channel field effect transistor M2 are all connected with a low dropout linear regulator compensating circuit V0 in the related art, the drain electrode of the N-channel field effect transistor M0 is connected with a second power supply VLDOIN, the grid electrode of the N-channel field effect transistor M3 is connected with the drain electrode of the N-channel field effect transistor M3, the drain electrode of the P-channel field effect transistor M5 and the grid electrode of the N-channel field effect transistor M2, the source electrode of the N-channel field effect transistor M3 and the source electrode of the N-channel field effect transistor M2 are all grounded, one end of a resistor R3 is connected with the low dropout linear regulator compensating circuit V0 in the related art, the other end of the resistor R3 is grounded, and a capacitor C1 is connected with the resistor R3 in parallel.

In the compensation circuit of the related art low dropout regulator, when a source current is applied, if the size of the N-channel fet M1 is small, for example, the size ratio of the N-channel fet M1 to the N-channel fet M0 is 1: 2400, when the output of the compensation circuit of the low dropout regulator is idle or lightly loaded, the current flowing through the N-channel fet M0 is close to 0, and at this time the output impedance of the second error amplifier approaches infinity, so that the position of the secondary pole of the second error amplifier is close to the primary pole, and at this time the phase margin of the compensation circuit of the low dropout regulator is negative, in order to adjust the phase margin of the compensation circuit of the low dropout regulator, it is necessary to use the N-channel fet M1 with a larger size, for example, the size ratio of the N-channel fet M1 to the N-channel fet M0 is 1: and 24, reducing the output impedance of the second error amplifier, so that the position of the secondary pole of the second error amplifier is far away from the position of the primary pole, thereby increasing the phase margin of the compensation circuit of the low dropout linear regulator, but when an N-channel field effect transistor M1 with a larger size is used, when the compensation circuit of the low dropout linear regulator is under heavy load, the gain of the circuit is reduced to a negative value, the output voltage is also reduced to a negative value, and the load regulation rate of the output voltage is higher at the moment.

When the current is pumped, if the size of the N-channel fet M3 is small, for example, the size ratio of the N-channel fet M3 to the N-channel fet M2 is 1:6000, when the compensation circuit of the related art is idle or lightly loaded, the current flowing through the N-channel fet M3 is close to 0, and the output impedance of the second error amplifier approaches infinity, so that the position of the secondary pole of the second error amplifier is close to the position of the primary pole, and the phase margin of the compensation circuit of the low dropout regulator is negative, in order to adjust the phase margin of the compensation circuit of the low dropout regulator, the N-channel fet M3 with a large size is required, for example, the size ratio of the N-channel fet M3 to the N-channel fet M2 is 1:60, so as to reduce the output impedance of the second error amplifier, thereby making the position of the secondary pole of the second error amplifier far away from the position of the primary pole, thereby increasing the phase margin of the compensation circuit of the low dropout regulator, but when using the N-channel field effect transistor M3 with a larger size, when the compensation circuit of the low dropout regulator is under heavy load, the gain of the circuit will be reduced to a negative value, the output voltage will also be reduced to a negative value, and at this moment, the load regulation rate of the output voltage is higher.

In order to solve the above-mentioned problems in the compensation circuit of the low dropout linear regulator in the related art, an embodiment of a first aspect of the present application provides a compensation circuit of a low dropout linear regulator.

Referring to fig. 2, the compensation circuit of the low dropout regulator according to the first embodiment of the present application includes a first error amplifier 100, a first input terminal of the first error amplifier 100 is configured to receive a reference voltage, a second input terminal of the first error amplifier 100 is connected to an output terminal V0 of the compensation circuit of the low dropout regulator, and the first error amplifier is configured to adjust an output voltage of the compensation circuit of the low dropout regulator according to the reference voltage and the output voltage of the compensation circuit of the low dropout regulator;

a first loop for sourcing current; the first loop circuit comprises a first current generating circuit 300 and a first compensating circuit 200, a first output end of the first error amplifier 100 is connected with the first current generating circuit 300 through the first compensating circuit 200, the first current generating circuit 300 is used for generating a first current applied to the first compensating circuit 200, and the first compensating circuit 200 is used for adjusting a first output impedance of the first error amplifier 100 through the first current;

the second loop is used for filling current; the second loop circuit includes a second current generating circuit 500 and a second compensating circuit 400, a second output terminal of the first error amplifier 100 is connected to the second current generating circuit 500 through the second compensating circuit 400, the second current generating circuit 500 is configured to generate a second current applied to the second compensating circuit 400, and the second compensating circuit 400 is configured to adjust a second output impedance of the first error amplifier 100 through the second current.

The compensation circuit of the low dropout regulator according to the embodiment of the first aspect of the present application, which can be applied to a low dropout regulator having a current sourcing or sinking capability, includes a first error amplifier 100, a first loop and a second loop, wherein the first error amplifier 100 is configured to adjust an output voltage of the compensation circuit of the low dropout regulator according to a reference voltage and the output voltage of the compensation circuit of the low dropout regulator, the first loop is configured to source a current, when the current sourcing is performed, a first current is generated by a first current generation circuit 300, and the first current acts on a first compensation circuit 200, so that the first compensation circuit 200 can adjust a first output impedance of the first error amplifier 100 through the first current to achieve a compensation effect and improve a load regulation rate of the output voltage; the second loop circuit is used for sinking current, and when the current is sunk, the second current generating circuit 500 generates a second current, and the second current acts on the second compensation circuit 400, so that the second compensation circuit 400 can adjust the second output impedance of the first error amplifier 100 through the second current to achieve a compensation effect and improve the load adjustment rate of the output voltage.

It is understood that the first error amplifier 100 includes a first operational amplifier AMP1, a first P-channel fet MP1, a second P-channel fet MP2, a third P-channel fet MP3, and a fourth P-channel fet MP 4; the non-inverting input end of the first operational amplifier AMP1 is used as the first input end of the first error amplifier 100 and is used for accessing a reference voltage, the inverting input end of the first operational amplifier AMP1 is used as the second input end of the first error amplifier 100 and is connected with the output end V0 of the low dropout linear regulator compensation circuit, the first output end of the first operational amplifier AMP1 is connected with the drain electrode of the first P-channel field effect transistor MP1, and the second output end of the first operational amplifier AMP1 is connected with the drain electrode of the third P-channel field effect transistor MP 3; the grid electrode of the first P-channel field effect transistor MP1 is connected with the grid electrode of the second P-channel field effect transistor MP2, and the grid electrode of the first P-channel field effect transistor MP1 is connected with the drain electrode of the first P-channel field effect transistor MP 1; the grid electrode of the third P-channel field effect transistor MP3 is connected with the grid electrode of the fourth P-channel field effect transistor MP4, the drain electrode of the third P-channel field effect transistor MP3 is connected with the grid electrode of the third P-channel field effect transistor MP3, the drain electrode of the fourth P-channel field effect transistor MP4 serves as the second output end of the first error amplifier 100 and is connected with the second compensation circuit, and the drain electrode of the second P-channel field effect transistor MP2 serves as the first output end of the first error amplifier 100 and is connected with the first compensation circuit; the source electrode of the first P-channel fet MP1, the source electrode of the second P-channel fet MP2, the source electrode of the third P-channel fet MP3, and the source electrode of the fourth P-channel fet MP4 are all used for connecting to the first power source VCC.

It is understood that the first compensation circuit 200 includes a first resistor R1, a first N-channel fet MN1, a second N-channel fet MN2, and a third N-channel fet MN 3; the drain electrode of the first N-channel field effect transistor MN1 is respectively connected with the drain electrode of the second P-channel field effect transistor MP2 and one end of the first current generating circuit, and the drain electrode of the second N-channel field effect transistor MN2 is respectively connected with the drain electrode of the second P-channel field effect transistor MP2 and one end of the first current generating circuit through a first resistor R1; the source electrode of the first N-channel field effect transistor MN1, the source electrode of the second N-channel field effect transistor MN2 and the source electrode of the third N-channel field effect transistor MN3 are all connected with the output end V0 of the low dropout linear regulator compensation circuit, the grid electrode of the first N-channel field effect transistor MN1 is connected with the drain electrode of the first N-channel field effect transistor MN1, the grid electrode of the second N-channel field effect transistor MN2 is connected with the grid electrode of the third N-channel field effect transistor MN3, the grid electrode of the third N-channel field effect transistor MN3 is connected with the drain electrode of the third N-channel field effect transistor MN3, and the drain electrode of the third N-channel field effect transistor MN3 is connected with the other end of the first current generation circuit.

It is understood that the first current generating circuit 300 includes a second resistor Rs1, a third resistor Rs2, a fourth N-channel fet HS, a fifth N-channel fet HS _ Sns, and a second operational amplifier HS _ CS;

the grid electrode of the fourth N-channel field effect transistor HS is connected with the drain electrode of the first N-channel field effect transistor MN1, the grid electrode of the fourth N-channel field effect transistor HS is connected with the drain electrode of the second N-channel field effect transistor MN2 through a first resistor R1, the drain electrode of the fourth N-channel field effect transistor HS is used for being connected with a second power supply VLDOIN, and the source electrode of the fourth N-channel field effect transistor HS is connected with the output end V0 of the low-dropout linear regulator compensating circuit;

the grid electrode of the fifth N-channel field effect tube HS _ Sns is connected with the grid electrode of the fourth N-channel field effect tube HS, the drain electrode of the fifth N-channel field effect tube HS _ Sns is connected with the inverting input end of the second operational amplifier HS _ CS, the drain electrode of the fifth N-channel field effect tube HS _ Sns is used for being connected with a second power supply VLDOIN through a second resistor Rs1, the non-inverting input end of the second operational amplifier HS _ CS is used for being connected with the second power supply VLDOIN through a third resistor Rs2, and the output end of the second operational amplifier HS _ CS is connected with the drain electrode of the third N-channel field effect tube MN 3.

It can be understood that the second compensation circuit 400 includes a sixth N-channel fet MN4, a seventh N-channel fet MN5, an eighth N-channel fet MN6 and a fourth resistor R2, a drain of the sixth N-channel fet MN4 is connected to the second output terminal of the first error amplifier, a drain of the seventh N-channel fet MN5 is connected to a gate of the sixth N-channel fet MN4 and one end of the second current generation circuit through a fourth resistor R2, a gate of the sixth N-channel fet MN4 is connected to a drain of the sixth N-channel fet MN4, a gate of the seventh N-channel fet MN5 is connected to a gate of the eighth N-channel fet MN6, and a drain of the eighth N-channel fet 6 is connected to the other end of the second current generation circuit and the gate of the eighth N-channel fet MN 6; the source electrode of the sixth N-channel field effect transistor MN4, the source electrode of the seventh N-channel field effect transistor MN5, and the source electrode of the eighth N-channel field effect transistor MN6 are all grounded.

It is understood that the second current generating circuit 500 includes a ninth N-channel fet LS, a tenth N-channel fet LS _ Sns, and a third operational amplifier LS _ CS, a drain of the ninth N-channel fet LS is connected to the output terminal V0 of the low dropout linear regulator compensating circuit, a source of the ninth N-channel fet LS is grounded, a gate of the ninth N-channel fet LS is connected to a gate of the tenth N-channel fet LS _ Sns, a gate of the ninth N-channel fet LS is connected to a drain of the seventh N-channel fet MN5 through a fourth resistor R2, a source of the tenth N-channel fet LS _ Sns is grounded, a drain of the tenth N-channel fet LS _ Sns is connected to an inverting input terminal of the third operational amplifier LS _ CS, a non-inverting input terminal of the third operational amplifier LS _ CS is connected to the output terminal V0 of the low dropout linear regulator compensating circuit, the output terminal of the third operational amplifier LS _ CS is connected to the drain of the eighth N-channel fet MN 6.

It is understood that, referring to fig. 3, the second operational amplifier HS _ CS includes a fourth operational amplifier AMP2, an eleventh N-channel fet MN7, a twelfth N-channel fet MN8, a thirteenth N-channel fet MN9, a fourteenth N-channel fet MN10, a fifth P-channel fet MP5, a sixth P-channel fet MP6, and a first current source a 1;

the non-inverting input end of the fourth operational amplifier AMP2 is used as the non-inverting input end of the second operational amplifier HS _ CS, the inverting input end of the fourth operational amplifier AMP2 is used as the inverting input end of the second operational amplifier HS _ CS, the non-inverting input end of the fourth operational amplifier AMP2 is further connected with the drain electrode of the eleventh N-channel field effect transistor MN7, the output end of the fourth operational amplifier AMP2 is connected with the gate electrode of the eleventh N-channel field effect transistor MN7, and the gate electrode of the eleventh N-channel field effect transistor MN7 is connected with the gate electrode of the twelfth N-channel field effect transistor MN 8; the grid electrode of the thirteenth N-channel field effect tube MN9 is connected with the drain electrode of the thirteenth N-channel field effect tube MN9, the grid electrode of the thirteenth N-channel field effect tube MN9 is connected with the grid electrode of the fourteenth N-channel field effect tube MN10, the drain electrode of the fourteenth N-channel field effect tube MN10 is connected with the drain electrode of the fifth P-channel field effect tube MP5, the drain electrode of the fifth P-channel field effect tube MP5 is connected with the grid electrode of the fifth P-channel field effect tube MP5, the grid electrode of the fifth P-channel field effect tube MP5 is connected with the grid electrode of the sixth P-channel field effect tube MP6, and the drain electrode of the sixth P-channel field effect tube MP6 is used as the output end of the second operational amplifier HS _ CS;

the output end of the first current source A1 is respectively connected with the drain electrode of a twelfth N-channel field effect transistor MN8 and the drain electrode of a thirteenth N-channel field effect transistor MN 9; the output end of the first current source A1 is also connected between the grid electrode of the thirteenth N-channel field effect transistor MN9 and the grid electrode of the fourteenth N-channel field effect transistor MN 10;

the input end of the first current source A1, the source electrode of the fifth P-channel field effect transistor MP5 and the source electrode of the sixth P-channel field effect transistor MP6 are all used for being connected with a first power supply VCC; the source electrode of the eleventh N-channel field effect transistor MN7, the source electrode of the twelfth N-channel field effect transistor MN8, the source electrode of the thirteenth N-channel field effect transistor MN9 and the source electrode of the fourteenth N-channel field effect transistor MN10 are all grounded.

It is understood that, referring to fig. 4, the third operational amplifier LS _ CS includes a fifth operational amplifier AMP3, a seventh P-channel fet MP7, an eighth P-channel fet MP8, a ninth P-channel fet MP9, a tenth P-channel fet MP10, a fifteenth N-channel fet MN11, a sixteenth N-channel fet MN12, a seventeenth N-channel fet MN13, an eighteenth N-channel fet MN14, a nineteenth N-channel fet MN15, a second current source a 2;

a non-inverting input terminal of the fifth operational amplifier AMP3 is used as an inverting input terminal of the third operational amplifier LS _ CS, a non-inverting input terminal of the fifth operational amplifier AMP3 is used as a non-inverting input terminal of the third operational amplifier LS _ CS, a non-inverting input terminal of the fifth operational amplifier AMP3 is connected to a source of the fifteenth N-channel fet MN11, an output terminal of the fifth operational amplifier AMP3 is connected to a gate of the fifteenth N-channel fet MN11, a drain of the fifteenth N-channel fet MN11 is connected to a drain of the seventh P-channel fet MP7, a gate of the seventh P-channel fet MP7, and a gate of the eighth P-channel fet MP 8;

the drain electrode of the seventeenth N-channel field effect transistor MN13 is connected with the output end of the second current source A2; the source electrode of the seventh P-channel field effect transistor MP7, the source electrode of the eighth P-channel field effect transistor MP8, the source electrode of the ninth P-channel field effect transistor MP9, the source electrode of the tenth P-channel field effect transistor MP10, and the input end of the second current source a2 are all connected to the first power source VCC;

the gate of the sixteenth N-channel fet MN12 is connected to the drain of the sixteenth N-channel fet MN12, the drain of the eighth P-channel fet MP8, and the gate of the seventeenth N-channel fet MN13, the drain of the seventeenth N-channel fet MN13 is connected to the drain of the eighteenth N-channel fet MN14, the gate of the eighteenth N-channel fet MN14, and the gate of the nineteenth N-channel fet MN15, the drain of the nineteenth N-channel fet MN15 is connected to the drain of the ninth P-channel fet MP9, the gate of the ninth P-channel fet MP9, and the gate of the tenth P-channel fet MP10, and the drain of the tenth P-channel fet MP10 is used as the output terminal of the third operational amplifier LS _ CS; the source electrode of the sixteenth N-channel field effect transistor MN12, the source electrode of the seventeenth N-channel field effect transistor MN13, the source electrode of the eighteenth N-channel field effect transistor MN14 and the source electrode of the nineteenth N-channel field effect transistor MN15 are all grounded.

It can be understood that the compensation circuit of the low dropout regulator of the embodiment of the present application further includes a load circuit 600, the load circuit 600 includes a load capacitor CL and a load resistor RL, the load capacitor CL and the load resistor RL are connected in parallel, one end of the load resistor RL is connected to the output terminal V0 of the compensation circuit of the low dropout regulator, and the other end of the load resistor RL is grounded.

The operation principle of the compensation circuit of the low dropout linear regulator according to the embodiment of the present application is described in detail with a specific embodiment with reference to fig. 2 to 4. It is to be understood that the following description is illustrative only and is not intended to be in any way limiting.

For example, when the low dropout regulator compensation circuit according to the embodiment of the present application is sourcing current, the first power source VCC is 3.3V, the second power source VLDOIN is 1.8V, the reference voltage VREF is 0.9V, the load capacitance CL is 30uF, and the first load current ILOAD1 of the low dropout regulator compensation circuit ranges from 0 to 3A, and it can be understood by those skilled in the art that the first load current of the low dropout regulator compensation circuit is no load when 0, the first load current of the low dropout regulator compensation circuit is light load when more than 0 and less than 100mA, the first load current is medium load when more than or equal to 100mA and less than 1A, and the first load current is heavy load when more than or equal to 1A and less than 3A. The second N-channel fet MN2 and the third N-channel fet MN3 are in a size ratio of N2: 1, current mirror. The size ratio of the fifth N-channel field effect tube HS _ Sns to the fourth N-channel field effect tube HS is 1: n1, since the first load current ILOAD1 flows through the fourth N-channel fet HS, the first load current ILOAD1 flowing through the fourth N-channel fet HS can be equally proportionally sampled by the fourth operational amplifier AMP2, the second resistor Rs1 and the third resistor Rs2, and the first sampling current Isns1 ═ ILOAD/N1 is obtained, that is, the current flowing through the eleventh N-channel fet MN7 is Isns1, and the size ratio of the eleventh N-channel fet MN7 to the twelfth N-channel fet MN8 is N3: 1, so that the current flowing through the twelfth N-channel fet MN8 is Isns2 ═ Isns1/N3 ═ ILOAD/(N1 × N3); the first current source a1 outputs a first bias current IBIAS1, and a current difference between the current IBIAS1 and the first sampling current Isns1 is sampled by a thirteenth N-channel fet MN9, and the thirteenth N-channel fet MN9 and a fourteenth N-channel fet MN10 have a size ratio of 1:1, the size ratio of the fifth P-channel fet MP5 to the sixth P-channel fet MP6 is 1:1, such that the first current Icomp 1-IBIAS 1-Isns 2-IBIAS 1- [ ILOAD/(N1 × N3) ], the first current Icomp1 is gradually decreased as the first load current ILOAD1 is increased. When the first bias current IBIAS1 output by the first current source a1 is made to be 2 μ a, and N1 × N3 is made to be 500000, when the compensation circuit of the low dropout linear regulator is in a heavy load state, that is, the first load current ILOAD1 is greater than or equal to 1A, the first current Icomp1 is reduced to 0, at this time, the current mirror formed by the thirteenth N-channel fet MN9 and the fourteenth N-channel fet MN10, and the current mirror formed by the fifth P-channel fet MP5 and the sixth P-channel fet 6 are turned off, and the current mirror formed by the second N-channel fet MN2 and the third N-channel fet MN3 are turned off, so that the gain of the turn-off loop is low, and when the current mirror is turned off, the output voltage does not suddenly change, thereby improving the linearity of the output voltage.

The equivalent resistance of the first N-channel field effect transistor MN1 is Rn1, the transconductance of the first N-channel field effect transistor MN1 is gmn1, and gmn1 and Rn1 are reciprocal; the equivalent resistance of the second N-channel field effect transistor MN2 is Rn2, the drain-source conductance of the second N-channel field effect transistor MN2 is gdsn2, and the gdsn2 and the Rn2 are reciprocal; the equivalent resistance of the second P-channel fet MP2 is Rp2, the drain-source conductance of the second P-channel fet MP2 is gdsp2, and gdsp2 and Rp2 are reciprocal. The first output impedance REA1 of the first error amplifier 100 is [ Rn1// (Rn2+ R1) ]// Rp2, and since the drain of the second N-channel fet MN2 is connected to the first resistor R1, the drain-to-source conductance gdsn2 of the second N-channel fet MN2 is increased, and the equivalent resistance Rn2 of the second N-channel fet MN2 is decreased. Due to the existence of the first resistor R1, the equivalent resistance Rn2 of the second N-channel fet MN2 increases as the current flowing through the second N-channel fet MN2 decreases, that is, the equivalent resistance Rn2 of the second N-channel fet MN2 increases as the first current Icomp1 decreases. When the compensation circuit of the low dropout linear regulator is in an idle state, i.e. the first load current ILOAD1 is 0, the first current Icomp1 is maximum, and the equivalent resistance Rn2 of the second N-channel fet MN2 is minimum.

The transfer function indicates that the dominant pole of the first error amplifier 100 is P0 ═ 1/[2 × pi × (Ro// RL) × CL ], the subordinate pole is P1 ═ 1/[2 × pi × REA1 × CEA1], where CEA1 is the first output capacitance of the first error amplifier 100, and Ro at this time is the output resistance when the low dropout linear regulator compensation circuit is sourcing current. It can be understood that to achieve stability compensation of the compensation circuit of the low dropout linear regulator, the minor pole is required to be far away from the major pole, and the minor pole is determined by the first output impedance of the first error amplifier 100 and the first output capacitance of the first error amplifier 100, and the embodiment of the present application adjusts the first output impedance of the first error amplifier 100 to change the position of the minor pole P1.

Since the drain-source conductance gdsp2 of the second P-channel fet MP2 is small, that is, the equivalent resistance Rp2 of the second P-channel fet MP2 is large and negligible, the first output impedance REA1 of the first error amplifier 100 may be approximated as REA1 ≈ Rn1// (Rn2+ R1).

When the compensation circuit of the low dropout linear regulator is in a light load state, the first load current ILOAD1 is greater than 0 and less than 100mA, the current flowing through the first N-channel fet MN1 is close to 0 and can be ignored, and the current flowing through the second N-channel fet MN2 is N2 × Icomp1, since the current flowing through the first N-channel fet MN1 is close to 0, the transconductance gmn1 of the first N-channel fet MN1 approaches 0, that is, the equivalent resistance Rn1 of the first N-channel fet MN1 approaches infinity, the first output impedance REA1 of the first error amplifier 100 can approach REA1 ≈ Rn2+ R1, at this time, the first output impedance REA1 of the first error amplifier 100 is small, the position of the minor pole of the first error amplifier 100 is far away from the position of the major pole, and as the first load current ILOAD1 increases from 0 to approach 100mA, the position of the minor pole gradually increases as the main pole approaches 1, the load current gradually increases, but the phase margin of the compensating circuit of the low-dropout linear regulator in the process meets the stability requirement.

When the compensation circuit of the low dropout linear regulator is in a medium load state, the first load current ILOAD1 is equal to or greater than 100mA and less than 1A, the current flowing through the first N-channel fet MN1 gradually increases with the increase of the first load current ILOAD1, and the current flowing through the second N-channel fet MN2 gradually decreases due to the gradual decrease of the first current Icomp1, at this time, the first output impedance REA1 of the first error amplifier 100 may be approximately REA1 ≈ Rn1// (Rn2+ R1), the position of the secondary pole of the first error amplifier 100 may be changed by changing the resistance value of the first resistor R1, and at the same time, a zero point is introduced into the presence of the first resistor R1, and the zero point is close to the secondary pole position, so that the phase margin of the compensation circuit of the low dropout linear regulator meets the requirement.

When the compensation circuit of the low dropout linear regulator is in a heavy load state, the first load current ILOAD1 is equal to or greater than 1A and less than 3A, at this time, the first current Icomp1 is reduced to 0, and since the equivalent resistance Rn2 of the second N-channel fet MN2 is increased along with the reduction of the first current Icomp1, the equivalent resistance Rn2 of the second N-channel fet MN2 is larger at this time and can be ignored, and the first output impedance REA1 of the first error amplifier 100 can be approximately REA1 ≈ Rn 1. If the first N-channel fet MN1 with a large size is used, the drain-source voltage Vgs1 of the first N-channel fet MN1 is small, and when the first load current ILOAD1 is large, the current flowing through the first N-channel fet MN1 is also large, that is, the first output impedance REA1 is reduced, at this time, the gain of the first loop is also reduced, so that the output voltage is reduced a lot during a heavy load, that is, the load regulation rate of the low dropout regulator compensation circuit is poor, therefore, the present application can use the first N-channel fet MN1 with a small size to ensure that the first output impedance REA1 is at a relatively large value during a heavy load, thereby avoiding reducing the gain of the first loop, so that excessive reduction of the output voltage can be avoided during a heavy load, and ensuring the load regulation rate of the low dropout regulator. It should be noted that, a person skilled in the art may select the size of the first N-channel fet MN1 according to actual needs, so that the phase margin of the first loop during heavy load may meet the requirement.

It can be understood that, in the compensation circuit of the low dropout regulator according to the embodiment of the present application, the first error amplifier 100 has different first output impedances when the compensation circuit is under light load, medium load, and heavy load, so as to change the secondary pole of the first error amplifier 100, so that the phase margin of the compensation circuit of the low dropout regulator meets the requirement. When the load is light, the first error amplifier 100 is lowered by the action of the first current Icomp1 to have different first output impedance, when the load is medium, the first current Icomp1 is gradually decreased with the increase of the first load current ILOAD1, so that the action of the first current Icomp1 on lowering the first output impedance is gradually decreased, and when the load is heavy, the first load current ILOAD1 is greater than or equal to 1A, and the second current Icomp2 is 0, thereby avoiding the gain of the low dropout regulator compensating circuit from being lowered due to the too low first output impedance, and improving the load regulation rate of the output voltage of the low dropout regulator compensating circuit.

The values of N1, N2, N3 and IBIAS1 may be set by those skilled in the art according to actual needs, and the present application is not limited thereto.

When the compensation circuit of the low dropout regulator according to the embodiment of the present application is performing current sinking, the first power source VCC is 3.3V, the second power source VLDOIN is 1.2V, the reference voltage VREF is 0.6V, the load capacitance CL is 30uF, and the second load current ILOAD2 is 0 to 3A. It can be understood by those skilled in the art that the compensation circuit of the low dropout regulator is no-load when the first load current is 0, light-load when the second load current is greater than 0 and less than 100mA, medium-load when the second load current is greater than or equal to 100mA and less than 1A, and heavy-load when the second load current is greater than or equal to 1A and less than 3A.

The size ratio of the ninth N-channel field effect transistor LS to the tenth N-channel field effect transistor LS _ Sns is N4: 1, since the second load current ILOAD2 flows through the ninth N-channel fet LS, the second load current ILOAD2 flowing through the ninth N-channel fet LS may be sampled in equal proportion by the fifth operational amplifier AMP3, the fifteenth N-channel fet MN11, the seventh P-channel fet MP7, and the eighth P-channel fet MP8, and the size ratio of the seventh P-channel fet MP7 to the eighth P-channel fet MP8 is N6: 1, the second sampling current Isns3 ═ Ipower/N4, that is, the current flowing through the fifteenth N-channel fet MN11 and the seventh P-channel fet MP7 is Isns3, and the eighth P-channel fet MP8 is Isns4 ═ Isns3/N6 ═ ILOAD2/(N4 × N6). The second current source a2 outputs a second bias current IBIAS2, the current difference between the second bias current IBIAS2 and the Isns4 is sampled by the eighteenth N-channel fet MN14, the sixteenth N-channel fet MN12 and the seventeenth N-channel fet MN13 are current mirrors with a size ratio of 1:1, the eighteenth N-channel fet MN14 and the nineteenth N-channel fet MN15 are current mirrors with a size ratio of 1:1, and the ninth P-channel fet MP9 and the tenth P-channel fet MP10 are current mirrors with a size ratio of 1:1, so that the second current generated by the second current generating circuit 500 is:

icomp 2-IBIAS 2-Isns 4-IBIAS 2- [ ILOAD2/(N4 × N6) ], then the second current Icomp2 decreases gradually as the second load current ILOAD2 increases. When the second bias current IBIAS2 output by the second current source a2 is made to be 2 μ a and N4 × N6 is made to be 500000, when the compensation circuit of the low dropout regulator is in a heavy load state, that is, the second load current ILOAD2 is greater than or equal to 1A, and the second current Icomp2 is reduced to 0, at this time, the current mirror formed by the eighteenth N-channel fet MN14 and the nineteenth N-channel fet MN15, the current mirror formed by the ninth P-channel fet MP9 and the tenth P-channel fet MP10, and the current mirrors formed by the seventh N-channel fet MN5 and the eighth N-channel fet MN6 are all turned off, and the multi-stage current mirror turning-off mode is adopted, so that the gain of the turn-off loop is low, and the output voltage does not suddenly change when the current mirrors are turned off, thereby improving the linearity of the output voltage.

The equivalent resistance of the sixth N-channel field effect transistor MN4 is Rn4, the step-over of the sixth N-channel field effect transistor MN4 is gmn4, and Rn4 and gmn4 are reciprocal; the equivalent resistance of the seventh N-channel field effect transistor MN5 is Rn5, the drain-source conductance of the seventh N-channel field effect transistor MN5 is gdsn5, and Rn5 and gdsn5 are reciprocal; the equivalent resistance of the fourth P-channel fet MP4 is Rp4, the drain-source conductance of the fourth P-channel fet MP4 is gdsp4, and Rp4 and gdsp4 are reciprocal. The second output impedance REA2 of the first error amplifier 100 is [ Rn4// (Rn5+ R2) ]// Rp4, since the drain of the seventh N-channel fet MN5 is connected to the fourth resistor R2, the drain-source conductance gdsn5 of the seventh N-channel fet MN5 is increased, the equivalent resistance Rn5 of the seventh N-channel fet MN5 is decreased, and due to the presence of the fourth resistor R1, the equivalent resistance Rn5 of the seventh N-channel fet MN5 is increased as the current flowing through the seventh N-channel fet MN5 is decreased, that is, the equivalent resistance Rn5 of the seventh N-channel fet MN5 is increased as the second current Icomp2 is decreased. When the compensation circuit of the low dropout linear regulator is in an idle state, i.e., when the second load current ILOAD2 is 0, the second current Icomp2 is maximum, and the equivalent resistance Rn5 of the seventh N-channel fet MN5 is minimum.

The transfer function indicates that the dominant pole of the first error amplifier 100 is P0 ═ 1/[2 × pi × (Ro// RL) × CL ], and the subordinate pole is P1 ═ 1/[2 × pi × REA2 × CEA2], where CEA2 is the second output capacitor of the first error amplifier 100, and Ro at this time is the output resistance when the low dropout linear regulator compensation circuit sinks current. It can be understood that to achieve stability compensation of the compensation circuit of the low dropout linear regulator, the secondary pole is far from the main pole, and the secondary pole is determined by the second output impedance of the first error amplifier 100 and the second output capacitance of the first error amplifier 100, the embodiment of the present application adjusts the second output impedance of the first error amplifier 100 to change the position of the secondary pole P1.

Since the drain-source conductance gdsp4 of the fourth P-channel fet MP4 is small, that is, the equivalent resistance Rp4 of the fourth P-channel fet MP4 is large and negligible, the second output impedance REA2 of the first error amplifier 100 may be approximated to REA2 ≈ Rn4// (Rn5+ R2).

When the compensation circuit of the low dropout linear regulator is in a light load state, the second load current ILOAD2 is greater than 0 and less than 100mA, the current flowing through the sixth N-channel fet MN4 is close to 0 and can be ignored, and the size ratio of the seventh N-channel fet MN5 to the eighth N-channel fet MN6 is N5: 1, therefore, the current flowing through the seventh N-channel fet MN5 is N5 × Icomp2, and since the current flowing through the sixth N-channel fet MN4 approaches 0, the cross-over gmn4 of the sixth N-channel fet MN4 approaches 0, that is, the equivalent resistance Rn4 of the sixth N-channel fet MN4 approaches infinity, the second output impedance REA2 of the first error amplifier 100 may approach REA2 ≈ Rn5+ R2, at this time, the second output impedance REA2 of the first error amplifier 100 is small, the position of the minor pole of the first error amplifier 100 is far away from the position of the major pole, and as the second load current ILOAD2 increases from 0 to approach 100mA, the REA2 gradually increases, and the position of the minor pole approaches the major pole as the load current increases, the phase difference voltage linear voltage regulator with low margin in this process meets the stability requirement.

When the compensation circuit of the low dropout linear regulator is in a medium load state, the second load current ILOAD2 is equal to or greater than 100mA and less than 1A, with the increase of the second load current ILOAD2, the current flowing through the sixth N-channel fet MN4 gradually increases, and since the second current Icomp2 gradually decreases, the current flowing through the seventh N-channel fet MN5 gradually decreases, at this time, the second output impedance REA2 of the first error amplifier 100 may be approximated to REA2 ≈ Rn4// (Rn5+ R2), the position of the secondary pole of the first error amplifier 100 may be changed by changing the resistance of the fourth resistor R2, and at the same time, a zero point is introduced by the presence of the fourth resistor R2, and the zero point is close to the secondary pole position, so that the phase margin of the compensation circuit of the low dropout linear regulator meets the requirement.

When the compensation circuit of the low dropout linear regulator is in a heavy load state, the second load current ILOAD2 is equal to or greater than 1A and less than 3A, the second current Icomp2 is reduced to 0, and since the equivalent resistance Rn5 of the seventh N-channel fet MN5 increases with the reduction of the second current Icomp2, the equivalent resistance Rn5 of the seventh N-channel fet MN5 is larger and negligible, and the second output impedance REA2 of the first error amplifier 100 may be approximately REA2 ≈ Rn 4. If the sixth N-channel fet MN4 with a large size is used, the drain-source voltage Vgs4 of the sixth N-channel fet MN4 is small, and when the second load current ILOAD2 is large, the current flowing through the sixth N-channel fet MN4 is also large, i.e., the second output impedance REA2 is lowered, and at this time, the gain of the second loop is also lowered, so that the output voltage of the low dropout regulator compensation circuit is increased greatly during heavy load, i.e., the load regulation rate of the low dropout regulator compensation circuit is poor. Therefore, the sixth N-channel fet MN4 with a smaller size can be used to ensure that the second output impedance REA2 has a relatively large value during heavy load, so as to prevent the gain of the second loop from being lowered, so that the output voltage can be prevented from increasing too much during heavy load, and the load regulation rate of the compensation circuit of the low dropout linear regulator can be ensured. It should be noted that, those skilled in the art can select the size of the sixth N-channel fet MN4 according to actual needs, so that the phase margin of the second loop circuit during heavy load can meet the requirement.

It can be understood that, in the compensation circuit of the low dropout regulator according to the embodiment of the present application, the first error amplifier 100 has different second output impedances when the compensation circuit is under light load, medium load, and heavy load, so as to change the secondary pole of the first error amplifier 100, so that the phase margin of the compensation circuit of the low dropout regulator meets the requirement. When the load is light, the first error amplifier 100 is lowered by the action of the second current Icomp2 to have a different second output impedance, when the load is medium, the second current Icomp2 is gradually decreased with the increase of the second load current ILOAD2, so that the action of the second current Icomp2 on lowering the second output impedance is gradually decreased, and when the load is heavy, the second load current ILOAD2 is greater than or equal to 1A, and the second current Icomp2 is 0, thereby avoiding the gain of the low dropout regulator compensating circuit from being lowered due to the low second output impedance, and improving the load regulation rate of the output voltage of the low dropout regulator compensating circuit.

The values of N4, N5, N6 and IBIAS2 may be set by those skilled in the art according to actual needs, and the present application is not limited thereto.

In addition, the embodiment of the second aspect of the present application provides a low dropout regulator, including the compensation circuit of the low dropout regulator of any embodiment of the present application.

The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.

Claims

1. A compensation circuit for a low dropout linear regulator, comprising:

2. The compensation circuit of claim 1, wherein the first error amplifier comprises a first operational amplifier, a first P-channel fet, a second P-channel fet, a third P-channel fet, and a fourth P-channel fet;

3. The low dropout regulator compensating circuit of claim 2, wherein the first compensating circuit comprises a first resistor, a first N-channel fet, a second N-channel fet, and a third N-channel fet;

4. The compensation circuit of claim 3, wherein the first current generation circuit comprises a second resistor, a third resistor, a fourth N-channel FET, a fifth N-channel FET, and a second operational amplifier;

the grid electrode of the fifth N-channel field effect transistor (HS _ Sns) is connected with the grid electrode of the fourth N-channel field effect transistor, the drain electrode of the fifth N-channel field effect transistor is connected with the inverting input end of the second operational amplifier, the drain electrode of the fifth N-channel field effect transistor is used for being connected with the second power supply through the second resistor, the non-inverting input end of the second operational amplifier is used for being connected with the second power supply through the third resistor (Rs2), and the output end of the second operational amplifier is connected with the drain electrode of the third N-channel field effect transistor.

5. The low dropout regulator compensating circuit according to claim 2, wherein the second compensating circuit comprises a sixth N-channel fet, a seventh N-channel fet, an eighth N-channel fet, and a fourth resistor, wherein the drain of the sixth N-channel fet is connected to the second output terminal of the first error amplifier, the drain of the seventh N-channel fet is connected to the gate of the sixth N-channel fet and one end of the second current generating circuit through the fourth resistor, respectively, the gate of the sixth N-channel fet is connected to the drain of the sixth N-channel fet, the gate of the seventh N-channel fet is connected to the gate of the eighth N-channel fet, and the drain of the eighth N-channel fet is connected to the other end of the second current generating circuit, respectively, The grid electrode of the eighth N-channel field effect transistor is connected; and the source electrode of the sixth N-channel field effect transistor, the source electrode of the seventh N-channel field effect transistor and the source electrode of the eighth N-channel field effect transistor are all grounded.

6. The LDO compensating circuit of claim 5, wherein said second current generating circuit comprises a ninth N-channel FET, a tenth N-channel FET and a third operational amplifier, wherein a drain of said ninth N-channel FET is connected to an output of said LDO compensating circuit, a source of said ninth N-channel FET is grounded, a gate of said ninth N-channel FET is connected to a gate of said tenth N-channel FET, a gate of said ninth N-channel FET is connected to a drain of said seventh N-channel FET through said fourth resistor, a source of said tenth N-channel FET is grounded, a drain of said tenth N-channel FET is connected to an inverting input of said third operational amplifier, a non-inverting input of said third operational amplifier is connected to an output of said LDO compensating circuit, and the output end of the third operational amplifier is connected with the drain electrode of the eighth N-channel field effect transistor.

7. The compensation circuit of claim 4, wherein the second operational amplifier comprises a fourth operational amplifier, an eleventh N-channel FET, a twelfth N-channel FET, a thirteenth N-channel FET, a fourteenth N-channel FET, a fifth P-channel FET, a sixth P-channel FET, and a first current source;

the output end of the first current source is respectively connected with the drain electrode of the twelfth N-channel field effect transistor and the drain electrode of the thirteenth N-channel field effect transistor; the output end of the first current source is also connected between the grid electrode of the thirteenth N-channel field effect transistor and the grid electrode of the fourteenth N-channel field effect transistor;

8. The low dropout linear regulator compensating circuit of claim 6 wherein the third operational amplifier comprises a fifth operational amplifier, a seventh P-channel fet, an eighth P-channel fet, a ninth P-channel fet, a tenth P-channel fet, a fifteenth N-channel fet, a sixteenth N-channel fet, a seventeenth N-channel fet, an eighteenth N-channel fet, a nineteenth N-channel fet, a second current source;

9. The compensation circuit of any one of claims 1 to 8, further comprising a load circuit, wherein the load circuit comprises a load capacitor and a load resistor, the load capacitor and the load resistor are connected in parallel, one end of the load resistor is connected to the output end of the compensation circuit of the low dropout linear regulator, and the other end of the load resistor is grounded.

10. A low dropout regulator comprising the compensation circuit of any one of claims 1 to 9.