CN113485514A - LDO overcurrent protection circuit - Google Patents
LDO overcurrent protection circuit Download PDFInfo
- Publication number
- CN113485514A CN113485514A CN202110667485.XA CN202110667485A CN113485514A CN 113485514 A CN113485514 A CN 113485514A CN 202110667485 A CN202110667485 A CN 202110667485A CN 113485514 A CN113485514 A CN 113485514A
- Authority
- CN
- China
- Prior art keywords
- transistor
- gate
- drain
- source
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003381 stabilizer Substances 0.000 claims abstract description 4
- 102100037224 Noncompact myelin-associated protein Human genes 0.000 claims description 14
- 101710184695 Noncompact myelin-associated protein Proteins 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims 4
- 230000007423 decrease Effects 0.000 description 5
- 238000005070 sampling Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention discloses an LDO (low dropout regulator) overcurrent protection circuit, which comprises: an overcurrent protection structure and a current foldback structure; the overcurrent protection structure is connected with the current foldback structure; the overcurrent protection structure clamps the maximum output current through a loop formed by a current mirror, the current foldback structure adopts a negative feedback loop formed by an error amplifier to generate a current foldback output current proportional to the output voltage, and the overcurrent limit and the foldback point voltage can be adjusted by adjusting an external resistor of the current foldback structure, so that the voltage stabilizer is prevented from generating latch. Compared with the traditional overcurrent limiting structure, the invention can reduce the power consumption and protect the power tube from being burnt; compared with the traditional turn-back type, the overcurrent limit and the turn-back point voltage can be conveniently adjusted by adjusting the external resistor, so that latch-up is avoided.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to an LDO (low dropout regulator) overcurrent protection circuit.
Background
Compared with a switching power supply, a linear regulator (LDO) has better transient response, lower noise, a more simplified circuit structure and lower cost, and is favored in mobile power supply devices. The overcurrent protection circuit is used as an important ring in the LDO circuit, can prevent overload and output short circuit from damaging the LDO circuit, and enables the LDO to work in a safe area.
Currently, there are two main modes for LDO over-current protection: constant overcurrent protection and foldback overcurrent protection. The constant over-current limit structure is simpler, but the power consumption is larger, and the power tube can be burnt by large current after long-time operation. The foldback overcurrent structure reduces the overcurrent limit when the output is reduced, avoids the risk possibly caused, but can cause LDO latch and cannot start the load.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects of the prior art are overcome, and the LDO over-current protection circuit is provided, so that compared with the traditional over-current limit structure, the power consumption can be reduced, and a power tube is protected from being burnt; compared with the traditional turn-back type, the overcurrent limit and the turn-back point voltage can be conveniently adjusted by adjusting the external resistor, so that latch-up is avoided.
The purpose of the invention is realized by the following technical scheme: an LDO over-current protection circuit, comprising: an overcurrent protection structure and a current foldback structure; the overcurrent protection structure is connected with the current foldback structure; the overcurrent protection structure clamps the maximum output current through a loop formed by a current mirror, the current foldback structure adopts a negative feedback loop formed by an error amplifier to generate a current foldback output current proportional to the output voltage, and the overcurrent limit and the foldback point voltage can be adjusted by adjusting an external resistor of the current foldback structure, so that the voltage stabilizer is prevented from generating latch.
In the LDO overcurrent protection circuit, the overcurrent protection structure includes a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP6, a transistor MN1, and a transistor MN 2; wherein the gate of the transistor MP1 is connected to the drain of the transistor MP6, and the source of the transistor MP1 is connected to the voltage VIN; the drain of the transistor MP1 is connected to the source of the transistor MP 2; the gate of the transistor MP2 is connected to the voltage VOUT; the source of the transistor MP2 is connected to the drain of the transistor MPI; the drain of the transistor MP2 is connected to the gate and drain of the transistor MN1 and the gate of the transistor MN 2; the gate of the transistor MP3 is connected to the voltage VB; the source of the transistor MP3 is connected to the voltage VIN; the drain electrode of the transistor MP3 is connected to the gate electrode of the transistor MP6 and the drain electrode of the transistor MN 2; the gate of the transistor MP6 is connected to the drain of the transistor MP 3; the source of the transistor MP6 is connected to the voltage VIN; the drain of the transistor MP6 is connected to the gate of the transistor MP 1; the gate and the drain of the transistor MN1 are connected and are connected to the gate of the transistor MN 2; the source of the transistor MN1 is connected to ground Vss; the source of the transistor MN2 is connected to ground VSs; the drain of the transistor MN2 is connected to the gate of the transistor MP6 and the drain of the transistor MP 3.
In the LDO overcurrent protection circuit, the current foldback structure includes a transistor MP4, a transistor MP5, a transistor MN3, a resistor R1, a resistor R2, and an error amplifier EA; wherein the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP 5; the source of the transistor MP4 is connected to the voltage VIN; the drain of the transistor MP4 is connected to the gate of the transistor MP6 and the drain of the transistor MP 3; the source of the transistor MP4 is connected to the voltage VIN; the gate and the drain of the transistor MP5 are connected, and are connected to the gate of the transistor MP4 and the drain of the transistor MN 3; the source of the transistor MP5 is connected to the voltage VIN; the gate of the transistor MN3 is connected to the output of the error amplifier EA; the source of the transistor MN3 is connected to a resistor R2; the drain of the transistor MN3 is connected to the gate and the drain of the transistor MP 5; the positive input end of the error amplifier EA is connected to the voltage VOUT; the negative input end of the error amplifier EA is connected to a resistor R1 and a resistor R2; the output end of the error amplifier EA is connected to the gate of a transistor MN 3; one end of the resistor R1 is connected to the resistor R2 and the negative input end of the error amplifier EA; the other end of the resistor R1 is connected to ground VSS; one end of the resistor R2 is connected to the source of the transistor MN 3; the other end of the resistor R2 is connected to the resistor R1 and the negative input end of the error amplifier EA.
In the LDO overcurrent protection circuit, the error amplifier EA includes a transistor MP7, a transistor MP8, a transistor MP9, a transistor MP10, a transistor MP11, a transistor MN4, a transistor MN5, a transistor MN6, and a transistor MN 7; wherein the gate of the transistor MP7 is connected to the voltage VB3, and the source of the transistor MP7 is connected to the voltage VIN; the drain of the transistor MP7 is connected to the source of the transistor MP8 and the source of the transistor MP 9; the gate of the transistor MP8 is connected to the voltage VOUT; the source of the transistor MP8 is connected to the source of the transistor MP 9; the drain electrode of the transistor MP8 is connected to the source electrode of the transistor MN4 and the drain electrode of the transistor MN 6; the gate of the transistor MP9 is connected to the voltage VR; the drain electrode of the transistor MP9 is connected to the source electrode of the transistor MN5 and the drain electrode of the transistor MN 7; the gate and the drain of the transistor MP10 are connected, and are connected to the gate of the transistor MP11 and the drain of the transistor MN 4; the source of the transistor MP10 is connected to the voltage VIN; the gate of the transistor MP11 is connected to the drain of the transistor MN 4; the source of the transistor MP11 is connected to the voltage VIN; the drain electrode of the transistor MP11 is connected to the drain electrode of the transistor MN 5; the gate of the transistor MN4 is connected to the gate of the transistor MN5 and to a voltage VB; the source electrode of the transistor MN4 is connected to the drain electrode of the transistor MN6 and the drain electrode of the transistor MN 8; the gate of the transistor MN5 is connected to a voltage VB 2; the source of the transistor MN5 is connected to the drain of the transistor MN 7; the gate of the transistor MN6 is connected to the gate of the transistor MN7 and to the voltage VB 1; the source of the transistor MN6 is connected to ground VSS; the gate of the transistor MN7 is connected to a voltage VB 1; the source of the transistor MN7 is connected to ground VSS.
In the LDO overcurrent protection circuit, the error amplifier EA is a folding active load amplifier.
In the LDO overcurrent protection circuit, the transistor MP1 is a mirror tube.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, the transistor MP2 and the transistor MP2 are followed by the mirror image tube MP1, so that the leakage potential of the transistor MP1 follows the output voltage, and the accurate sampling of the output current is realized;
(2) according to the invention, a negative feedback loop consisting of the transistor MN3, the resistor R1, the resistor R2 and the error amplifier EA generates current proportional to output voltage, so that the output current foldback function is realized;
(3) according to the invention, the overcurrent limit protection loop is formed by the transistors MP1, MP2, MP3, MP6, MN1 and MN2, and the maximum output current of the box position realizes overcurrent limit protection;
(4) according to the invention, the influence of the overcurrent limit on the starting of the LDO is avoided by introducing the reference current IREF;
(5) according to the invention, through the external adjustable resistors R1 and R2, the over-current limit and the voltage at the turn-back point can be adjusted, so that the invention can be suitable for various load scenes;
(6) the error amplifier EA adopts a folding active load amplifier structure, so that the overcurrent protection foldback part does not work when VOUT is high, and a large amount of power consumption is saved;
(7) when the overcurrent protection circuit has overcurrent, the overcurrent limit loop firstly clamps the output current to a fixed value, the operational amplifier starts to normally work to return the output current after the output voltage drops to a return point along with the continuous reduction of the load, and the power consumption is reduced after the output current returns.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a structural diagram of an LDO overcurrent protection circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of an error amplifier EA according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
An LDO over-current protection circuit with current limiting and foldback functions, as shown in fig. 1, the left half is an over-current protection structure: the MP1 tube is a mirror image tube; the MP2 tube enables the leakage potential of the MP1 tube to follow the output voltage, and accurate sampling of the output current is achieved. The right half part is a foldback protection structure with an external adjustable resistor, a negative feedback loop is formed by the MN3 tube, the folding error amplifier EA and the external adjustable resistors R1 and R2, and when the loop is started, the output voltage is converted into proportional current, so that the output current value is folded back.
The left half overcurrent limiting part clamps the maximum output current through a loop formed by a current mirror, and the right half return part adopts a negative feedback loop formed by an error amplifier to generate a current return output current proportional to the output voltage. The overcurrent limit and the voltage of the turn-back point can be conveniently adjusted by adjusting the external resistor, so that the voltage stabilizer is prevented from latching.
Specifically, the over-current limiting part is composed of transistors MP1, MP2, MP3, MP6, MN1, and MN 2.
The gate of the transistor MP1 is connected to the drain of the transistor MP6, and the source of MP1 is connected to the voltage VIN; the drain of MP1 is connected to the source of transistor MP 2. The gate of transistor MP2 is connected to voltage VOUT; the source of MP2 is connected to the drain of transistor MPI; the drain of MP2 is connected to the gate and drain of transistor MN1 and the gate of MN 2. The gate of transistor MP3 is connected to voltage VB; the source of MP3 is connected to voltage VIN; the drain of MP3 is connected to the gate of transistor MP6, the most polar of transistor MP4, and the drain of transistor MN 2. The gate of the transistor MP6 is connected to the drain of the drain transistor MP4 of the transistor MP3 and the drain of the transistor MN 2; the source of MP6 is connected to voltage VIN; the drain of MP6 is connected to the gate of transistor MP 1. The gate and the drain of the transistor MN1 are connected, and the transistor MN2 is connected with the gate; the source of MN1 is connected to ground Vss. The gate of the transistor MN2 is connected to the gate and the drain of the transistor MN 1; the source of MN2 is connected to ground VSs; the drain of MN2 is connected to the gate of transistor MP6, the drain of MP3, and the drain of MP 4.
The current foldback part is formed by transistors MP4, MP5, MN3, a resistor R1 and a resistor R2; an error amplifier EA.
Wherein, the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP 5; the source of MP4 is connected to voltage VIN; the drain of the MP4 is connected to the gate of the transistor MP6, the drain of the transistor MN2 of the transistor MP 3; the source of MP4 is connected to voltage VIN. The gate and the drain of the transistor MP5 are connected, and the transistor MP4 and the drain of the transistor MN3 are connected; the source of MP5 is connected to voltage VIN. The gate of transistor MN3 is connected to the output of error amplifier EA; the source of MN3 is connected to resistor R2; the drain of MN3 is connected to the gate and drain of transistor MP 5. The positive input end of the error amplifier EA is connected to the voltage VOUT; the negative input end of the EA is connected to the resistor R1 and the resistor R2; the output of EA is connected to the gate of transistor MN 3. One end of the resistor R1 is connected to the resistor R2 and the negative input end of the error amplifier EA; the other end of resistor R1 is connected to ground Vss. One end of the resistor R2 is connected to the source of the transistor MN 3; the other end of the resistor R2 is connected to the resistor R1 and the negative input end of the error amplifier EA.
As shown in fig. 2, the error amplifier EA is formed by transistors MP7, MP8, MP9, MP10. mp11; n4, MN5, MN6 and MN 7.
The gate of the transistor MP7 is connected to the voltage VB3, and the source of MP7 is connected to the voltage VIN; the drain of MP7 is connected to the source of transistor MP8 and the source of transistor MP 9. The gate of transistor MP8 is connected to voltage VOUT; the source of MP8 is connected to the source of drain transistor MP9 of transistor MP 7; the drain of the MP8 is connected to the source of the transistor MN4, the drain of MN 6. The gate of transistor MP9 is connected to voltage VR; the source of the MP9 is connected to the drain of the transistor MP7, the source of the transistor MP 8; the drain of MP9 is connected to the source of transistor MN5, the drain of MN 7. The gate and the drain of the transistor MP10 are connected, and are connected to the gate of the transistor MP11 and the drain of the transistor MN 4; the primary of MP10 is connected to voltage VIN. The gate of the transistor MP11 is connected to the gate and the drain of the transistor MP10, the drain of the transistor MN 4; the source of MP11 is connected to voltage VIN; the drain of MP11 is connected to the drain of transistor MN 5. The gate of the transistor MN4 is connected to the gate of the transistor MN5 and to the voltage VB; the source of the MN4 is connected to the drain of the transistor MN6 and the drain of the transistor MN 8; the drain of MN4 is connected to the gate and drain of transistor MP10. The gate of the transistor MN5 is connected to the gate of the transistor MN4 and to the voltage VB 2; the source of the MN5 is connected to the drain of the transistor MP9, the drain of the transistor MN 7. The gate of the transistor MN6 is connected to the gate of the transistor MN7 and to the voltage VB 1; the source of MN6 is connected to VSS; the drain of MN6 is connected to the source of MN4, the drain of transistor MP 8. The gate of the transistor MN7 is connected to the gate of the transistor MN6 and to the voltage VB 1; the source of MN7 is connected to VSS; the drain of MN7 is connected to the source of MN5, the drain of transistor MP 9.
The LDO over-current protection circuit with the current limiting and foldback functions can conveniently determine the over-current limit and the foldback point voltage by adjusting the external resistor, so that different over-current protection requirements and load requirements are met. As shown in figure 1 of the drawings, in which,
the left half part is an overcurrent protection structure: the MP1 tube is a mirror image tube; the MP2 tube enables the leakage potential of the MP1 tube to follow the output voltage, and accurate sampling of the output current is achieved. The right half part is a foldback protection structure with an external adjustable resistor, a negative feedback loop is formed by the MN3 tube, the error amplifier EA and the external adjustable resistors R1 and R2, and when the loop is started, the output voltage is converted into proportional current, so that the output current value is folded back.
Specifically, the current of the overcurrent loop branch is determined by the smaller current of the N tube and the P tube. When the output current is smaller than the clamping current, the MP3 and MP4 tubes work in a linear region, the VCON potential is pulled up to VIN to turn off the MP6 tubes, and the normal operation of the LDO is not influenced by the overcurrent limit. When the output current reaches the clamping current, the N tube and the P tube work in a saturation region, and the output current is determined by the sum of the two branches of the P tube.
In order to realize the output current foldback function, the branch current of the MP4 tube is proportional to the output voltage to reduce the overcurrent limit by utilizing the characteristic that the output voltage is reduced after the output current is clamped. And a reference current IREF is introduced, so that the influence of an overcurrent limit on the starting of the LDO is avoided.
The EA amplifier in the foldback configuration is shown in fig. 2, and in order to ensure that the overcurrent protection foldback portion does not operate when VOUT is high, a foldback active load amplifier is used, and the operation is turned off when the output voltage VOUT > VGS, MP8+ Vov, MP 7. When the LDO works normally, the voltage drop is small enough, the EA amplifier does not work at the moment, the output potential of the operational amplifier is high potential (power supply potential), the branch current is determined by MN3, R1 and R2, and the maximum value of the output current is clamped at a constant value.
When the output current is clamped, the output voltage linearly decreases when the output load continues to decrease until the operational amplifier starts to work normally after the output voltage decreases to the voltage of the turning point. The output foldback point voltage is determined by the over-current limit of the operational amplifier during clamping. The drain-source voltage across the power transistor, i.e. the difference between the input voltage and the output voltage, increases as the output voltage decreases, however, the leakage current thereof decreases. The power consumption of the power tube is reduced along with the reduction of the load, namely the power consumption is reduced after the output current is folded back.
Therefore, through the embodiment, compared with the traditional constant overcurrent limiting structure, the improved externally adjustable foldback LDO overcurrent protection circuit with the current limiting function saves a large amount of power consumption after overcurrent and avoids the power tube from being burnt due to overlarge heat; compared with the traditional foldback type overcurrent structure, the latch-up phenomenon caused by the intersection of an overcurrent curve and a load line is avoided; through adjusting the external resistor, the overcurrent limit and the voltage of the turn-back point can be conveniently adjusted, so that the overcurrent limit structure can be applied to various load scenes.
According to the invention, the transistor MP2 and the transistor MP2 are followed by the mirror image tube MP1, so that the leakage potential of the transistor MP1 follows the output voltage, and the accurate sampling of the output current is realized; according to the invention, a negative feedback loop consisting of the transistor MN3, the resistor R1, the resistor R2 and the error amplifier EA generates current proportional to output voltage, so that the output current foldback function is realized; according to the invention, the overcurrent limit protection loop is formed by the transistors MP1, MP2, MP3, MP6, MN1 and MN2, and the maximum output current of the box position realizes overcurrent limit protection; according to the invention, the influence of the overcurrent limit on the starting of the LDO is avoided by introducing the reference current IREF; according to the invention, through the external adjustable resistors R1 and R2, the over-current limit and the voltage at the turn-back point can be adjusted, so that the invention can be suitable for various load scenes; the error amplifier EA adopts a folding active load amplifier structure, so that the overcurrent protection foldback part does not work when VOUT is high, and a large amount of power consumption is saved; when the overcurrent protection circuit has overcurrent, the overcurrent limit loop firstly clamps the output current to a fixed value, the operational amplifier starts to normally work to return the output current after the output voltage drops to a return point along with the continuous reduction of the load, and the power consumption is reduced after the output current returns.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (6)
1. An LDO over-current protection circuit, comprising: an overcurrent protection structure and a current foldback structure; wherein the content of the first and second substances,
the overcurrent protection structure is connected with the current foldback structure;
the overcurrent protection structure clamps the maximum output current through a loop formed by a current mirror, the current foldback structure adopts a negative feedback loop formed by an error amplifier to generate a current foldback output current proportional to the output voltage, and the overcurrent limit and the foldback point voltage can be adjusted by adjusting an external resistor of the current foldback structure, so that the voltage stabilizer is prevented from generating latch.
2. The LDO overcurrent protection circuit of claim 1, wherein: the overcurrent protection structure comprises a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP6, a transistor MN1 and a transistor MN 2; wherein the content of the first and second substances,
the gate of the transistor MP1 is connected to the drain of the transistor MP6, and the source of the transistor MP1 is connected to the voltage VIN; the drain of the transistor MP1 is connected to the source of the transistor MP 2;
the gate of the transistor MP2 is connected to the voltage VOUT; the source of the transistor MP2 is connected to the drain of the transistor MPI; the drain of the transistor MP2 is connected to the gate and drain of the transistor MN1 and the gate of the transistor MN 2;
the gate of the transistor MP3 is connected to the voltage VB; the source of the transistor MP3 is connected to the voltage VIN; the drain electrode of the transistor MP3 is connected to the gate electrode of the transistor MP6 and the drain electrode of the transistor MN 2;
the gate of the transistor MP6 is connected to the drain of the transistor MP 3; the source of the transistor MP6 is connected to the voltage VIN; the drain of the transistor MP6 is connected to the gate of the transistor MP 1;
the gate and the drain of the transistor MN1 are connected and are connected to the gate of the transistor MN 2; the source of the transistor MN1 is connected to ground Vss;
the source of the transistor MN2 is connected to ground VSs; the drain of the transistor MN2 is connected to the gate of the transistor MP6 and the drain of the transistor MP 3.
3. The LDO overcurrent protection circuit of claim 2, wherein: the current foldback structure comprises a transistor MP4, a transistor MP5, a transistor MN3, a resistor R1, a resistor R2 and an error amplifier EA; wherein the content of the first and second substances,
the gate of the transistor MP4 is connected to the gate and the drain of the transistor MP 5; the source of the transistor MP4 is connected to the voltage VIN; the drain of the transistor MP4 is connected to the gate of the transistor MP6 and the drain of the transistor MP 3; the source of the transistor MP4 is connected to the voltage VIN;
the gate and the drain of the transistor MP5 are connected, and are connected to the gate of the transistor MP4 and the drain of the transistor MN 3; the source of the transistor MP5 is connected to the voltage VIN;
the gate of the transistor MN3 is connected to the output of the error amplifier EA; the source of the transistor MN3 is connected to a resistor R2; the drain of the transistor MN3 is connected to the gate and the drain of the transistor MP 5;
the positive input end of the error amplifier EA is connected to the voltage VOUT; the negative input end of the error amplifier EA is connected to a resistor R1 and a resistor R2; the output end of the error amplifier EA is connected to the gate of a transistor MN 3;
one end of the resistor R1 is connected to the resistor R2 and the negative input end of the error amplifier EA; the other end of the resistor R1 is connected to ground Vss;
one end of the resistor R2 is connected to the source of the transistor MN 3; the other end of the resistor R2 is connected to the resistor R1 and the negative input end of the error amplifier EA.
4. The LDO over-current protection circuit of claim 3, wherein: the error amplifier EA includes a transistor MP7, a transistor MP8, a transistor MP9, a transistor MP10, a transistor MP11, a transistor MN4, a transistor MN5, a transistor MN6, and a transistor MN 7; wherein the content of the first and second substances,
the gate of the transistor MP7 is connected to the voltage VB3, and the source of the transistor MP7 is connected to the voltage VIN; the drain of the transistor MP7 is connected to the source of the transistor MP8 and the source of the transistor MP 9;
the gate of the transistor MP8 is connected to the voltage VOUT; the source of the transistor MP8 is connected to the source of the transistor MP 9; the drain electrode of the transistor MP8 is connected to the source electrode of the transistor MN4 and the drain electrode of the transistor MN 6;
the gate of the transistor MP9 is connected to the voltage VR; the drain electrode of the transistor MP9 is connected to the source electrode of the transistor MN5 and the drain electrode of the transistor MN 7;
the gate and the drain of the transistor MP10 are connected, and are connected to the gate of the transistor MP11 and the drain of the transistor MN 4; the source of the transistor MP10 is connected to the voltage VIN;
the gate of the transistor MP11 is connected to the drain of the transistor MN 4; the source of the transistor MP11 is connected to the voltage VIN; the drain electrode of the transistor MP11 is connected to the drain electrode of the transistor MN 5;
the gate of the transistor MN4 is connected to the gate of the transistor MN5 and to a voltage VB; the source electrode of the transistor MN4 is connected to the drain electrode of the transistor MN6 and the drain electrode of the transistor MN 8;
the gate of the transistor MN5 is connected to a voltage VB 2; the source of the transistor MN5 is connected to the drain of the transistor MN 7;
the gate of the transistor MN6 is connected to the gate of the transistor MN7 and to the voltage VB 1; the source of the transistor MN6 is connected to a voltage VSS;
the gate of the transistor MN7 is connected to a voltage VB 1; the source of the transistor MN7 is connected to VSS.
5. The LDO over-current protection circuit of claim 3, wherein: the error amplifier EA is a folded active load amplifier.
6. The LDO overcurrent protection circuit of claim 2, wherein: the transistor MP1 is a mirror tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110667485.XA CN113485514A (en) | 2021-06-16 | 2021-06-16 | LDO overcurrent protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110667485.XA CN113485514A (en) | 2021-06-16 | 2021-06-16 | LDO overcurrent protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113485514A true CN113485514A (en) | 2021-10-08 |
Family
ID=77935352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110667485.XA Pending CN113485514A (en) | 2021-06-16 | 2021-06-16 | LDO overcurrent protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113485514A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115729308A (en) * | 2023-01-13 | 2023-03-03 | 上海海栎创科技股份有限公司 | Dynamic current-limiting control system |
| CN117472139A (en) * | 2023-12-28 | 2024-01-30 | 成都时域半导体有限公司 | Novel LDO power tube driving circuit without through current and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213908A1 (en) * | 2009-02-25 | 2010-08-26 | Mediatek Inc. | Low dropout regulators |
| CN202720534U (en) * | 2012-07-30 | 2013-02-06 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low dropout linear regulator circuit capable of enhancing stability of loop |
| CN104167999A (en) * | 2014-08-12 | 2014-11-26 | 成都信息工程学院 | Error amplifier used for switching power supply |
| CN109032241A (en) * | 2018-08-24 | 2018-12-18 | 电子科技大学 | A kind of low pressure difference linear voltage regulator charging ductility limit function |
| CN112462838A (en) * | 2020-12-04 | 2021-03-09 | 电子科技大学 | Overcurrent protection circuit of low dropout linear regulator with adjustable overcurrent limit and foldback point |
-
2021
- 2021-06-16 CN CN202110667485.XA patent/CN113485514A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213908A1 (en) * | 2009-02-25 | 2010-08-26 | Mediatek Inc. | Low dropout regulators |
| CN202720534U (en) * | 2012-07-30 | 2013-02-06 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low dropout linear regulator circuit capable of enhancing stability of loop |
| CN104167999A (en) * | 2014-08-12 | 2014-11-26 | 成都信息工程学院 | Error amplifier used for switching power supply |
| CN109032241A (en) * | 2018-08-24 | 2018-12-18 | 电子科技大学 | A kind of low pressure difference linear voltage regulator charging ductility limit function |
| CN112462838A (en) * | 2020-12-04 | 2021-03-09 | 电子科技大学 | Overcurrent protection circuit of low dropout linear regulator with adjustable overcurrent limit and foldback point |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115729308A (en) * | 2023-01-13 | 2023-03-03 | 上海海栎创科技股份有限公司 | Dynamic current-limiting control system |
| CN117472139A (en) * | 2023-12-28 | 2024-01-30 | 成都时域半导体有限公司 | Novel LDO power tube driving circuit without through current and electronic equipment |
| CN117472139B (en) * | 2023-12-28 | 2024-03-15 | 成都时域半导体有限公司 | Novel LDO power tube driving circuit without through current and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109032241B (en) | Low-dropout linear voltage regulator with current limiting function | |
| CN112462838B (en) | Overcurrent protection circuit of low dropout linear regulator with adjustable overcurrent limit and foldback point | |
| US5563501A (en) | Low voltage dropout circuit with compensating capacitance circuitry | |
| KR101071799B1 (en) | Constant voltage circuit and method of controlling output voltage of constant voltage circuit | |
| US7548044B2 (en) | Constant-voltage power circuit with fold back current limiting capability | |
| US5552697A (en) | Low voltage dropout circuit with compensating capacitance circuitry | |
| JP2017523530A (en) | Short circuit protection for voltage regulator | |
| KR102225712B1 (en) | Voltage regulator | |
| CN113050750B (en) | Low dropout regulator capable of realizing wide input range and rapid stable state | |
| JP2012088987A (en) | Semiconductor integrated circuit for regulators | |
| CN112860002B (en) | Instantaneous response linear voltage regulator | |
| CN113485514A (en) | LDO overcurrent protection circuit | |
| CN113067469A (en) | Quick response loop compensation circuit, loop compensation chip and switching power supply | |
| WO2022057026A1 (en) | Internal power generation circuit | |
| CN113342109A (en) | Low dropout regulator with maximum current limiting function | |
| CN106055011A (en) | Self-startup power supply circuit | |
| TWI514104B (en) | Current source for voltage regulator and voltage regulator thereof | |
| CN213934662U (en) | Linear voltage stabilizing circuit without off-chip capacitor | |
| US20020125937A1 (en) | Bandgap reference voltage circuit | |
| CN113406989A (en) | Low dropout linear regulator compensation circuit and low dropout linear regulator | |
| CN110888487B (en) | Low dropout regulator and electronic equipment | |
| CN115079762B (en) | Low dropout linear voltage regulator circuit | |
| CN215576341U (en) | Voltage-stabilizing source circuit | |
| CN215117309U (en) | Low dropout linear regulator compensation circuit and low dropout linear regulator | |
| CN114895743A (en) | Low starting current circuit for dynamic bias current LDO |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211008 |
|
| RJ01 | Rejection of invention patent application after publication |