CN114167933A

CN114167933A - Low-dropout linear regulator circuit with low power consumption and fast transient response

Info

Publication number: CN114167933A
Application number: CN202111475165.0A
Authority: CN
Inventors: 李天望
Original assignee: Shanghai Lingrui Microelectronics Co ltd
Current assignee: Shanghai Lingrui Microelectronics Co ltd
Priority date: 2021-12-06
Filing date: 2021-12-06
Publication date: 2022-03-11
Anticipated expiration: 2041-12-06
Also published as: CN114167933B

Abstract

The invention belongs to the technical field of electronic circuits and semiconductors, and particularly relates to a low dropout linear regulator circuit. A low dropout linear regulator circuit with low power consumption and fast transient response, comprising: an error amplifier; a series regulating power tube, the grid of which is connected with the output end of the error amplifier; the resistance feedback network is provided with a first resistance and a second resistance which are connected in series, the common end of the first resistance and the second resistance is used as a feedback end, and the other end of the second resistance is grounded; the same-direction input end of the error amplifier is connected with a reference voltage, and the reverse input end of the error amplifier is connected with a feedback end; the drain electrode of the series adjusting power tube is connected with the power input end, the source electrode of the series adjusting power tube is connected with the output end of the circuit, and the output end of the circuit is also connected with the other end of the first resistor; further comprising: and the output end of the bias circuit is respectively connected with the error amplifier and the circuit output end. The invention has the function of fast load transient response, and improves the load response speed of the low dropout linear regulator circuit through a simpler circuit.

Description

Low-dropout linear regulator circuit with low power consumption and fast transient response

Technical Field

The invention belongs to the technical field of electronic circuits and semiconductors, and particularly relates to a low dropout linear regulator circuit.

Background

Power supply and power regulation are the most basic functions of an electrical system. Any loaded application will not work properly without a stable power supply. Low dropout linear regulators (LDO) are increasingly used in SOC designs due to their simple structure, low power consumption, small output ripple and few peripheral circuits. The low dropout linear regulator circuit mainly comprises a reference voltage source, an error amplifier, a series regulation power tube and a resistance feedback network.

Fig. 1 is a block diagram of a typical low dropout linear regulator, wherein a reference voltage Vref is connected to an inverting input terminal of an error amplifier, a non-inverting input terminal of the error amplifier is connected to a common terminal VFB of a first resistor R1 and a second resistor R2 of a resistor feedback network, an output terminal of the error amplifier is connected to a gate of a PMOS power transistor MP0, a common terminal of a drain terminal of the MP0 and a first resistor R1 serves as an output voltage VOUT of the low dropout linear regulator, CL is an output load capacitor, and IL is an output load current. In fig. 1, when the output load changes, the output voltage changes are fed back to the homodromous input end of the error amplifier through the resistor feedback network, and the input end of the error amplifier generates a differential voltage, so as to adjust the output voltage of the error amplifier, that is, adjust the gate voltage of the power transistor MP0, and further adjust the magnitude of the output current, so that the output voltage is stabilized.

With the development of integrated circuit technology and the continuous progress of semiconductor technology, the supply voltage of digital circuits is continuously reduced, which has higher requirements on the load transient performance of the LDO supplying the digital circuits. With the continuous improvement of the integration level of the digital circuit, the power consumption is continuously increased, so that the transient response of the LDO becomes worse, and the power consumption of the whole SOC becomes larger, so that the reduction of the power consumption of the LDO circuit is very important. The conventional LDO often has an external capacitor for the good load transient response, which cannot meet the requirement of high integration and also increases the complexity of the peripheral circuit. The conventional LDO circuit cannot meet the design requirements, and particularly, under the conditions that the current integration level is higher and higher, and the LDO without an off-chip capacitor is applied more and more widely, it is more necessary to improve the transient response capability of the LDO and reduce the static power consumption of the LDO.

Therefore, how to design a low dropout linear regulator with low power consumption and fast transient response becomes a problem to be solved currently.

Disclosure of Invention

The invention aims to solve the technical problems that the traditional LDO circuit has large static power consumption and cannot meet the transient response capability with higher requirements, and provides a low-power-consumption and quick transient response low-dropout linear regulator circuit.

A low dropout linear regulator circuit with low power consumption and fast transient response, comprising:

an error amplifier;

a grid electrode of the series adjusting power tube is connected with the output end of the error amplifier;

the resistance feedback network is provided with a first resistance and a second resistance which are connected in series, the common end of the first resistance and the second resistance is used as a feedback end, and the other end of the second resistance is grounded;

the same-direction input end of the error amplifier is connected with a reference voltage, and the reverse-direction input end of the error amplifier is connected with the feedback end;

the drain electrode of the series adjusting power tube is connected with the power input end, the source electrode of the series adjusting power tube is connected with the circuit output end, and the circuit output end is also connected with the other end of the first resistor;

further comprising:

and the output end of the bias circuit is respectively connected with the error amplifier and the circuit output end.

Preferably, the system further comprises a load transient response enhancement circuit, wherein the load transient response enhancement circuit comprises:

and one end of the first capacitor is connected with the output end of the bias circuit, and the other end of the first capacitor is connected with the output end of the circuit.

Preferably, the error amplifier includes:

the tail current source is a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of the tail current source is connected with the output end of the bias circuit, and the source electrode of the tail current source is connected with the power supply input end;

the differential pair comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein the source electrodes of the first PMOS tube and the second PMOS tube are connected with the drain electrode of the tail current source, the grid electrode of the first PMOS tube is connected with the reference voltage, and the grid electrode of the second PMOS tube is connected with the feedback end;

the load current source circuit is provided with a first NMOS tube and a second NMOS tube, the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with the drain electrode, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube.

Preferably, the method further comprises the following steps:

and one end of the compensation capacitor is connected with the common end of the second PMOS tube and the second NMOS tube, and the other end of the compensation capacitor is grounded.

Preferably, the error amplifier is connected to the gate of the series-adjusting power transistor through a source follower buffer circuit.

Preferably, the source follower buffer circuit includes:

the third PMOS tube is used as a source electrode follower, the grid electrode of the third PMOS tube is connected with the common end of the second PMOS tube and the common end of the second NMOS tube, and the drain electrode of the third PMOS tube is grounded;

the grid electrode of the fourth PMOS tube is connected with the output end of the bias circuit, the source electrode of the fourth PMOS tube is connected with the power supply input end, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube;

and the common end of the source electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube is used as the buffer output end of the error amplifier and is connected with the grid electrode of the series adjusting power tube.

Preferably, the bias circuit includes:

one end of the bias current source is connected with the power supply input end;

the drain electrode of the third NMOS tube is connected with the other end of the bias current source, the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is connected with the drain electrode;

the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is grounded;

and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fifth PMOS tube is connected with the power input end, and the grid electrode of the fifth PMOS tube is connected with the drain electrode and serves as the output end of the bias circuit.

Preferably, the method further comprises the following steps:

and the mode switching circuit is provided with a first switching circuit, the output end of the first switching circuit is connected with the control end of the bias circuit, and the first switching circuit controls the working state of the bias circuit.

Preferably, the first switching circuit includes:

the two control signals are respectively a first control signal and a second control signal, and the two control signals are mutually reverse signals;

the grid electrode of the fifth NMOS tube is connected with the second control signal, and the source electrode of the fifth NMOS tube is connected with the grid electrode of the third NMOS tube;

the grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the common ends of the fourth NMOS tube and the fifth PMOS tube, and the source electrode of the sixth NMOS tube is grounded;

the grid electrode of the seventh NMOS tube is connected with the first control signal, the drain electrode of the seventh NMOS tube is respectively connected with the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the seventh NMOS tube is grounded;

when the load circuit is in a working mode under a normal working state, the first control signal is made to be at a low level, the second control signal is at a high level, the fifth NMOS tube is conducted, the grid electrode of the sixth NMOS tube is biased at a preset voltage, and the fifth PMOS tube flows through a bias current to provide the bias current for each subsequent current mirror;

when the load circuit is in a standby mode in a standby state, the first control signal is made to be at a high level, the second control signal is at a low level, the fifth NMOS tube is disconnected at the moment, the seventh NMOS tube is conducted to pull down the grid of the sixth NMOS tube to the ground, the sixth NMOS tube is closed to reduce the current flowing through the fifth PMOS tube, and the current at the output end of the bias circuit is reduced.

Preferably, the mode switching circuit further includes a second switching circuit, and the second switching circuit includes:

the drain electrode of the sixth PMOS tube is connected with the common end of the differential pair of the error amplifier, and the source electrode of the sixth PMOS tube is connected with the power supply input end;

the grid electrode of the seventh PMOS tube is connected with the first control signal, and the source electrode of the seventh PMOS tube is connected with the output end of the bias circuit;

the eighth PMOS tube is used as a switching tube, the grid electrode of the eighth PMOS tube is connected with the second control signal, the drain electrode of the eighth PMOS tube is respectively connected with the grid electrode of the sixth PMOS tube and the drain electrode of the seventh PMOS tube, and the source electrode of the eighth PMOS tube is connected with the power supply input end;

a ninth PMOS tube, the grid electrode of which is connected with the drain electrode of the eighth PMOS tube, the drain electrode of which is connected with the grid electrode of the series adjusting power tube, and the source electrode of which is connected with the power input end;

when the load circuit is in a working mode under a normal working state, the first control signal is made to be at a low level, the second control signal is at a high level, and the differential pair of the error amplifier normally works through the bias current output by the output end of the bias circuit;

when the load circuit is in a standby mode in a standby state, the first control signal is at a high level, the second control signal is at a low level, the sixth PMOS tube and the ninth PMOS tube are disconnected, and the current of the differential pair of the error amplifier is reduced.

Preferably, the mode switching circuit further includes a third switching circuit, and the third switching circuit includes:

the eighth NMOS tube is used as a switching tube, the grid electrode of the eighth NMOS tube is connected with the second control signal, and the source electrode of the eighth NMOS tube is connected with the common end of the load current source circuit of the error amplifier;

the grid electrode of the ninth NMOS tube is connected with the first control signal, and the source electrode of the ninth NMOS tube is grounded;

a tenth NMOS tube, a grid electrode of which is respectively connected with the drain electrode of the eighth NMOS tube and the drain electrode of the ninth NMOS tube, the drain electrode of which is connected with the output end of the circuit, and a source electrode of which is grounded;

when the load circuit is in a working mode under a normal working state, the first control signal is made to be at a low level, the second control signal is at a high level, and the load current source circuit of the error amplifier works normally;

when the load circuit is in a standby mode in a standby state, the first control signal is at a high level, the second control signal is at a low level, the eighth NMOS transistor is turned off, the ninth NMOS transistor is turned on to pull down the gate of the tenth NMOS transistor to the ground, and the tenth NMOS transistor is turned off to further reduce the current flowing through the output end of the circuit.

The positive progress effects of the invention are as follows: the low dropout linear regulator circuit adopting low power consumption and rapid transient response has the following advantages:

1. the low dropout linear regulator has a quick load transient response function, and improves the load response speed of the low dropout linear regulator circuit through a simpler circuit.

2. The self-adaptive bias circuit is designed, and when the load circuit works normally, the stability requirement can be met by increasing the current of each branch circuit, the load transient performance of the circuit is improved, and the problems of reducing power consumption and improving transient response are properly solved.

3. And meanwhile, a dynamic adjusting circuit is designed, and when the output voltage changes, the current of the output power tube is quickly adjusted by dynamically adjusting the charging and discharging current of the grid electrode of the series adjusting power tube and the current of the output branch circuit so as to deal with the quick change of the load current, so that the stability of the output voltage of the output end of the circuit is maintained.

4. The bias circuit is controlled by the mode switching circuit, so that the error amplifier is controlled, the magnitude of the quiescent current of the power tube is adjusted in series, two working modes of low power consumption and heavy current load can be realized, and the low dropout linear voltage regulator circuit has low power under the condition of no load current.

Drawings

FIG. 1 is a schematic circuit diagram of a conventional LDO regulator;

FIG. 2 is a schematic circuit diagram according to the present invention.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific drawings.

Referring to fig. 2, a low-power-consumption fast transient response low dropout regulator circuit includes an error amplifier, a series-regulated power transistor MPOWER, a resistance feedback network, a compensation capacitor C2, a source follower buffer, a bias circuit, a load transient response enhancement circuit, and a mode switching circuit.

The same-direction input end of the error amplifier is connected with the reference voltage Vref, and the reverse-direction input end of the error amplifier is connected with the feedback end VFB. The error amplifier includes a tail current source, a differential pair, and a load current source circuit.

The tail current source is a PMOS pipe PM0, influences the bandwidth of the error amplifier and plays a certain role in transient state. The grid electrode of the tail current source is connected with the output end of the bias circuit, the source electrode of the tail current source is connected with the power input end VDD, and the drain electrodes of the tail current source are respectively connected with the common ends of the differential pairs.

The differential pair is respectively a first PMOS transistor PM1 and a second PMOS transistor PM2, the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are used as common ends and are both connected with the drain of a tail current source, the grid of the first PMOS transistor PM1 is connected with a reference voltage Vref, and the grid of the second PMOS transistor PM2 is connected with a feedback end VFB.

The load current source circuit is provided with a first NMOS tube NM1 and a second NMOS tube NM2, the drain electrode of the first NMOS tube NM1 is connected with the drain electrode of the first PMOS tube PM1, the source electrode of the first NMOS tube NM1 is grounded, the grid electrode of the first NMOS tube NM1 is connected with the drain electrode, the drain electrode of the second NMOS tube NM2 is connected with the drain electrode of the second PMOS tube PM2, the source electrode of the second NMOS tube NM2 is grounded, and the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM 1.

One end of the compensation capacitor C2 is connected to the common terminal of the second PMOS transistor PM2 and the second NMOS transistor NM2, and the other end of the compensation capacitor C2 is grounded. The stability of the whole circuit can be further maintained by adding the compensation capacitor C2 to the common terminal of the drains of the second PMOS transistor PM2 and the second NMOS transistor NM 2.

The output end of the error amplifier is preferably connected with the grid of the series-regulated power tube MPOWER through a source follower buffer circuit. The source follower buffer circuit comprises a third PMOS transistor PM3 and a fourth PMOS transistor PM 4.

The third PMOS transistor PM3 is used as a source follower, the gate of the third PMOS transistor PM3 is connected to the output end of the error amplifier, that is, the gate of the third PMOS transistor PM3 is connected to the common end of the second PMOS transistor PM2 and the second NMOS transistor NM2, the drain of the third PMOS transistor PM3 is grounded, and the source of the third PMOS transistor PM3 is connected to the drain of the fourth PMOS transistor PM 4.

The gate of the fourth PMOS transistor PM4 is connected to the output terminal of the bias circuit, the source of the fourth PMOS transistor PM4 is connected to the power input terminal VDD, and the drain of the fourth PMOS transistor PM4 is connected to the source of the third PMOS transistor PM 3.

The common end of the source electrode of the third PMOS tube PM3 and the drain electrode of the fourth PMOS tube PM4 is used as a buffer output end of the error amplifier and is connected with the grid electrode of the series regulation power tube MPOWER.

The gate of the series-adjustment power transistor MPOWER is preferably connected to the output terminal of the error amplifier through a source follower buffer circuit, and preferably, the gate of the series-adjustment power transistor MPOWER is connected to the source of the third PMOS transistor PM3 and the common drain of the fourth PMOS transistor PM 4. The drain of the series regulation power tube MPOWER is connected with the power supply input end VDD, and the source of the series regulation power tube MPOWER is connected with the output end VOUT of the circuit. The series-adjustment power tube MPOWER can be a normal NMOS tube, and the substrate of the series-adjustment power tube MPOWER can be connected with a non-self substrate or a self substrate according to the applied power voltage condition.

The resistor feedback network is provided with a first resistor R1 and a second resistor R2 which are connected in series, the common end of the first resistor R1 and the second resistor R2 is used as a feedback end VFB, the other end of the first resistor R1 is connected with the circuit output end VOUT, and the other end of the second resistor R2 is grounded.

The output end of the bias circuit is respectively connected with the error amplifier, the source electrode following buffer circuit, the mode switching circuit and the circuit output end VOUT. The bias circuit comprises a bias current source IB, a third NMOS transistor NM3, a fourth NMOS transistor NM4 and a fifth PMOS transistor PM 5.

One end of the bias current source IB is connected to the power input terminal VDD, and the other end of the bias current source IB is connected to the drain of the third NMOS transistor NM 3.

The drain of the third NMOS transistor NM3 is connected to the other end of the bias current source IB, the source of the third NMOS transistor NM3 is grounded, and the gate of the third NMOS transistor NM3 is connected to the drain.

The gate of the fourth NMOS transistor NM4 is connected to the gate of the third NMOS transistor NM3, the drain of the fourth NMOS transistor NM4 is connected to the drain of the fifth PMOS transistor PM5, and the source of the fourth NMOS transistor NM4 is grounded.

The grid electrode of the fifth PMOS pipe PM5 is connected with the drain electrode and serves as the output end of the bias circuit, the drain electrode of the fifth PMOS pipe PM5 is connected with the drain electrode of the fourth NMOS pipe NM4, and the source electrode of the fifth PMOS pipe PM5 is connected with the power supply input end VDD.

The output terminal of the bias circuit is preferably connected to the circuit output terminal VOUT via a load transient response enhancement circuit. The load transient response enhancement circuit comprises a first capacitor C1, one end of the first capacitor C1 is connected with the output end of the bias circuit, and the other end of the first capacitor C1 is connected with the circuit output end VOUT. The change of the output terminal VOUT of the circuit is sensed and transmitted through the first capacitor C1 to the components connected to the output terminal of the bias circuit.

The mode switching circuit includes a first switching circuit, a second switching circuit, and a third switching circuit. The output end of the first switching circuit is connected with the control end of the bias circuit, and the first switching circuit controls the working state of the bias circuit. The second switching circuit is connected with the common end of the differential pair of the error amplifier, and controls the current of the differential pair of the error amplifier and the current of the source electrode following buffer circuit. The third switching circuit is connected with the common end of the load current source circuit of the error amplifier, and the current of the third switching circuit is adjusted through the voltage change of the load current source circuit of the error amplifier so as to further control the voltage of the output end of the circuit.

The first switching circuit includes two control signals, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM 7.

The two control signals are a first control signal Deep and a second control signal Deep, which are opposite signals, that is, when the first control signal Deep is at a high level (Deep ═ 1), the second control signal Deep is at a low level (Deep ═ 0), and when the first control signal Deep is at a low level (Deep ═ 0), the second control signal Deep is at a high level (Deep ═ 1). Both control signals may be provided by an external power control circuit.

A gate of the fifth NMOS transistor NM5 is connected to the second control signal deep b, and a source of the fifth NMOS transistor NM5 is connected to the gate of the third NMOS transistor NM 3. The gate of the sixth NMOS transistor NM6 is connected to the drain of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6 is connected to the common terminal of the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5, and the source of the sixth NMOS transistor NM6 is grounded. A gate of the seventh NMOS transistor NM7 is connected to the first control signal Deep, a drain of the seventh NMOS transistor NM7 is connected to a drain of the fifth NMOS transistor NM5 and a gate of the sixth NMOS transistor NM6, respectively, and a source of the seventh NMOS transistor NM7 is grounded.

When the load circuit is in a working mode in a normal working state, the first control signal Deep is made to be a low level (Deep ═ 0), the second control signal Deep b is a high level (Deep ═ 1), at this time, the fifth NMOS transistor NM5 is turned on, the gate of the sixth NMOS transistor NM6 is biased at a preset voltage, and the fifth PMOS transistor PM5 flows through a large bias current to provide a large bias current for each subsequent current mirror; when the load circuit is in a standby mode in a standby state, the load current is small, and the first control signal Deep is set to a high level (Deep ═ 1), the second control signal Deep is set to a low level (Deep ═ 0), at this time, the fifth NMOS transistor NM5 is turned off, the seventh NMOS transistor NM7 is turned on to pull down the gate of the sixth NMOS transistor NM6 to the ground, the sixth NMOS transistor NM6 is turned off to reduce the current flowing through the fifth PMOS transistor PM5, and the output end current of the bias circuit is reduced, thereby reducing the power consumption of the entire low dropout linear regulator circuit.

The second switching circuit comprises a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8 and a ninth PMOS transistor PM 9. The drain of the sixth PMOS transistor PM6 is connected to the common terminal of the differential pair of the error amplifier, and preferably, the drain of the sixth PMOS transistor PM6 is connected to the common terminal of the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2, the source of the sixth PMOS transistor PM6 is connected to the power input terminal VDD, and the gate of the sixth PMOS transistor PM6 is connected to the drain of the eighth PMOS transistor PM 8. The gate of the seventh PMOS transistor PM7 is connected to the first control signal Deep, the source of the seventh PMOS transistor PM7 is connected to the output of the bias circuit, and the drain of the seventh PMOS transistor PM7 is connected to the drain of the eighth PMOS transistor PM 8. The eighth PMOS transistor PM8 is used as a switch transistor, the gate of the eighth PMOS transistor PM8 is connected to the second control signal deep b, the drain of the eighth PMOS transistor PM8 is connected to the gate of the sixth PMOS transistor PM6 and the drain of the seventh PMOS transistor PM7, respectively, and the source of the eighth PMOS transistor PM8 is connected to the power input terminal VDD. The gate of the ninth PMOS transistor PM9 is connected to the drain of the eighth PMOS transistor PM8, the drain of the ninth PMOS transistor PM9 is connected to the gate of the series regulator MPOWER, and the source of the ninth PMOS transistor PM9 is connected to the power input terminal VDD.

When the load circuit is in a working mode in a normal working state, the first control signal Deep is made to be at a low level (Deep ═ 0), the second control signal Deep b is at a high level (Deep ═ 1), a large bias current is output through the output end of the bias circuit, the current of each branch of the error amplifier, the current of the source following buffer circuit and the current of the output branch are increased, and the adjusting speed of the whole circuit is accelerated; when the load circuit is in the standby mode in the standby state, the first control signal Deep is set to the high level (Deep ═ 1), the second control signal Deep b is set to the low level (Deep ═ 0), at this time, the sixth PMOS transistor PM6 and the ninth PMOS transistor PM9 are turned off, the current of the differential pair of the error amplifier is reduced, and thus the power consumption of the whole low dropout linear regulator circuit is reduced.

The third switching circuit includes an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM 10. The third switching circuit is used as an output branch circuit, and influences the voltage condition of the output end VOUT of the circuit according to the gate voltage of the first NMOS transistor NM 1. The eighth NMOS transistor NM8 is connected to the second control signal deep b as a gate of the switching transistor, the source of the eighth NMOS transistor NM8 is connected to the common terminal of the load current source circuit of the error amplifier, preferably, the source of the eighth NMOS transistor NM8 is connected to the common terminal of the gates of the first and second NMOS transistors NM1 and NM2, and the drain of the eighth NMOS transistor NM8 is connected to the gate of the tenth NMOS transistor NM 10. A gate of the ninth NMOS transistor NM9 is connected to the first control signal Deep, a drain of the ninth NMOS transistor NM9 is connected to the gate of the tenth NMOS transistor NM10, and a source of the ninth NMOS transistor NM9 is grounded. The grid electrode of the tenth NMOS transistor NM10 is connected to the drain electrode of the eighth NMOS transistor NM8 and the drain electrode of the ninth NMOS transistor NM9, respectively, the drain electrode of the tenth NMOS transistor NM10 is connected to the output terminal VOUT of the circuit, and the source electrode of the tenth NMOS transistor NM10 is grounded.

When the load circuit is in the operating mode in the normal operating state, the first control signal Deep is set to the low level (Deep ═ 0), the second control signal Deep is set to the high level (Deep ═ 1), a large bias current is output through the output end of the bias circuit, the current flowing through the load current source circuit of the error amplifier is increased, and the voltage of the output end VOUT of the circuit can be further adjusted through the tenth NMOS tube NM 10. When the load circuit is in the standby mode in the standby state, the first control signal Deep is set to the high level (Deep ═ 1), the second control signal Deep is set to the low level (Deep ═ 0), the eighth NMOS transistor NM8 is turned off, the ninth NMOS transistor NM9 is turned on to pull down the gate of the tenth NMOS transistor NM10 to the ground, and the tenth NMOS transistor NM10 is turned off to further reduce the current flowing through the output terminal VOUT.

Referring to fig. 2, one end of the first capacitor C1 of the present invention is connected to the output end of the bias circuit, and therefore, the gates of the PMOS transistor PM0, the fourth PMOS transistor PM4, and the ninth PMOS transistor PM9, which are directly or indirectly connected to the fifth PMOS transistor PM5, are all affected by the first capacitor C1, as shown in fig. 2, the load transient enhancement principle of the present invention is specifically as follows:

when the load circuit is in a working mode under a normal working state, and the load current is rapidly reduced, the output voltage of the output end VOUT of the circuit is increased, the voltage of the voltage a of the first capacitor C1 is increased, and the voltage of the voltage b of the first capacitor C1 is also increased because the voltages of the two sides of the capacitor cannot be suddenly changed, so that the gate voltages of the fifth PMOS transistor PM5, the PMOS transistor PM0, the fourth PMOS transistor PM4 and the ninth PMOS transistor PM9 are increased, thereby directly reducing the magnitude of the charging current of the power supply to the gate of the series adjustment power transistor MPOWER, enabling the third PMOS transistor PM3 to pull down the gate voltage of the series adjustment power transistor MPOWER more rapidly, reducing the current flowing through the series adjustment power transistor MPOWER, and inhibiting the increase of the output voltage VOUT of the circuit. The VFB voltage connected to the inverting input terminal of the error amplifier increases, and the differential voltage is generated in the output tube of the differential pair of the error amplifier, so that the gate potential of the first NMOS transistor NM1 increases, because the gate of the tenth NMOS transistor NM10 is connected to the gate of the first NMOS transistor NM1 as a switching tube through the eighth NMOS transistor NM8, the gate voltage of the tenth NMOS transistor NM10 also increases, thereby increasing the discharging current of the output branch to the circuit output terminal VOUT, and further suppressing the increase of the circuit output terminal VOUT.

When the load current increases rapidly, the output voltage decreases, the gate-source voltage of the series regulation power tube MPOWER increases, the current flowing through the series regulation power tube MPOWER increases, the decrease of the output voltage of the circuit output end VOUT is suppressed, meanwhile, the voltage at the terminal a of the first capacitor C1 decreases, since the voltage at two sides of the capacitor cannot change suddenly, the voltage at the terminal b of the first capacitor C1 also decreases, the decrease of the circuit output end VOUT is transmitted to the gates of the fifth PMOS tube PM5, the PMOS tube PM0, the fourth PMOS tube PM4 and the ninth PMOS tube PM9 through the first capacitor C1, so that the dynamic current flowing through the gates of the fifth PMOS tube PM5, the PMOS tube PM0, the fourth PMOS tube PM4 and the ninth PMOS tube PM9 dynamically decreases, the dynamic current flowing through the gates of the fifth PMOS tube PM5, the PMOS tube PM0, the fourth PMOS tube PM4 and the ninth PMOS tube PM9 increases, the speed of the gate series regulation power tube MPOWER is directly increased, and the gate charging voltage of the series regulation power tube MPOWER increases, therefore, the current flowing through the series-regulated power tube MPOWER is increased, and the reduction of the output voltage of the output end VOUT of the circuit is further inhibited.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A low dropout linear regulator circuit with low power consumption and fast transient response, comprising:

an error amplifier;

the circuit is characterized in that the homodromous input end of the error amplifier is connected with a reference voltage, and the reverse input end of the error amplifier is connected with the feedback end;

further comprising:

2. The low power consumption fast transient response low dropout linear regulator circuit of claim 1, further comprising a load transient response enhancement circuit, said load transient response enhancement circuit comprising:

3. The low power consumption fast transient response low dropout linear regulator circuit according to claim 1, wherein said error amplifier comprises:

4. The low power consumption fast transient response low dropout linear regulator circuit according to claim 3, further comprising:

5. The low power consumption fast transient response low dropout regulator circuit according to claim 1, wherein said error amplifier is connected to the gate of said series regulated power transistor through a source follower buffer circuit.

6. The low power consumption fast transient response low dropout linear regulator circuit according to claim 5, wherein said source follower buffer circuit comprises:

7. The low power consumption fast transient response low dropout linear regulator circuit according to claim 1, wherein said bias circuit comprises:

8. The low power consumption fast transient response low dropout linear regulator circuit according to claim 7, further comprising:

the mode switching circuit is provided with a first switching circuit, the output end of the first switching circuit is connected with the control end of the bias circuit, and the first switching circuit controls the working state of the bias circuit;

the first switching circuit includes:

9. A low power consumption fast transient response low dropout linear regulator circuit according to any one of claims 1 to 8, further comprising:

a mode switching circuit having a second switching circuit;

the second switching circuit includes:

10. A low power consumption fast transient response low dropout linear regulator circuit according to any one of claims 1 to 8, further comprising:

a mode switching circuit having a third switching circuit;

the third switching circuit includes: