CN116126080A

CN116126080A - Source follower circuit and low dropout linear voltage regulator

Info

Publication number: CN116126080A
Application number: CN202310412036.XA
Authority: CN
Inventors: 甘留军; 曾梓琪; 邓兰青; 丁颜玉
Original assignee: Nexwise Intelligence China Ltd
Current assignee: Nexwise Intelligence China Ltd
Priority date: 2023-04-18
Filing date: 2023-04-18
Publication date: 2023-05-16
Anticipated expiration: 2043-04-18
Also published as: CN116126080B

Abstract

The invention provides a source follower circuit and a low dropout linear voltage regulator, which relate to the technical field of integrated circuits, wherein the source follower circuit comprises: the power supply voltage detection circuit is used for comparing the divided power supply voltage with the reference voltage, outputting a first control signal when the divided voltage is smaller than the reference voltage and outputting a second control signal when the divided voltage is larger than the reference voltage; the first isolation circuit is respectively connected with the first source follower circuit and the second source follower circuit and is used for conducting the following input end with the first source follower circuit under the control of a first control signal and conducting the following input end with the second source follower circuit under the control of a second control signal so as to perform circuit switching; the voltage withstand value of the input field effect transistor and the output field effect transistor of the first source follower circuit is smaller than that of the second source follower circuit. The technical scheme provided by the invention enables the lowest supply voltage of the source follower circuit to be downwards moved, and can be compatible with a wider supply voltage range.

Description

Source follower circuit and low dropout linear voltage regulator

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a source follower circuit and a low dropout linear voltage regulator.

Background

The low dropout linear regulator (Low Dropout Regulator, LDO) is a low-power-consumption micro system-on-a-chip (SoC), plays an important role in power supply voltage regulation, and is widely applied to power supply. With the continuous development of chip design towards low power consumption, the voltage of the power supply of the chip is also continuously reduced, but for the LDO system, a wider working range is pursued, including a relatively wide power supply voltage range and a load range.

The LDO system uses a source follower to carry out voltage following and impedance transformation between the error amplifier and the output stage power tube, so that isolation between the error amplifier and the output stage power tube is realized. For LDO systems of high frequency bandwidth, source followers can be designed using field effect transistors. In order to meet the requirement of the LDO system compatible with a wider power supply voltage range, devices in a circuit are not damaged, the circuit needs to use a field effect tube with a high withstand voltage value, but the field effect tube with the high withstand voltage value can bring high threshold voltage, so that the voltage difference between the input and the output of the source follower is increased, and the lowest power supply voltage in the LDO system is raised and is difficult to drop.

Disclosure of Invention

The invention provides a source follower circuit and a low dropout linear voltage regulator, which are used for solving the problem that the minimum supply voltage of an LDO system is difficult to drop in the prior art.

The invention provides a source follower circuit which is applied to a low dropout linear voltage regulator, wherein the source follower circuit comprises a power supply input end, a reference voltage end, a following input end, a following output end, a power supply voltage detection circuit, a first isolation circuit, a first source follower circuit and a second source follower circuit;

the power supply voltage detection circuit is used for dividing the power supply voltage received by the power supply input end, comparing the obtained divided voltage with the reference voltage input by the reference voltage end, outputting a first control signal when the divided voltage is smaller than the reference voltage, and outputting a second control signal when the divided voltage is larger than the reference voltage;

the first isolation circuit comprises a first output end and a second output end, the first output end is connected with the input end of the first source follower circuit, and the second output end is connected with the input end of the second source follower circuit; the first isolation circuit is used for conducting the following input end and the first source follower circuit and disconnecting the following input end and the second source follower circuit under the control of the first control signal, and conducting the following input end and the second source follower circuit and disconnecting the following input end and the first source follower circuit under the control of the second control signal;

The first source electrode follower circuit is used for carrying out first voltage follower on the voltage signal received by the follower input end and outputting first follower voltage through the follower output end;

the second source follower circuit is used for carrying out second voltage following on the voltage signal received by the following input end and outputting second following voltage through the following output end;

the voltage withstanding values of the first input field effect transistor and the first output field effect transistor of the first source electrode follower circuit are smaller than those of the second input field effect transistor and the second output field effect transistor of the second source electrode follower circuit.

According to the source follower circuit provided by the invention, the power supply voltage detection circuit comprises a voltage division circuit, a switch circuit, a comparator and a hysteresis control circuit;

the voltage division input end of the voltage division circuit is connected with the power input end, and the voltage division output end of the voltage division circuit is connected with the non-inverting input end of the comparator;

the inverting input end of the comparator is connected with the reference voltage end, and the comparison output end of the comparator is connected with the input end of the hysteresis control circuit;

the output end of the switching circuit is connected with the voltage division control end of the voltage division circuit, and the control end of the switching circuit is connected with the hysteresis control end of the hysteresis control circuit;

The comparator is used for comparing the divided voltage output by the voltage dividing circuit with the reference voltage, inputting a first voltage signal to the hysteresis control circuit when the divided voltage is smaller than the reference voltage, and inputting a second voltage signal to the hysteresis control circuit when the divided voltage is larger than the reference voltage;

the hysteresis control circuit is used for outputting the first control signal through the output end of the hysteresis control circuit when receiving the first voltage signal, controlling the switch circuit to be turned on through the hysteresis control end of the hysteresis control circuit, outputting the second control signal through the output end of the hysteresis control circuit when receiving the second voltage signal, and controlling the switch circuit to be turned off through the hysteresis control end of the hysteresis control circuit;

the switching circuit is used for controlling the voltage division ratio of the voltage division circuit according to on or off;

the voltage dividing circuit is used for dividing the power supply voltage according to the voltage dividing ratio and inputting the divided voltage into the non-inverting input end of the comparator.

According to the source follower circuit provided by the invention, the voltage dividing circuit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor;

The first voltage dividing resistor, the second voltage dividing resistor and the third voltage dividing resistor are connected in series between the voltage dividing input end and the ground;

the first series node of the first voltage dividing resistor and the second voltage dividing resistor is used as the voltage dividing output end to be connected with the non-inverting input end of the comparator;

the second series node of the second voltage dividing resistor and the third voltage dividing resistor is used as the voltage dividing control end to be connected with the output end of the switch circuit;

the switch circuit is used for grounding the second series node when being conducted and disconnecting the second series node from the ground when being disconnected.

According to the source follower circuit provided by the invention, the output end of the power supply voltage detection circuit comprises a first sub-output end and a second sub-output end; the hysteresis control circuit comprises a first inverter and a second inverter;

the input end of the first inverter is connected with the comparison output end of the comparator, and the output end of the first inverter is respectively connected with the input end of the second inverter and the first sub-output end and serves as the hysteresis control end; the first inverter is used for outputting the voltage signal output by the comparison output end of the comparator in an inverting way;

The output end of the second inverter is connected with the second sub-output end, and the second inverter is used for outputting the output signal of the first inverter in an inverted mode;

the first control signal comprises a high-level signal output by the first sub-output end and a low-level signal output by the second sub-output end; the second control signal includes a low level signal output from the first sub-output terminal and a high level signal output from the second sub-output terminal.

According to the source follower circuit provided by the invention, the first isolation circuit comprises a first isolation sub-circuit and a second isolation sub-circuit;

the first input end of the first isolation sub-circuit is connected with the following input end, and the first controlled end of the first isolation sub-circuit is connected with the output end of the power supply voltage detection circuit; the first isolation sub-circuit is used for conducting the following input end and the first source following circuit under the control of the first control signal, and disconnecting the following input end and the first source following circuit under the control of the second control signal;

the second input end of the second isolation sub-circuit is connected with the following input end, and the second controlled end of the second isolation sub-circuit is connected with the output end of the power supply voltage detection circuit; the second isolation sub-circuit is used for disconnecting the following input end from the second source electrode following circuit under the control of the first control signal, and conducting the following input end from the second source electrode following circuit under the control of the second control signal.

The source follower circuit provided by the invention further comprises a second isolation circuit, a third isolation circuit and a fourth isolation circuit;

the second isolation circuit is connected between the power input end and the first end of the first source follower circuit; the second isolation circuit is used for conducting the power supply input end and the first source follower circuit under the control of the first control signal, and disconnecting the power supply input end and the first source follower circuit under the control of the second control signal;

the third isolation circuit is connected between the output end of the first source follower circuit and the follower output end; the third isolation circuit is used for conducting the first source follower circuit and the follower output end under the control of the first control signal, and disconnecting the first source follower circuit and the follower output end under the control of the second control signal;

the second end of the first source follower circuit and the third end of the first source follower circuit are connected with ground through the fourth isolation circuit; the fourth isolation circuit is used for conducting the first source follower circuit with the ground under the control of the first control signal, and disconnecting the first source follower circuit from the ground under the control of the second control signal.

According to the source follower circuit provided by the invention, the output end of the power supply voltage detection circuit comprises a first sub-output end and a second sub-output end, and the first control signal comprises a high-level signal output by the first sub-output end and a low-level signal output by the second sub-output end; the second control signal comprises a low-level signal output by the first sub-output end and a high-level signal output by the second sub-output end;

the second isolation circuit comprises a first N-channel field effect transistor and a first P-channel field effect transistor, wherein the grid electrode of the first N-channel field effect transistor is connected with the first sub-output end, and the grid electrode of the first P-channel field effect transistor is connected with the second sub-output end; the source electrode of the first N-channel field effect transistor and the drain electrode of the first P-channel field effect transistor are connected with the first end of the first source follower circuit; the drain electrode of the first N-channel field effect transistor and the source electrode of the first P-channel field effect transistor are connected with the power input end;

the third isolation circuit comprises a second N-channel field effect transistor and a second P-channel field effect transistor, wherein the grid electrode of the second N-channel field effect transistor is connected with the first sub-output end, and the grid electrode of the second P-channel field effect transistor is connected with the second sub-output end; the source electrode of the second N-channel field effect transistor and the drain electrode of the second P-channel field effect transistor are connected with the following output end; the drain electrode of the second N-channel field effect transistor and the source electrode of the second P-channel field effect transistor are connected with the output end of the first source follower circuit;

The fourth isolation circuit comprises a third N-channel field effect transistor and a fourth N-channel field effect transistor, wherein the drain electrode of the third N-channel field effect transistor is connected with the second end of the first source follower circuit, the drain electrode of the fourth N-channel field effect transistor is connected with the third end of the first source follower circuit, the source electrode of the third N-channel field effect transistor and the source electrode of the fourth N-channel field effect transistor are respectively connected with the ground, and the grid electrode of the third N-channel field effect transistor and the grid electrode of the fourth N-channel field effect transistor are respectively connected with the first sub-output end.

The source follower circuit provided by the invention further comprises a fifth isolation circuit, a sixth isolation circuit and a seventh isolation circuit;

the fifth isolation circuit is connected between the power input end and the first end of the second source follower circuit, and is used for disconnecting the power input end from the second source follower circuit under the control of the first control signal and conducting the power input end from the second source follower circuit under the control of the second control signal;

the sixth isolation circuit is connected between the output end of the second source follower circuit and the following output end, and is used for disconnecting the second source follower circuit from the following output end under the control of the first control signal and conducting the second source follower circuit from the following output end under the control of the second control signal;

The second end of the second source follower circuit and the third end of the second source follower circuit are connected with the ground through the seventh isolation circuit, and the seventh isolation circuit is used for disconnecting the second source follower circuit from the ground under the control of the first control signal and conducting the second source follower circuit with the ground under the control of the second control signal.

According to the source follower circuit provided by the invention, the circuit structure of the first source follower circuit is the same as that of the second source follower circuit.

The invention also provides a low dropout linear voltage regulator, which comprises an error amplifier, an output stage power tube circuit and any one of the source follower circuits;

the following input end of the source follower circuit is connected with the output end of the error amplifier, and the following output end of the source follower circuit is connected with the input end of the output stage power tube circuit.

The source follower circuit and the low dropout linear voltage regulator provided by the invention divide the power supply voltage received by the power supply input end through the power supply voltage detection circuit, and compare the divided voltage obtained by dividing with the reference voltage input by the reference voltage end so as to detect the power supply voltage; the power supply voltage detection circuit outputs a first control signal under the condition that the divided voltage is smaller than the reference voltage, the first isolation circuit is controlled by the first control signal to conduct the following input end with the first source following circuit and disconnect the following input end from the second source following circuit, at this time, the first voltage following can be carried out on the voltage signal received by the following input end through the first source following circuit, and the first following voltage is output through the following output end; the power supply voltage detection circuit outputs a second control signal under the condition that the divided voltage is larger than the reference voltage, the first isolation circuit is controlled by the second control signal to conduct the following input end with the second source following circuit and disconnect the following input end from the first source following circuit, at this time, the voltage signal received by the following input end can be subjected to second voltage following through the second source following circuit, and the second following voltage is output through the following output end. The voltage withstand values of the first input field effect transistor and the first output field effect transistor of the first source follower circuit are smaller than those of the second input field effect transistor and the second output field effect transistor of the second source follower circuit, so that the first source follower circuit with a low voltage withstand value or the second source follower circuit with a high voltage withstand value can be automatically selected to carry out voltage following according to detection output of the power supply voltage detection circuit to the power supply voltage, the second source follower circuit with the high voltage withstand value can meet the requirement of higher power supply voltage, the first source follower circuit with the low voltage withstand value can enable small pressure difference to exist between the input and the output of the source follower circuit, the requirement on the lowest power supply voltage is reduced, the lowest power supply voltage of the whole source follower circuit can move downwards, and the lowest power supply voltage of a low-voltage differential linear voltage stabilizer applying the source follower circuit can move downwards, and can be compatible with a wider power supply voltage range.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a source follower circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a power supply voltage detection circuit in a source follower circuit according to an embodiment of the present invention;

FIG. 3 is a second schematic diagram of a power supply voltage detection circuit in a source follower circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a first isolation circuit in a source follower circuit according to an embodiment of the present invention;

FIG. 5 is a second schematic diagram of a source follower circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a first source follower circuit connection isolation circuit in a source follower circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a second source follower circuit connection isolation circuit in a source follower circuit according to an embodiment of the present invention;

Fig. 8 is a schematic diagram of a low dropout linear regulator according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, in the present invention, the numbers of the described components or objects, such as "first", "second", etc., are only used to distinguish the described components or objects, and do not have any sequence or technical meaning.

The source follower circuit of the present invention is described below with reference to fig. 1 to 7.

Fig. 1 schematically illustrates one of the schematic configurations of a source follower circuit according to an embodiment of the present invention, and referring to fig. 1, the source follower circuit may include a power supply input terminal VIN, a reference voltage terminal VREF, a follower input terminal IN, a follower output terminal OUT, a power supply voltage detection circuit 110, a first isolation circuit 120, a first source follower circuit 130, and a second source follower circuit 140.

The power supply voltage detection circuit 110 is configured to divide a power supply voltage received at the power supply input terminal VIN, compare the obtained divided voltage with a reference voltage input at the reference voltage terminal VREF, output a first control signal to the first isolation circuit 120 through the output terminal a thereof when the divided voltage is smaller than the reference voltage, and output a second control signal to the first isolation circuit 120 through the output terminal a thereof when the divided voltage is greater than the reference voltage. In this way, by comparing the divided voltage of the power supply voltage with the reference voltage by the power supply voltage detection circuit 110, it is possible to detect the change in the power supply voltage and the level of the voltage value, for example, consider the power supply voltage as a low voltage when the divided voltage is smaller than the reference voltage, and consider the power supply voltage as a high voltage when the divided voltage is larger than the reference voltage.

The first isolation circuit 120 includes a first output terminal B1 and a second output terminal B2, the first output terminal B1 is connected to the input terminal of the first source follower circuit 130, and the second output terminal B2 is connected to the input terminal of the second source follower circuit 140. The first isolation circuit 120 is configured to conduct the follower input terminal IN with the first source follower circuit 130 and disconnect the follower input terminal IN from the second source follower circuit 140 under the control of the first control signal, and at this time, the voltage signal received by the follower input terminal IN is input to the first source follower circuit 130; the first source follower circuit 130 is configured to perform a first voltage follower on the voltage signal received at the follower input terminal IN, and output a first follower voltage through the follower output terminal OUT. The first isolation circuit 120 is further configured to conduct the follower input terminal IN with the second source follower circuit 140 and disconnect the follower input terminal IN from the first source follower circuit 130 under the control of the second control signal, and at this time, the voltage signal received by the follower input terminal IN is input to the second source follower circuit 140; the second source follower circuit 140 is configured to perform a second voltage follower on the voltage signal received at the follower input terminal IN, and output a second follower voltage through the follower output terminal OUT. IN this way, the voltage signal received at the follower input terminal IN can be automatically selected to be followed by the first source follower circuit 130 or the second source follower circuit 140 according to the change of the power supply voltage.

Among them, the first source follower circuit 130 and the second source follower circuit 140 are circuits in which field effect transistors are used as impedance conversion and voltage follower, and can convert high input impedance into low output impedance. The first source follower circuit 130 may include a first input field effect transistor and a first output field effect transistor, and the second source follower circuit 140 may include a second input field effect transistor and a second output field effect transistor. Illustratively, the first source follower circuit 130 and the second source follower circuit 140 may employ super source follower structures.

In the embodiment of the present invention, the withstand voltage values of the first input field effect transistor and the first output field effect transistor of the first source follower circuit 130 are smaller than those of the second input field effect transistor and the second output field effect transistor of the second source follower circuit 140. In this way, when the divided voltage of the power supply voltage is greater than the reference voltage, the second source follower circuit 140 having a higher withstand voltage value can be gated to meet the requirement of a higher power supply voltage; when the divided voltage of the power supply voltage is smaller than the reference voltage, the first source follower circuit 130 with small withstand voltage is switched to the first source follower circuit, and the threshold voltage of the input field effect transistor is reduced, so that the lowest power supply voltage of the whole source follower circuit can be shifted downwards.

The source follower circuit provided by the embodiment of the invention divides the power supply voltage received by the power supply input end through the power supply voltage detection circuit, and compares the divided voltage with the reference voltage input by the reference voltage end so as to detect the power supply voltage; the power supply voltage detection circuit outputs a first control signal under the condition that the divided voltage is smaller than the reference voltage, the first isolation circuit is controlled by the first control signal to conduct the following input end with the first source following circuit and disconnect the following input end from the second source following circuit, at this time, the first voltage following can be carried out on the voltage signal received by the following input end through the first source following circuit, and the first following voltage is output through the following output end; the power supply voltage detection circuit outputs a second control signal under the condition that the divided voltage is larger than the reference voltage, the first isolation circuit is controlled by the second control signal to conduct the following input end with the second source following circuit and disconnect the following input end from the first source following circuit, at this time, the voltage signal received by the following input end can be subjected to second voltage following through the second source following circuit, and the second following voltage is output through the following output end. The voltage withstand values of the first input field effect transistor and the first output field effect transistor of the first source follower circuit are smaller than those of the second input field effect transistor and the second output field effect transistor of the second source follower circuit, so that the first source follower circuit with a low voltage withstand value or the second source follower circuit with a high voltage withstand value can be automatically selected to carry out voltage following according to detection output of the power supply voltage detection circuit to the power supply voltage, the second source follower circuit with the high voltage withstand value can meet the requirement of higher power supply voltage, the first source follower circuit with the low voltage withstand value can enable small pressure difference to exist between the input and the output of the source follower circuit, the requirement on the lowest power supply voltage is reduced, the lowest power supply voltage of the whole source follower circuit can move downwards, and the lowest power supply voltage of a low-voltage differential linear voltage stabilizer applying the source follower circuit can move downwards, and can be compatible with a wider power supply voltage range.

Based on the source follower circuit of the corresponding embodiment of fig. 1, in an exemplary embodiment, fig. 2 schematically illustrates one of the structure diagrams of the power supply voltage detection circuit in the source follower circuit according to the embodiment of the present invention, and referring to fig. 2, the power supply voltage detection circuit 110 may include a voltage division circuit 111, a switching circuit 112, a comparator 113, and a hysteresis control circuit 114. The voltage division input end of the voltage division circuit 111 is connected with the power supply input end VIN, and the voltage division output end of the voltage division circuit 111 is connected with the non-inverting input end of the comparator 113; an inverting input terminal of the comparator 113 is connected with a reference voltage terminal VREF, and a comparison output terminal of the comparator 113 is connected with an input terminal of the hysteresis control circuit 114; an output end of the switch circuit 112 is connected with a voltage division control end of the voltage division circuit 111, a control end of the switch circuit 112 is connected with a hysteresis control end CL of the hysteresis control circuit 114, and a grounding end of the switch circuit 112 is connected with ground; the output of the hysteresis control circuit 114 is used as the output a of the supply voltage detection circuit 110.

The comparator 113 compares the divided voltage output from the voltage dividing circuit 111 with a reference voltage, and inputs a first voltage signal to the hysteresis control circuit 114 when the divided voltage is smaller than the reference voltage, and inputs a second voltage signal to the hysteresis control circuit 114 when the divided voltage is larger than the reference voltage.

The hysteresis control circuit 114 is configured to output a first control signal through an output terminal of the hysteresis control circuit 114 when receiving a first voltage signal, and control the switch circuit 112 to be turned on through a hysteresis control terminal CL of the hysteresis control circuit 114, and output a second control signal through an output terminal of the hysteresis control circuit 114 when receiving a second voltage signal, and control the switch circuit 112 to be turned off through the hysteresis control terminal CL of the hysteresis control circuit 114.

The switch circuit 112 is used to control the voltage division ratio of the voltage division circuit 111 according to on or off.

The voltage dividing circuit 111 is configured to divide the power supply voltage input at the power supply input terminal VIN according to the voltage dividing ratio, and input the divided voltage to the non-inverting input terminal of the comparator 113.

In an exemplary embodiment, fig. 3 illustrates a second schematic diagram of a power supply voltage detection circuit in a source follower circuit according to an embodiment of the present invention, which illustrates an alternative implementation of the power supply voltage detection circuit 110. Referring to fig. 3, in the power supply voltage detection circuit 110, the voltage division circuit 111 includes a first voltage division resistor R1, a second voltage division resistor R2, and a third voltage division resistor R3. The first voltage dividing resistor R1, the second voltage dividing resistor R2 and the third voltage dividing resistor R3 are connected in series between the voltage dividing input terminal and the ground, the first series node a of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is used as a voltage dividing output terminal to be connected with the non-inverting input terminal of the comparator 113, and the second series node b of the second voltage dividing resistor R2 and the third voltage dividing resistor R3 is used as a voltage dividing control terminal to be connected with the output terminal of the switch circuit 112.

The switch circuit 112 is configured to connect the second series node b to ground when turned on, and disconnect the second series node b from ground when turned off. When the switch circuit 112 is turned on, the third voltage dividing resistor R3 is shorted, and the second voltage dividing resistor R2 and the first voltage dividing resistor R1 divide voltage; when the switch circuit 112 is turned off, the third voltage dividing resistor R3 is connected to the circuit to participate in voltage division, and at this time, the sum of the second voltage dividing resistor R2 and the second voltage dividing resistor R2 is divided by the first voltage dividing resistor R1. Thus, by controlling the on/off of the switching circuit 112, the voltage division ratio of the voltage dividing circuit 111 can be controlled.

Illustratively, the switching circuit 112 may include a first field effect transistor NM11, as shown in fig. 3, and the first field effect transistor NM11 may be an N-channel enhancement type field effect transistor, such as an N-channel metal-oxide semiconductor field effect transistor (MOSFET).

Illustratively, as shown in fig. 3, the output terminal a of the power supply voltage detection circuit 110 includes a first sub-output terminal A1 and a second sub-output terminal A2, and the hysteresis control circuit 114 includes a first inverter D1 and a second inverter D2. The input terminal of the first inverter D1 is connected to the output terminal of the comparator 113, the output terminal of the first inverter D1 is connected to the input terminal of the second inverter D2 and the first sub-output terminal A1, respectively, and is connected to the control terminal of the switching circuit 112 as the hysteresis control terminal CL, and the output terminal of the second inverter D2 is connected to the second sub-output terminal A2.

The first inverter D1 is configured to invert and output the voltage signal output from the comparison output terminal of the comparator 113. The second inverter D2 is configured to invert and output the output signal of the first inverter D1. The second inverter D2 is configured to invert and output the output signal of the first inverter D1.

Based on this, in combination with fig. 1 or 2, the first control signal output from the output terminal a of the power supply voltage detection circuit 110 includes a high level signal output from the first sub-output terminal A1 and a low level signal output from the second sub-output terminal A2; the second control signal output from the output terminal a of the power voltage detection circuit 110 includes a low level signal output from the first sub-output terminal A1 and a high level signal output from the second sub-output terminal A2. That is, in the case where the divided voltage output from the first series node a is less than the reference voltage of the reference voltage terminal VREF, the first sub-output terminal A1 outputs a high level signal and the second sub-output terminal A2 outputs a low level signal; in the case where the divided voltage outputted from the first series node a is greater than the reference voltage of the reference voltage terminal VREF, the first sub-output terminal A1 outputs a low level signal and the second sub-output terminal A2 outputs a high level signal.

For example, as shown in fig. 3, the comparator 113 may include N-channel field effect transistors NM31 and NM32, and P-channel field effect transistors PM31, PM32, and PM33, and the gate of the P-channel field effect transistor PM33 serves as a bias voltage terminal BI0 of the comparator 113, through which bias voltage terminal BI0 the bias voltage is received. It will be appreciated that fig. 3 illustrates an alternative embodiment of the comparator 113 and is not intended to be a unique limitation of the present invention.

According to the power supply voltage detection circuit shown in fig. 3, after the power supply voltage input by the power supply input terminal VIN is divided by the voltage dividing circuit 111, the output divided voltage is compared with the reference voltage of the reference voltage terminal VREF, and the first control signal or the second control signal is output according to the comparison result. Specifically, when the power supply voltage VDD input at the power supply input terminal VIN is smaller, the reference voltage VREF at the reference voltage terminal VREF is greater than the divided voltage output at the divided output terminal a of the voltage dividing circuit 111, and at this time, the first voltage signal output by the comparator 113 is a low level signal, and after the low level signal is operated by the two inverters of the hysteresis control circuit 114, the first sub-output terminal A1 outputs a high level signal, the second sub-output terminal A2 outputs a low level signal, and the two level signals output by the first sub-output terminal A1 and the second sub-output terminal A2 can control the on state of the first isolation circuit 120. Meanwhile, the hysteresis control terminal CL of the hysteresis control circuit 114 also outputs the same high-level signal as the first sub-output terminal A1, and can control the first field effect transistor NM11 to be turned on, and the third voltage dividing resistor R3 is shorted, and at this time, the voltage dividing ratio of the voltage dividing circuit 111 can be expressed as R ₂ /（R ₁ +R ₂ ) The voltage division ratio represents the ratio of the voltage input from the non-inverting input terminal of the comparator 113 to the power supply voltage VDD, and the voltage input from the non-inverting input terminal of the comparator 113 is VDD ₂ /（R ₁ +R ₂ ) Wherein R is ₁ Represents the resistance value of the first voltage dividing resistor R1, R ₂ The resistance of the second shunt resistor R2 is shown.

With the rise of the power supply voltage VDD, vdd×r can be made at a certain moment ₂ /（R ₁ +R ₂ ）>Vref, the second voltage signal outputted from the comparator 113 is a high level signal, the high level signal is calculated by two inverters of the hysteresis control circuit 114, the first sub-output terminal A1 outputs a low level signal, the second sub-output terminal A2 outputs a high level signal, i.e. the two level signals outputted from the first sub-output terminal A1 and the second sub-output terminal A2 are turned over, and the turning over makes the first isolation circuit 120 conductiveThe state changes, and the switching from the first source follower circuit 130 to the second source follower circuit 140 is completed. At the same time, the hysteresis control terminal CL of the hysteresis control circuit 114 also outputs the same low-level signal as the first sub-output terminal A1, and can control the first fet NM11 to be turned off, and the third voltage dividing resistor R3 participates in the voltage division, and at this time, the voltage dividing ratio of the voltage dividing circuit 111 is changed to (R ₂ +R ₃ ）/（R ₁ +R ₂ +R ₃ ) This value is greater than R ₂ /（R ₁ +R ₂ ) The voltage input from the non-inverting input terminal of the comparator 113 is changed to VDD (R ₂ +R ₃ ）/（R ₁ +R ₂ +R ₃ ) Wherein R is ₃ The resistance of the third voltage dividing resistor R3 is shown.

Therefore, the voltage at the non-inverting input terminal of the comparator 113 rises to Vref and then immediately jumps to a higher value, and the level signals at the first sub-output terminal A1 and the second sub-output terminal A2 are inverted rapidly in positive feedback, which means that the power supply voltage VDD needs to fall to satisfy the relationship VDD (R) ₂ +R ₃ ）/(R ₁ +R ₂ +R ₃ ) When Vref, the level signals output by the first sub-output terminal A1 and the second sub-output terminal A2 can be inverted again, which requires a lower power supply voltage VDD.

Based on this, the inversion points of the first control signal and the second control signal outputted from the power supply voltage detection circuit are set to be equal to or smaller than the first condition VDD (R ₂ +R ₃ ）/(R ₁ +R ₂ +R ₃ ) =vref and fulfils the second condition vdd×r ₂ /（R ₁ +R ₂ ) Switching between Vref forms a hysteresis space, which can prevent the first source follower circuit 130 and the second source follower circuit 140 from switching back and forth due to the fluctuation of the power supply voltage VDD, thereby playing a role in jitter prevention.

Based on the source follower circuit of the corresponding embodiment of fig. 1, in an exemplary embodiment, fig. 4 schematically illustrates a structure of a first isolation circuit, and referring to fig. 4, the first isolation circuit 120 includes a first isolation sub-circuit 121 and a second isolation sub-circuit 122. A first input terminal of the first isolation sub-circuit 121 is connected to the following input terminal IN, and a first controlled terminal of the first isolation sub-circuit 121 is connected to the output terminal a of the power supply voltage detection circuit 110; a second input terminal of the second isolation sub-circuit 122 is connected to the following input terminal IN, and a second controlled terminal of the second isolation sub-circuit 122 is connected to the output terminal a of the power supply voltage detection circuit 110. The output terminal of the first isolation sub-circuit 121 is connected to the first source follower circuit 130 as a first output terminal B1 of the first isolation circuit 120, and the output terminal of the second isolation sub-circuit 122 is connected to the second source follower circuit 140 as a second output terminal B2 of the first isolation circuit 120.

The first isolation sub-circuit 121 is configured to conduct the follower input terminal IN with the first source follower circuit 130 under the control of the first control signal output by the output terminal a of the power supply voltage detection circuit 110, and disconnect the follower input terminal IN from the first source follower circuit 130 under the control of the second control signal output by the output terminal a of the power supply voltage detection circuit 110.

The second isolation sub-circuit 122 is configured to disconnect the follower input terminal IN from the second source follower circuit 140 under the control of the first control signal output from the output terminal a of the power supply voltage detection circuit 110, and to conduct the follower input terminal IN from the second source follower circuit 140 under the control of the second control signal.

In conjunction with the power supply voltage detection circuit 110 shown in fig. 3, the output terminal a thereof may include a first sub-output terminal A1 and a second sub-output terminal A2, it being understood that, in the first isolation circuit 120 illustrated in fig. 4, the first controlled terminal of the first isolation sub-circuit 121 may include a first sub-controlled terminal connected to the first sub-output terminal A1 and a second sub-controlled terminal connected to the second sub-output terminal A2, through which the control signal output from the power supply voltage detection circuit 110 is received. Similarly, the second controlled terminal of the second isolation sub-circuit 122 may include a third sub-controlled terminal connected to the first sub-output terminal A1 and a fourth sub-controlled terminal connected to the second sub-output terminal A2, and receives the control signal output from the supply voltage detection circuit 110 through the two sub-controlled terminals.

Based on the source follower circuits of the above embodiments, fig. 5 schematically illustrates a second schematic diagram of the source follower circuit according to the embodiment of the present invention, and referring to fig. 5, the source follower circuit according to the embodiment of the present invention may further include a second isolation circuit 510, a third isolation circuit 520, and a fourth isolation circuit 530.

The second isolation circuit 510 is connected between the power input terminal VIN and the first terminal of the first source follower circuit 130, and the second isolation circuit 510 is configured to turn on the power input terminal VIN and the first source follower circuit 130 under the control of the first control signal output by the first isolation circuit 120, and turn off the power input terminal VIN and the first source follower circuit 130 under the control of the second control signal output by the first isolation circuit 120.

The third isolation circuit 520 is connected between the output terminal of the first source follower circuit 130 and the follower output terminal OUT, and the third isolation circuit 520 is configured to turn on the first source follower circuit 130 and the follower output terminal OUT under the control of the first control signal output by the first isolation circuit 120, and turn off the first source follower circuit 130 and the follower output terminal OUT under the control of the second control signal output by the first isolation circuit 120.

The second end of the first source follower circuit 130 and the third end of the first source follower circuit 130 are connected to ground through a fourth isolation circuit 530, and the fourth isolation circuit 530 is configured to turn on the first source follower circuit 130 and ground under the control of the first control signal output by the first isolation circuit 120, and to turn off the first source follower circuit 130 and ground under the control of the second control signal output by the first isolation circuit 120.

By providing the isolation circuits at the first terminal, the output terminal, and the second and third terminals of the first source follower circuit 130 IN this way, it is possible to ensure that the first source follower circuit 130 is completely isolated from the power supply, the ground, and the follower output terminal OUT when the second source follower circuit 140 is selected to follow the voltage signal received at the input terminal IN, and the first source follower circuit 130 can be circuit-protected.

In an example embodiment, as shown in fig. 5, the source follower circuit may further include a fifth isolation circuit 540, a sixth isolation circuit 550, and a seventh isolation circuit 560.

The fifth isolation circuit 540 is connected between the power input terminal VIN and the first terminal of the second source follower circuit 140, and the fifth isolation circuit 540 is configured to disconnect the power input terminal VIN from the second source follower circuit 140 under the control of the first control signal output by the first isolation circuit 120, and to connect the power input terminal VIN from the second source follower circuit 140 under the control of the second control signal output by the first isolation circuit 120.

The sixth isolation circuit 550 is connected between the output terminal of the second source follower circuit 140 and the follower output terminal OUT, and the sixth isolation circuit 550 is configured to disconnect the second source follower circuit 140 from the follower output terminal OUT under the control of the first control signal output by the first isolation circuit 120, and to connect the second source follower circuit 140 to the follower output terminal OUT under the control of the second control signal output by the first isolation circuit 120.

The second end of the second source follower circuit 140 and the third end of the second source follower circuit 140 are connected to ground through a seventh isolation circuit 560, and the seventh isolation circuit 560 is configured to disconnect the second source follower circuit 140 from ground under the control of the first control signal output by the first isolation circuit 120, and to turn on the second source follower circuit 140 from ground under the control of the second control signal output by the first isolation circuit 120.

IN this way, by providing the isolation circuits at the first end, the output end, and the second and third ends of the second source follower circuit 140, it is possible to ensure that the second source follower circuit 140 is completely isolated from the power supply, the ground, and the follower output end when the first source follower circuit 130 is selected to follow the voltage signal received at the input end IN, and the second source follower circuit 140 can be circuit-protected.

Based on the source follower circuit of the corresponding embodiment of fig. 5, fig. 6 schematically illustrates a structural diagram of a first source follower circuit connection isolation circuit in the source follower circuit according to an embodiment of the present invention. Taking the example that the output terminal a of the power supply voltage detection circuit 110 shown in fig. 3 includes the first sub-output terminal A1 and the second sub-output terminal A2, the first control signal output by the power supply voltage detection circuit 110 includes the high level signal output by the first sub-output terminal A1 and the low level signal output by the second sub-output terminal A2, and the second control signal output by the power supply voltage detection circuit 110 includes the low level signal output by the first sub-output terminal A1 and the high level signal output by the second sub-output terminal A2, that is, the first sub-output terminal A1 and the second sub-output terminal A2 output opposite level signals. The level signals output through the first sub-output terminal A1 and the second sub-output terminal A2 can control the operation of the circuit shown in fig. 6.

Referring to fig. 6, the second isolation circuit 510 is a Complementary Metal Oxide Semiconductor (CMOS) transmission gate structure, and includes a first N-channel field effect transistor NM1 and a first P-channel field effect transistor PM1, where a gate of the first N-channel field effect transistor NM1 is connected to the first sub-output terminal A1, and a gate of the first P-channel field effect transistor PM1 is connected to the second sub-output terminal A2; the source of the first N-channel fet NM1 and the drain of the first P-channel fet PM1 are connected to the first end of the first source follower circuit 130; the drain of the first N-channel fet NM1 and the source of the first P-channel fet PM1 are connected to the power input terminal VIN.

The third isolation circuit 520 has the same circuit configuration as the second isolation circuit 510. Specifically, the third isolation circuit 520 includes a second N-channel field effect transistor NM2 and a second P-channel field effect transistor PM2, where a gate of the second N-channel field effect transistor NM2 is connected to the first sub-output terminal A1, and a gate of the second P-channel field effect transistor PM2 is connected to the second sub-output terminal A2; the source electrode of the second N-channel field effect transistor NM2 and the drain electrode of the second P-channel field effect transistor PM2 are connected with the following output end OUT; the drain of the second N-channel fet NM2 and the source of the second P-channel fet PM2 are connected to the output of the first source follower circuit 130.

The fourth isolation circuit 530 includes a third N-channel field effect transistor NM3 and a fourth N-channel field effect transistor NM4, where a drain of the third N-channel field effect transistor NM3 is connected to the second end of the first source follower circuit 130, a drain of the fourth N-channel field effect transistor NM4 is connected to the third end of the first source follower circuit 130, a source of the third N-channel field effect transistor NM3 and a source of the fourth N-channel field effect transistor NM4 are respectively connected to ground, and a gate of the third N-channel field effect transistor NM3 and a gate of the fourth N-channel field effect transistor NM4 are respectively connected to the first sub-output terminal A1.

The first isolation sub-circuit 121 has the same circuit structure as the second isolation circuit 510, and is a CMOS transmission gate structure, and includes a fifth N-channel field effect transistor NM5 and a third P-channel field effect transistor PM3, where the drain of the fifth N-channel field effect transistor NM5 and the source of the third P-channel field effect transistor PM3 are connected as the first input terminal of the first isolation sub-circuit 121 and the following input terminal IN.

The circuit structure of the first source follower circuit 130 may be a super source follower structure including a first input fet PM51, a first output fet NM52, a second fet PM4, a third fet PM5, and a fourth fet NM6, and the negative feedback of the first output fet NM52 may be used to reduce the output impedance of the first source follower circuit 130, which may be expressed as

Wherein g _m1 Representing the transconductance, g, of the first input fet PM51 _mb1 Representing the bulk transconductance, g, of the first input fet PM51 _m2 Representing the transconductance, r, of the first output field effect transistor NM52 _o1 Representing the small signal impedance of the first input fet PM 51.

Illustratively, the first, second and third input field-effect transistors PM51, PM4 and PM5 may be P-channel field-effect transistors, and the first, output and fourth field-effect transistors NM52, NM6 may be N-channel field-effect transistors.

Specifically, the gate of the first input fet PM51 is connected to the first output terminal B1 of the first isolation circuit 120 as the input terminal of the first source follower circuit 130, and the source of the first input fet PM51 is connected to the drain of the first output fet NM52, the drain of the second fet PM4, the gate of the third fet PM5, and the drain of the third fet PM5, respectively, and the drain of the first input fet PM51 is connected to the gate of the first output fet NM52 and the drain of the fourth fet NM6, respectively. The source of the first output fet NM52 is connected to the drain of the fourth N-channel fet NM4 in the fourth isolation circuit 530 as the third terminal of the first source follower circuit 130, and the drain of the first output fet NM52 is connected to the third isolation circuit 520 as the output terminal of the first source follower circuit 130. The source of the fourth fet NM6 is connected to the drain of the third N-channel fet NM3 in the fourth isolation circuit 530 as the second end of the first source follower circuit 130.

The source of the second fet PM4 and the source of the third fet PM5 are connected to the second isolation circuit 510 as the first end of the first source follower circuit 130, respectively. The gate of the second fet PM4 is for receiving the positive bias voltage Bp of the mirror current source, and the gate of the fourth fet NM6 is for receiving the negative bias voltage Bn of the mirror current source.

In an example embodiment, the second source follower circuit 140 may have the same circuit structure as the first source follower circuit 130. For example, fig. 7 schematically illustrates a structure diagram of a second source follower circuit connection isolation circuit in the source follower circuit according to the embodiment of the present invention, referring to fig. 7, a fifth isolation circuit 540 includes an N-channel fet NM7 and a P-channel fet PM6, a sixth isolation circuit 550 includes an N-channel fet NM8 and a P-channel fet PM7, a seventh isolation circuit 560 includes N-channel fets NM9 and NM10, a second isolation sub-circuit 122 includes an N-channel fet NM11 and a P-channel fet PM8, a second source follower circuit 140 includes a second input fet PM53, a second output fet NM54, a fifth fet PM9, a third fet PM10 and a fourth fet NM12, wherein the second input fet PM53, the fifth fet PM9 and the third fet PM10 may be P-channel fets, and the second output fet NM54 and the fourth fet NM12 may be N-channel fets. The connection relationship between each device can be seen in fig. 7, which is the same as the circuit structure shown in fig. 6, but the connection relationship between the first sub-output terminal A1 and the second sub-output terminal A2 in fig. 6 is exchanged, and will not be described here again.

In the embodiment of the invention, the field effect transistor can be used for selecting the MOSFET.

Referring to fig. 7 and the above embodiments, the first source follower circuit 130 and the second source follower circuit 140 form a dual-mode source follower circuit, and can be switched under the control of the control signals output from the first sub-output terminal A1 and the second sub-output terminal A2 of the power supply voltage detection circuit 110. The source follower circuit provided by the embodiment of the present invention is further illustrated below by taking a MOSFET with 1.8V for the first input fet PM51 and the first output fet NM52, a MOSFET with 5V for the second input fet PM53 and the second output fet NM54, and MOSFETs with the same withstand voltage value as the second input fet PM53 for other fets as examples.

The voltage withstanding values of the input field effect transistor and the output field effect transistor of the first source follower circuit 130 are smaller than those of the input field effect transistor and the output field effect transistor of the second source follower circuit 140, and the threshold voltage of the input field effect transistor is reduced by the first source follower circuit 130, so that the lowest supply voltage of the dual-mode source follower circuit can be shifted down.

After the determination of the voltage dividing resistors of the voltage dividing circuit 111 and the reference voltage VREF of the reference voltage terminal VREF in the power supply voltage detection circuit 110, the voltage is calculated according to the first condition VDD (R ₂ +R ₃ ）/(R ₁ +R ₂ +R ₃ ) =vref and second condition vdd×r ₂ /（R ₁ +R ₂ ) The value of the voltage to be met by the supply voltage VDD when the first control signal and the second control signal output by the supply voltage detection circuit 110 reach the inversion point can be determined by =vref, and if VDD1 is determined according to the first condition and VDD2 is determined according to the second condition, the circuit is switched to the first source follower circuit 130 when the supply voltage falls to VDD1, and is switched back to the second source follower circuit 140 when the supply voltage rises back to VDD 2.

Taking vdd1=2. V, VDD2 =3v as an example, the power supply voltage detection circuit 110 divides the power supply voltage VDD and compares the divided power supply voltage VDD with the reference voltage Vref, when the power supply voltage VDD is less than 2.8V, the first sub-output terminal A1 of the power supply voltage detection circuit 110 outputs a high level signal and the second sub-output terminal A2 outputs a low level signal, at this time, the first isolation sub-circuit 121, the second isolation circuit 510, the third isolation circuit 520 and the fourth isolation circuit 530 can be controlled to be turned on, and the second isolation sub-circuit 122, the fifth isolation circuit 540, the sixth isolation circuit 550 and the fourth isolation circuit 530 can be controlled to be turned onThe seventh isolation circuit 560 is turned off, the circuit is switched to a low withstand voltage value operation mode of 1.8V, the voltage signal received by the follower input terminal IN is voltage-followed by the first source follower circuit 130, and the impedance transformation between the follower input terminal IN and the follower output terminal OUT is realized, and the second source follower circuit 140 is completely isolated. At the same time, the hysteresis control circuit 114 controls the switch circuit 112 to be turned on to switch the voltage dividing ratio of the voltage dividing circuit 111 from (R ₂ +R ₃ ）/（R ₁ +R ₂ +R ₃ ) Is adjusted to R ₂ /（R ₁ +R ₂ ) By adjusting the voltage dividing ratio, the switching threshold for switching to the high withstand voltage operation mode is adjusted to 3V, that is, the circuit is switched from the first source follower circuit 130 to the second source follower circuit 140 when the power supply voltage VDD rises back to 3V.

When the power supply voltage VDD is greater than 3V, the first sub-output terminal A1 of the power supply voltage detection circuit 110 outputs a low level signal and the second sub-output terminal A2 outputs a high level signal, at this time, the first isolation sub-circuit 121, the second isolation circuit 510, the third isolation circuit 520, and the fourth isolation circuit 530 may be controlled to be turned off, and the second isolation sub-circuit 122, the fifth isolation circuit 540, the sixth isolation circuit 550, and the seventh isolation circuit 560 may be controlled to be turned on, the circuits may be switched to a high withstand voltage value operation mode of 5V, the voltage signal received at the following input terminal IN may be voltage-followed by the second source follower circuit 140, and impedance transformation between the following input terminal IN and the following output terminal OUT may be implemented, and the first source follower circuit 130 may be completely isolated. At the same time, the hysteresis control circuit 114 controls the switch circuit 112 to be turned off to separate the voltage dividing ratio of the voltage dividing circuit 111 from R ₂ /（R ₁ +R ₂ ) Is adjusted to (R) ₂ +R ₃ ）/（R ₁ +R ₂ +R ₃ ) By adjusting the voltage dividing ratio, the switching threshold for switching to the low withstand voltage operation mode is adjusted to 2.8V, i.e., the circuit is switched from the second source follower circuit 140 to the first source follower circuit 130 when the power supply voltage VDD falls to 2.8V.

In this way, when the operation mode is switched, the hysteresis control circuit 114 will automatically switch the voltage division ratio of the voltage division circuit 111, and a certain margin is reserved between the two operation modes by switching the voltage division ratio, so that the power supply voltage is ensured to be switched to the low withstand voltage operation mode when being reduced to 2.8V, and to be switched to the high withstand voltage operation mode when being increased to 3V again, so that the two operation modes can be kept stable after being switched, and the switching back and forth at the critical point is prevented. In addition, the high withstand voltage value working mode can adapt to the power supply voltage of 3V to 5.5V, when the power supply voltage is reduced to 2.8V, the low withstand voltage value working mode can be switched, and in the low withstand voltage value working mode, the low threshold voltage of the 1.8V input field effect transistor enables the input and output of the source follower circuit to have smaller voltage difference, the requirement on the minimum power supply voltage is reduced, and then the LDO system using the source follower circuit can work with lower power supply voltage.

According to the source follower circuit provided by the embodiment of the invention, the first source follower circuit with a low voltage resistance value or the second source follower circuit with a high voltage resistance value can be automatically selected to carry out voltage following according to the detection output of the power supply voltage detection circuit, the second source follower circuit with the high voltage resistance value can meet the requirement of higher power supply voltage, the first source follower circuit with the low voltage resistance value can enable smaller pressure difference between the input and the output of the source follower circuit, the requirement on the minimum power supply voltage is reduced, the minimum power supply voltage of the whole source follower circuit can be downwards moved by about the difference between the threshold voltage of the MOSFET with the high voltage resistance value and the threshold voltage of the MOSFET with the low voltage resistance value, and the whole source follower circuit can be compatible with a wider power supply voltage range, so that an LDO system using the source follower circuit can work with lower power supply voltage and can be compatible with the wider power supply voltage range. In addition, a plurality of isolation circuits are designed for the dual-mode source follower circuit formed by the first source follower circuit and the second source follower circuit, so that when one source follower circuit is used, the other source follower circuit is completely isolated from a power supply, a ground, a follower input end and a follower output end, and the protection of the circuit is realized.

The embodiment of the invention further provides a low dropout linear regulator, fig. 8 schematically shows a structural diagram of the low dropout linear regulator, and referring to fig. 8, the low dropout linear regulator may include an error amplifier 810, an output stage power tube circuit 820, and a source follower circuit 830, where a following input terminal IN of the source follower circuit 830 is connected to an output terminal of the error amplifier 810, and a following output terminal OUT of the source follower circuit 830 is connected to an input terminal of the output stage power tube circuit 820.

The source follower circuit 830 may be any of the source follower circuits described in the above embodiments.

According to the low-dropout linear voltage regulator provided by the embodiment of the invention, the field effect transistor with a high withstand voltage value is used to meet the requirement of the LDO system for compatibility with a wider supply voltage range, and devices in a circuit are not damaged, so that the lowest supply voltage of the LDO system can be continuously reduced, the low-dropout linear voltage regulator works with a lower supply voltage, the power consumption is reduced, and the LDO system can be compatible with the wider supply voltage range.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The source follower circuit is characterized by being applied to a low dropout linear voltage regulator, and comprises a power supply input end, a reference voltage end, a following input end, a following output end, a power supply voltage detection circuit, a first isolation circuit, a first source follower circuit and a second source follower circuit;

2. The source follower circuit of claim 1, wherein the supply voltage detection circuit comprises a voltage divider circuit, a switching circuit, a comparator, and a hysteresis control circuit;

3. The source follower circuit of claim 2, wherein the voltage divider circuit comprises a first voltage divider resistor, a second voltage divider resistor, and a third voltage divider resistor;

4. A source follower circuit according to claim 3, wherein the output of the supply voltage detection circuit comprises a first sub-output and a second sub-output; the hysteresis control circuit comprises a first inverter and a second inverter;

5. The source follower circuit of claim 1, wherein the first isolation circuit comprises a first isolation sub-circuit and a second isolation sub-circuit;

6. The source follower circuit of any one of claims 1 to 5, further comprising a second isolation circuit, a third isolation circuit, and a fourth isolation circuit;

7. The source follower circuit of claim 6, wherein the output of the supply voltage detection circuit comprises a first sub-output and a second sub-output, the first control signal comprising a high level signal output by the first sub-output and a low level signal output by the second sub-output; the second control signal comprises a low-level signal output by the first sub-output end and a high-level signal output by the second sub-output end;

8. The source follower circuit of any one of claims 1 to 5, further comprising a fifth isolation circuit, a sixth isolation circuit, and a seventh isolation circuit;

9. The source follower circuit according to any one of claims 1 to 5, wherein the first source follower circuit and the second source follower circuit have the same circuit structure.

10. A low dropout linear regulator comprising an error amplifier, an output stage power transistor circuit and a source follower circuit according to any one of claims 1 to 9;