WO2024018927A1 - Linear power supply device and power supply system - Google Patents

Linear power supply device and power supply system Download PDF

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Publication number
WO2024018927A1
WO2024018927A1 PCT/JP2023/025292 JP2023025292W WO2024018927A1 WO 2024018927 A1 WO2024018927 A1 WO 2024018927A1 JP 2023025292 W JP2023025292 W JP 2023025292W WO 2024018927 A1 WO2024018927 A1 WO 2024018927A1
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Prior art keywords
power supply
linear power
voltage information
output
voltage
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PCT/JP2023/025292
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French (fr)
Japanese (ja)
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勇武 岩橋
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ローム株式会社
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Publication of WO2024018927A1 publication Critical patent/WO2024018927A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the present disclosure relates to a linear power supply device and a power supply system.
  • linear power supplies linear regulators
  • linear regulators linear regulators
  • Some linear power supply devices use two linear power supply devices and commonly connect the output terminals of the respective linear power supply devices to a common load (for example, Patent Document 1). That is, such linear power supplies are connected in parallel to a common load.
  • the purpose of such a linear power supply is to disperse heat by distributing the load current into the output current output from the output terminals, or to increase the load current based on the output current output from each output terminal. The purpose is to do something.
  • an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation in parallel connection applications, regardless of variations in the linear power supply devices.
  • the linear power supply device is an output transistor having a first main electrode configured to be connectable to an input voltage application end and a second main electrode; an output terminal connected to the second main electrode; an error amplifier configured to receive a feedback voltage based on the output voltage generated at the output terminal and a reference voltage, and to be able to drive a control end of the output transistor; a mirror transistor configured to be able to generate a mirror current of the current flowing through the output transistor; a current/voltage converter that converts the mirror current into first voltage information; a voltage information output terminal configured to be able to output the first voltage information to the outside; a voltage information input terminal configured to allow input of second voltage information from the outside; a comparison unit configured to compare the second voltage information and the first voltage information;
  • the control transistor is configured to include a control transistor that is driven based on the comparison result of the comparison section and controls so that the difference between the second voltage information and the first voltage information becomes small.
  • linear power supply device in parallel connection applications, it is possible to effectively perform parallel operation regardless of variations in the linear power supply devices.
  • FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example.
  • FIG. 2 is a diagram showing the configuration of the power supply system according to the first embodiment.
  • FIG. 3 is a diagram showing an OR circuit.
  • FIG. 4 is a diagram showing another configuration example of the power supply system according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a current waveform in the configuration shown in FIG. 4.
  • FIG. 6 is a diagram showing the configuration of a power supply system according to the second embodiment.
  • FIG. 7 is a diagram showing another configuration example of the power supply system according to the second embodiment.
  • FIG. 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example.
  • the power supply system 50 includes a linear power supply device 10A, a linear power supply device 10B, and resistors Ra and Rb.
  • Power supply system 50 supplies load current Iout to load RL using two linear power supplies 10A and 10B.
  • the linear power supplies 10A and 10B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 10A and the linear power supply device 10B are ICs (Integrated Circuits) with the same configuration, and corresponding components are designated with “A” or "B” for the same reference numerals. It is illustrated. Below, the configuration of the linear power supply device 10A will be representatively explained.
  • the linear power supply device 10A is an IC that includes an output transistor M10A, resistors R11A and 12A, and an error amplifier AP10A, and integrates these into one chip.
  • the source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input terminal of the input voltage Vin.
  • the drain of the output transistor M10A and the first end of the resistor R11A are commonly connected to an output terminal ToA for outputting the output voltage VoA.
  • a second end of resistor R11A is connected to a first end of resistor R12A.
  • a second end of the resistor R12A is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP10A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP10A is connected to the gate of the output transistor M
  • the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.
  • the output terminal ToA is connected to the first end of a resistor Ra provided outside the linear power supply devices 10A and 10B.
  • the output terminal ToB is connected to a first end of a resistor Rb provided outside the linear power supply devices 10A and 10B.
  • the second ends of each of the resistors Ra and Rb are commonly connected to the load RL. Therefore, linear power supplies 10A and 10B are connected in parallel to a common load RL.
  • the standard values (Typ values) of the output voltages VoA and VoB of the linear power supplies 10A and 10B are set to be the same, but due to variations in the linear power supplies, the output voltage may vary from the standard value. be. For example, it varies by ⁇ 2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, as well as variations in the input offset voltage of the error amplifier.
  • the output transistor M10B on the linear power supply 10B side is kept off, and the output is output from the output terminal ToB.
  • the current IoutB is not output, and the load current Iout is supplied only by the output current IoutA output from the output terminal ToA of the linear power supply device 10A. Therefore, the output current is concentrated on one linear power supply device.
  • the output voltage VoA when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0 A, the output voltage VoA is dropped by the resistor Ra.
  • the output voltage Vo generated at the node to which the second ends of the resistors Ra and Rb are connected gradually decreases.
  • the output transistor M10B on the linear power supply device 10B side starts operating, and the output of the output current IoutB is started from the output terminal ToB. That is, a parallel operation is started in which the load current Iout is supplied by both the output currents IoutA and IoutB.
  • the resistors Ra and Rb may be set to such resistance values that the voltage drop across the resistors is greater than or equal to the voltage difference between the maximum and minimum values due to variations in the output voltage.
  • this comparative example has problems in that loss and heat generation occur due to the resistors Ra and Rb, and that the output currents IoutA and IoutB are not equal. Further, when the load current Iout changes, the output voltage Vo changes due to the voltage drop caused by the resistors Ra and Rb, causing a problem in the function as a regulator.
  • FIG. 2 is a diagram showing the configuration of the power supply system 5 according to the first embodiment.
  • the power supply system 5 includes a linear power supply device 1A and a linear power supply device 1B.
  • the power supply system 5 supplies a load current Iout to the load RL using two linear power supplies 1A and 1B.
  • the linear power supplies 1A and 1B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 1A and the linear power supply device 1B are ICs with the same configuration, and corresponding components are shown with "A” or "B" attached to the same reference numerals. There is. Below, the configuration of the linear power supply device 1A will be representatively explained.
  • the linear power supply device 1A includes an output transistor M1A, a mirror transistor M2A, an error amplifier AP1A, feedback resistors R1A, R2A, R3A, R4A, a bypass switch BPA, a sense resistor RsA, and a comparator.
  • This IC includes a CPA, an NMOS transistor (N-channel MOSFET) NMA, a resistor RA, NMOS switches NS1A, NS2A, and a PMOS switch PMA, and these are integrated into one chip.
  • the linear power supply device 1A has external terminals such as an output terminal ToA and a voltage information transmission/reception terminal TvA in order to establish electrical connection with the outside.
  • the source of the output transistor M1A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of output transistor M1A is connected to the first end of feedback resistor R1A.
  • the drain of the output transistor M1A is connected to an output terminal ToA for outputting an output voltage VoA.
  • a second end of feedback resistor R1A is connected to a first end of feedback resistor R2A.
  • a second end of feedback resistor R2A is connected to a first end of feedback resistor R3A.
  • a second end of feedback resistor R3A is connected to a first end of feedback resistor R4A.
  • a second end of the feedback resistor R4A is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP1A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP1A is connected to the gate of the output transistor M1A.
  • bypass switch BPA constituted by an NMOS transistor
  • the source of bypass switch BPA is connected to the second end of feedback resistor R4A.
  • a gate of bypass switch BPA is connected to an application terminal of control signal ScA. Thereby, the on state/off state of the bypass switch BPA is switched according to the control signal ScA.
  • the bypass switch BPA is in the on state, both ends of the feedback resistor R4A are short-circuited, and the feedback resistor R4A is bypassed.
  • the bypass switch BPA is in the off state, the feedback resistor R4A is enabled.
  • the source of the mirror transistor M2A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M2A is connected to the first end of sense resistor RsA.
  • the gate of mirror transistor M2A is connected to the output terminal of error amplifier AP1A.
  • a second end of the sense resistor RsA is connected to a ground terminal.
  • a first end of the sense resistor RsA is connected to the drain of an NMOS switch NS1A configured as an NMOS transistor.
  • the source of the NMOS switch NS1A is connected to the voltage information transmission/reception terminal TvA.
  • the gate of the NMOS switch NS1A is connected to the application terminal of the control signal ScA. The on/off state of the NMOS switch NS1A is switched by the control signal ScA.
  • a mirror current Im2A of the current flowing through the output transistor M1A flows through the mirror transistor M2A.
  • the mirror current Im2A is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1A.
  • voltage information Vmon obtained by converting the mirror current Im2A into a current/voltage by the sense resistor RsA can be outputted to the outside from the voltage transmitting/receiving terminal TvA via the NMOS switch NS1A.
  • the comparator CPA includes PMOS transistors P1 and P2 and NMOS transistors N1 and N2.
  • the sources of PMOS transistors P1 and P2 are connected to the drain of PMOS switch PMA.
  • the gate of PMOS transistor P1 is connected to voltage information transmission/reception terminal TvA.
  • the gate of PMOS transistor P2 is connected to the first end of sense resistor RsA.
  • the drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1.
  • the drain and gate of NMOS transistor N1 are shorted.
  • the gates of NMOS transistors N1 and N2 are connected to each other.
  • the sources of NMOS transistors N1 and N2 are connected to a ground terminal.
  • the drain of the NMOS transistor N2 and the drain of the PMOS transistor P2 are connected at a node Nd. Note that a phase compensation capacitor C1 is connected between the gate and drain of the NMOS transistor N2.
  • NMOS transistor NMA The gate of NMOS transistor NMA is connected to node Nd.
  • the source of the NMOS transistor NMA is connected to a ground terminal via a resistor RA.
  • the drain of the NMOS transistor NMA is connected to a node NDA to which feedback resistors R1A and R2A are connected. Note that a phase compensation capacitor C2 is connected between the gate and drain of the NMOS transistor NMA.
  • the drain of the NMOS switch NS2A is connected to the gate of the NMOS transistor NMA.
  • the source of NMOS switch NS2A is connected to the ground terminal.
  • the gate of the PMOS switch PMA and the gate of the NMOS switch NS2A are connected to the application terminal of the control signal ScA.
  • the control signal ScA switches the on state/off state of the PMOS switch PMA and the NMOS switch NS2A.
  • the NMOS switch NS1A When the control signal ScA is at a low level, the NMOS switch NS1A is in the off state, the PMOS switch PMA is in the on state, and the NMOS switch NS2A is in the off state.
  • voltage information Vmon input from the outside to the voltage information transmitting/receiving terminal TvA is applied to the gate of the PMOS transistor P1
  • voltage information Vs obtained by converting the mirror current Im2A into a voltage by the sense resistor RsA is applied to the gate of the PMOS transistor P2. Applied to the gate.
  • the voltage information Vs and Vmon are compared by the comparator CPA, and the gate of the NMOS transistor NMA is driven based on the comparison result. Since the drain of the NMOS transistor NMA is connected to the node NDA, the output voltage VoA is controlled so that the voltage information Vs and Vmon match.
  • FIG. 3 is a diagram showing an OR circuit Or provided in the linear power supply device 1A.
  • the protection signals P1 to Pn, the enable signal En, and the master/slave selection signal MS are input to the OR circuit Or.
  • a control signal ScA is output from the OR circuit Or.
  • the control signal ScA is at a high level. Note that the configuration is not limited to the OR circuit, but may be configured using other logic circuits such as a NAND circuit.
  • the output terminal ToA of the linear power supply device 1A and the output terminal ToB of the linear power supply device 1B are commonly connected to the load RL. That is, two linear power supplies are connected in parallel to the load RL. Further, the voltage information transmitting/receiving terminal TvA of the linear power supply device 1A and the voltage information transmitting/receiving terminal TvB of the linear power supply device 1B are connected.
  • One of the linear power supply devices 1A and 1B is set as a master, and the other is set as a slave.
  • the linear power supply device 1A is set as the master and the linear power supply device 1B is set as the slave.
  • the linear power supply device 1A is set as the master (FIG. 2).
  • the control signal ScA becomes high level
  • the NMOS switch NS1A is turned on
  • the PMOS switch PMA is turned off
  • the NMOS switch NS2A is turned on.
  • the voltage information Vmon to be output from the voltage information transmission/reception terminal TvA.
  • no current is supplied to the comparator CPA, making the comparator CPA ineffective, and the gate of the NMOS transistor NMA becomes a low level.
  • the bypass switch BPA is turned on, and the feedback resistor R4A is bypassed.
  • the linear power supply device 1B is set as a slave (FIG. 2).
  • the control signal ScB becomes a low level
  • the NMOS switch NS1B is turned off
  • the PMOS switch PMB is turned on
  • the NMOS switch NS2B is turned off.
  • a current is supplied to the comparator CPB, and the comparator CPB becomes valid, making it possible to compare the voltage information Vs and Vmon.
  • NMOS transistor NMB becomes valid.
  • the bypass switch BPB is turned off, and the feedback resistor R4B is enabled.
  • the feedback resistors R4A and R4B may be set to a resistance value that is greater than or equal to the voltage difference between the maximum value and the minimum value due to variations in the output voltage. Thereby, even if there are variations in the output voltages VoA and VoB, the output voltage VoB can be set lower than VoA.
  • the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
  • the mirror current Im2B also starts flowing, and by driving the NMOS transistor NMB by comparing the voltage information Vs and Vmon, the voltage information Vs and Vmon match, that is, the output currents IoutB and IoutA match. controlled as follows.
  • linear power supply devices may be connected in parallel to the load RL.
  • Output terminals ToA, ToB, and ToC of linear power supplies 1A, 1B, and 1C shown in FIG. 4 are commonly connected to a load RL.
  • voltage information transmitting/receiving terminals TvA, TvB, and TvC of the linear power supplies 1A, 1B, and 1C are connected.
  • the linear power supply device 1A is set as a master, and the linear power supply devices 1B and 1C are set as slaves.
  • the output currents IoutA, IoutB, and IoutC of the linear power supplies 1A, 1B, and 1C are controlled to match (that is, the output currents IoutA, IoutB, and IoutC are each controlled to 1 ⁇ 3 of the load current Iout).
  • FIG. 5 shows a schematic current waveform at startup in the configuration shown in FIG. 4. As shown in FIG. 5, first, the output current IoutA of the master linear power supply device 1A rises, and then the output currents IoutB and IoutC rise. Then, the output currents IoutA, IoutB, and IoutC are controlled to match.
  • three or more linear power supply devices may be provided as slaves. That is, it is possible to provide two or more linear power supply devices that are set as slaves for a linear power supply device that is set as a master. Since the voltage information Vmon output from the master linear power supply is a voltage signal rather than a current signal, the signal is not divided by two or more slave linear power supply devices, and the output current of each linear power supply can be made equal.
  • FIG. 6 is a diagram showing the configuration of a power supply system 5 according to the second embodiment.
  • FIG. 6 shows the configuration of a power supply system 5 according to the second embodiment.
  • FIG. 2 shows the configuration of this embodiment and the first embodiment (FIG. 2).
  • the configuration of the linear power supply device 1A among the linear power supply devices 1A and 1B will be representatively explained.
  • the NMOS switch NS1A is not provided, and the first end of the sense resistor RsA is connected to the voltage source terminal TsrA, which is an external terminal.
  • the voltage source terminal TsrA is a terminal for outputting to the outside voltage information VmonA obtained by converting the mirror current Im2A into a current voltage using the sense resistor RsA.
  • the gate of the PMOS transistor P1 is connected to the voltage sink terminal TskA.
  • the voltage sink terminal TskA is a terminal for inputting voltage information Vmon from the outside.
  • Voltage source terminal TsrA and voltage sink terminal TskA are separate terminals.
  • the feedback resistor R4A and the bypass switch BPA are not provided.
  • the voltage source terminal TsrA of the linear power supply device 1A is connected to the voltage sink terminal TskB of the linear power supply device 1B. Thereby, the voltage information VmonA output from the voltage source terminal TsrA is input to the voltage sink terminal TskB.
  • a comparator CPB compares voltage information VsB obtained by converting the mirror current Im2B into a current voltage using a sense resistor RsB and VmonA.
  • the voltage source terminal TsrB of the linear power supply device 1B is connected to the voltage sink terminal TskA of the linear power supply device 1A. Thereby, the voltage information VmonB output from the voltage source terminal TsrB is input to the voltage sink terminal TskA.
  • a comparator CPA compares voltage information VsA obtained by converting a mirror current Im2A into a current voltage using a sense resistor RsA and VmonB.
  • the output voltage VoA of the linear power supply device 1A is higher than the output voltage VoB of the linear power supply device 1B due to variations in the linear power supply device.
  • the output current IoutB is not initially output from the output terminal ToB of the linear power supply 1B, and the load is caused only by the output current IoutA output from the output terminal ToA of the linear power supply 1A.
  • a current Iout is supplied.
  • mirror current Im2A flows, and voltage information VmonA based on mirror current Im2A is output from voltage source terminal TsrA and input to voltage sink terminal TskB.
  • mirror current Im2B does not flow, voltage information VsB and VmonA are compared by comparator CPB, NMOS transistor NMB is driven, and output voltage VoB of linear power supply device 1B is increased.
  • the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
  • the mirror current Im2B also starts to flow, and the NMOS transistor NMB is driven by comparing the voltage information VsB and VmonA, and is controlled so that the voltage information VsB and VmonA match.
  • the NMOS transistor NMA is driven by comparing the voltage information VsA and VmonB, and is controlled so that the voltage information VsA and VmonB match. Thereby, the output currents IoutA and IoutB are controlled to match.
  • FIG. 7 is a diagram showing a case where three linear power supply devices according to the second embodiment are connected in parallel to a load RL to configure a power supply system 5.
  • the voltage source terminal TsrA of the linear power supply 1A is connected to the voltage sink terminal TskB of the linear power supply 1B
  • the voltage source terminal TsrB of the linear power supply 1B is connected to the voltage sink terminal TskC of the linear power supply 1C
  • the linear A voltage source terminal TsrC of the power supply device 1C is connected to a voltage sink terminal TskA of the linear power supply device 1A.
  • the output currents IoutA, IoutB, and IoutC of the linear power supply devices 1A, 1B, and 1C can be equally controlled. Note that even if four or more linear power supply devices 1 are connected in parallel to the load RL, each output current can be controlled equally.
  • the linear power supply device (1A) having a first main electrode configured to be connectable to an application end of the input voltage (Vin) and a second main electrode; an output terminal (ToA) connected to the second main electrode; an error amplifier (AP1A) configured to receive a feedback voltage (VfbA) based on the output voltage (VoA) generated at the output terminal and a reference voltage (VrefA) and to be able to drive a control end of the output transistor; a mirror transistor (M2A) configured to be able to generate a mirror current (Im2A) of the current flowing through the output transistor; a current/voltage converter (RsA) that converts the mirror current into first voltage information (Vmon, Vs); a voltage information output terminal (TvA) configured to be able to output the first voltage information (Vmon) to the outside; a voltage information input terminal (TvA) configured to be able to input
  • the first main electrode of the control transistor (NMA) is connected to the feedback resistor section (R1A, R2A, R3A, R4A) connected to the second main electrode of the output transistor (M1A).
  • a configuration in which they are connected may also be used (second configuration).
  • the voltage information output terminal and the voltage information input terminal are the same terminal (TvA), further comprising a first switch (NS1A) for switching whether or not to output the first voltage information from the voltage information output terminal;
  • a first switch for switching whether or not to output the first voltage information from the voltage information output terminal;
  • a second switch switches whether or not to bypass a part of the feedback resistor (R4A) of the feedback resistor section connected to the second main electrode of the output transistor (M1A).
  • the second switch may be configured to operate in conjunction with the first switch (fourth configuration).
  • the third switch (PMA) is further provided for switching whether or not to supply current to the comparing section (CPA), and the third switch is interlocked with the first switch. (fifth configuration).
  • any one of the third to fifth configurations further comprising a fourth switch (NS2A) connected between the control terminal and the ground terminal of the control transistor (NMA),
  • the fourth switch may be configured to work in conjunction with the first switch (sixth configuration).
  • the voltage information output terminal (TsrA) and the voltage information input terminal (TskA) may be separate terminals (seventh configuration).
  • a power supply system (5) includes a master linear power supply device (1A) that is a linear power supply device having the third configuration, in which the first switch (NS1A) is set to an on state; one or more slave linear power supply devices (1B), which are linear power supply devices of the third configuration, in which the first switch is set to an off state;
  • the output terminal (ToA) of the master linear power supply device and the output terminal (ToB) of the slave linear power supply device can be commonly connected to a load,
  • the voltage information output terminal (TvA) of the master linear power supply device and the voltage information input terminal (TvB) of the slave linear power supply device are connectable (eighth configuration).
  • the number of slave linear power supply devices may be two or more (ninth configuration).
  • a power supply system (5) includes a plurality of linear power supply devices according to the seventh configuration,
  • the respective output terminals (ToA, ToB) in the plurality of linear power supply devices (1A, 1B) can be commonly connected to a load,
  • the voltage information output terminals (TsrA, TsrB) and the voltage information input terminals (TskB, TskA) are sequentially connected between different linear power supply devices. (10th configuration).
  • the present disclosure can be used in power supply systems installed in various devices.

Abstract

A linear power supply device (1A) comprises: a current/voltage conversion unit (RsA) that converts a mirror current into first voltage information (Vmon, Vs); a voltage information output terminal (TvA) configured to be able to output the first voltage information (Vmon) to the outside; a voltage information input terminal (TvA) configured to allow for the input of second voltage information (Vmon) from the outside; a comparison unit (CPA) configured to compare the second voltage information (Vmon) with the first voltage information (Vs); and a control transistor (NMA) that is driven on the basis of the result of comparison by the comparison unit, and effects control to decrease the difference between the second voltage information and the first voltage information.

Description

リニア電源装置、および電源システムLinear power supplies and power systems
　本開示は、リニア電源装置、および電源システムに関する。 The present disclosure relates to a linear power supply device and a power supply system.
　従来、入力電圧から所望の出力電圧を生成することのできるリニア電源装置（リニアレギュレータ）は、様々なアプリケーション（車載機器、産業機器、事務機器、デジタル家電、あるいはポータブル機器など）に搭載されている。 Conventionally, linear power supplies (linear regulators) that can generate a desired output voltage from an input voltage have been installed in various applications (in-vehicle equipment, industrial equipment, office equipment, digital home appliances, portable equipment, etc.) .
　リニア電源装置には、２つのリニア電源装置を用いて、それぞれのリニア電源装置の出力電圧を出力する出力端子を共通の負荷に共通接続するものがある（例えば特許文献１）。すなわち、このようなリニア電源装置は、共通の負荷に対して並列に接続される。このようなリニア電源装置の用途は、負荷電流を出力端子から出力される出力電流に分散することで熱分散を行ったり、各出力端子から出力される出力電流に基づき負荷電流を大電流化することなどを目的とする。 Some linear power supply devices use two linear power supply devices and commonly connect the output terminals of the respective linear power supply devices to a common load (for example, Patent Document 1). That is, such linear power supplies are connected in parallel to a common load. The purpose of such a linear power supply is to disperse heat by distributing the load current into the output current output from the output terminals, or to increase the load current based on the output current output from each output terminal. The purpose is to do something.
特開２０２０－４２１４号公報JP 2020-4214 Publication
　しかしながら、上記のようにリニア電源装置を並列接続した場合、リニア電源装置のばらつきの影響でそれぞれの出力端子から出力される出力電圧に差が生じる場合がある。この場合、低いほうの出力電圧のリニア電源装置から出力電流が出力されず、高いほうの出力電圧のリニア電源装置の出力電流のみにより負荷電流が供給される現象が生じる。これにより、リニア電源装置の並列接続が意味をなさない虞があった。 However, when linear power supplies are connected in parallel as described above, differences may occur in the output voltages output from the respective output terminals due to variations in the linear power supplies. In this case, a phenomenon occurs in which no output current is output from the linear power supply device with the lower output voltage, and the load current is supplied only by the output current of the linear power supply device with the higher output voltage. As a result, there was a possibility that parallel connection of the linear power supply devices would be meaningless.
　上記状況に鑑み、本開示は、並列接続の用途において、リニア電源装置のばらつきに関わらず、効果的に並列動作を行うことが可能となるリニア電源装置を提供することを目的とする。 In view of the above situation, an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation in parallel connection applications, regardless of variations in the linear power supply devices.
　例えば、本開示に係るリニア電源装置は、
　入力電圧の印加端に接続可能に構成される第１主電極と、第２主電極と、を有する出力トランジスタと、
　前記第２主電極に接続される出力端子と、
　前記出力端子に発生する出力電圧に基づく帰還電圧と、基準電圧とが入力され、前記出力トランジスタの制御端を駆動可能に構成されるエラーアンプと、
　前記出力トランジスタに流れる電流のミラー電流を生成可能に構成されるミラートランジスタと、
　前記ミラー電流を第１電圧情報に変換する電流／電圧変換部と、
　前記第１電圧情報を外部に対して出力可能に構成される電圧情報出力端子と、
　第２電圧情報を外部から入力可能に構成される電圧情報入力端子と、
　前記第２電圧情報と前記第１電圧情報とを比較するように構成される比較部と、
　前記比較部の比較結果に基づき駆動され、前記第２電圧情報と前記第１電圧情報の差が小さくなるように制御する制御トランジスタと、を備える構成としている。 For example, the linear power supply device according to the present disclosure is
an output transistor having a first main electrode configured to be connectable to an input voltage application end and a second main electrode;
an output terminal connected to the second main electrode;
an error amplifier configured to receive a feedback voltage based on the output voltage generated at the output terminal and a reference voltage, and to be able to drive a control end of the output transistor;
a mirror transistor configured to be able to generate a mirror current of the current flowing through the output transistor;
a current/voltage converter that converts the mirror current into first voltage information;
a voltage information output terminal configured to be able to output the first voltage information to the outside;
a voltage information input terminal configured to allow input of second voltage information from the outside;
a comparison unit configured to compare the second voltage information and the first voltage information;
The control transistor is configured to include a control transistor that is driven based on the comparison result of the comparison section and controls so that the difference between the second voltage information and the first voltage information becomes small.
　本開示に係るリニア電源装置によれば、並列接続の用途において、リニア電源装置のばらつきに関わらず、効果的に並列動作を行うことが可能となる。 According to the linear power supply device according to the present disclosure, in parallel connection applications, it is possible to effectively perform parallel operation regardless of variations in the linear power supply devices.
図１は、比較例に係る電源システムの構成を示す図である。FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example. 図２は、第１実施形態に係る電源システムの構成を示す図である。FIG. 2 is a diagram showing the configuration of the power supply system according to the first embodiment. 図３は、ＯＲ回路を示す図である。FIG. 3 is a diagram showing an OR circuit. 図４は、第１実施形態に係る電源システムの別構成例を示す図である。FIG. 4 is a diagram showing another configuration example of the power supply system according to the first embodiment. 図５は、図４に示す構成における電流波形例を示す図である。FIG. 5 is a diagram showing an example of a current waveform in the configuration shown in FIG. 4. 図６は、第２実施形態に係る電源システムの構成を示す図である。FIG. 6 is a diagram showing the configuration of a power supply system according to the second embodiment. 図７は、第２実施形態に係る電源システムの別構成例を示す図である。FIG. 7 is a diagram showing another configuration example of the power supply system according to the second embodiment.
＜１．比較例＞
　ここでは、リニア電源装置の新規な実施形態を説明する前に、これと対比される比較例について説明する。 <1. Comparative example>
Here, before describing a new embodiment of a linear power supply device, a comparative example to be compared with this will be described.
　図１は、比較例に係る電源システム５０の構成を示す図である。電源システム５０は、リニア電源装置１０Ａと、リニア電源装置１０Ｂと、抵抗Ｒａ，Ｒｂと、を備える。電源システム５０は、２つのリニア電源装置１０Ａ，１０Ｂを用いて負荷ＲＬに対して負荷電流Ｉｏｕｔを供給する。 FIG. 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example. The power supply system 50 includes a linear power supply device 10A, a linear power supply device 10B, and resistors Ra and Rb. Power supply system 50 supplies load current Iout to load RL using two linear power supplies 10A and 10B.
　リニア電源装置１０Ａ，１０Ｂは、それぞれ入力電圧Ｖｉｎを降圧して所望の出力電圧ＶｏＡ，ＶｏＢを生成するリニアレギュレータである。なお、リニア電源装置１０Ａとリニア電源装置１０Ｂは、同一の構成のＩＣ（Integrated　Circuit）であり、それぞれの対応する構成要素には、同一の符号に対して“Ａ”または“Ｂ”を付して図示している。以下では、リニア電源装置１０Ａの構成について代表的に説明する。 The linear power supplies 10A and 10B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively. Note that the linear power supply device 10A and the linear power supply device 10B are ICs (Integrated Circuits) with the same configuration, and corresponding components are designated with "A" or "B" for the same reference numerals. It is illustrated. Below, the configuration of the linear power supply device 10A will be representatively explained.
　図１に示すように、リニア電源装置１０Ａは、出力トランジスタＭ１０Ａと、抵抗Ｒ１１Ａ，１２Ａと、エラーアンプＡＰ１０Ａと、を備え、これらを１チップに集積したＩＣである。 As shown in FIG. 1, the linear power supply device 10A is an IC that includes an output transistor M10A, resistors R11A and 12A, and an error amplifier AP10A, and integrates these into one chip.
　ＰＭＯＳトランジスタ（ＰチャネルＭＯＳＦＥＴ（metal-oxide-semiconductor　field-effect　transistor））として構成される出力トランジスタＭ１０Ａのソースは、入力電圧Ｖｉｎの入力端に接続されている。出力トランジスタＭ１０Ａのドレインと抵抗Ｒ１１Ａの第１端は、出力電圧ＶｏＡを出力するための出力端子ＴoＡに共通接続されている。抵抗Ｒ１１Ａの第２端は、抵抗Ｒ１２Ａの第１端に接続されている。抵抗Ｒ１２Ａの第２端は、接地端に接続されている。エラーアンプＡＰ１０Ａの非反転入力端（＋）は、抵抗Ｒ１１ＡとＲ１２Ａとが接続される接続ノード（＝帰還電圧ＶｆｂＡの印加端）に接続されている。エラーアンプＡＰ１０Ａの反転入力端（－）は、基準電圧ＶｒｅｆＡの印加端に接続されている。エラーアンプＡＰ１０Ａの出力端は、出力トランジスタＭ１０Ａのゲートに接続されている。 The source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input terminal of the input voltage Vin. The drain of the output transistor M10A and the first end of the resistor R11A are commonly connected to an output terminal ToA for outputting the output voltage VoA. A second end of resistor R11A is connected to a first end of resistor R12A. A second end of the resistor R12A is connected to a ground terminal. The non-inverting input terminal (+) of the error amplifier AP10A is connected to a connection node (=an application terminal of the feedback voltage VfbA) to which the resistors R11A and R12A are connected. The inverting input terminal (-) of the error amplifier AP10A is connected to the application terminal of the reference voltage VrefA. The output terminal of the error amplifier AP10A is connected to the gate of the output transistor M10A.
　上記したエラーアンプＡＰ１０Ａは、出力電圧ＶｏＡに応じた帰還電圧ＶｆｂＡ（＝ＶｏＡ×｛Ｒ１２Ａ／（Ｒ１１Ａ＋Ｒ１２Ａ）｝）が所定の基準電圧ＶｒｅｆＡと一致するように、出力トランジスタＭ１０Ａのゲート制御を行う。すなわち、出力トランジスタＭ１０Ａは、出力電圧ＶｏＡがその目標値（＝ＶｒｅｆＡ×｛（Ｒ１１Ａ＋Ｒ１２Ａ）／Ｒ１２Ａ｝）と一致するように、オン抵抗値が連続的に制御される。 The error amplifier AP10A described above performs gate control of the output transistor M10A so that the feedback voltage VfbA (=VoA×{R12A/(R11A+R12A)}) corresponding to the output voltage VoA matches the predetermined reference voltage VrefA. That is, the on-resistance value of the output transistor M10A is continuously controlled so that the output voltage VoA matches its target value (=VrefA×{(R11A+R12A)/R12A}).
　同様に、リニア電源装置１０Ｂにおいては、出力電圧ＶｏＢがその目標値と一致するように出力トランジスタＭ１０Ｂのオン抵抗値が連続的に制御される。 Similarly, in the linear power supply device 10B, the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.
　出力端子ＴoＡは、リニア電源装置１０Ａ，１０Ｂの外部に設けられる抵抗Ｒａの第１端に接続される。出力端ＴｏＢは、リニア電源装置１０Ａ，１０Ｂの外部に設けられる抵抗Ｒｂの第１端に接続される。抵抗Ｒａ，Ｒｂのそれぞれの第２端は、負荷ＲＬに共通接続される。従って、リニア電源装置１０Ａ，１０Ｂは、共通の負荷ＲＬに対して並列に接続される。 The output terminal ToA is connected to the first end of a resistor Ra provided outside the linear power supply devices 10A and 10B. The output terminal ToB is connected to a first end of a resistor Rb provided outside the linear power supply devices 10A and 10B. The second ends of each of the resistors Ra and Rb are commonly connected to the load RL. Therefore, linear power supplies 10A and 10B are connected in parallel to a common load RL.
　ここで、リニア電源装置１０Ａ，１０Ｂの出力電圧ＶｏＡ，ＶｏＢの標準値（Typ値）は同じに設定しているが、リニア電源装置のばらつきにより、出力電圧は標準値に対してばらつく可能性がある。例えば、標準値５Ｖに対して±２％ばらつく等である。このようなばらつきは、例えば、基準電圧、帰還電圧、または出力トランジスタの閾値電圧のばらつき、さらにエラーアンプの入力オフセット電圧のばらつきなどによって生じる。 Here, the standard values (Typ values) of the output voltages VoA and VoB of the linear power supplies 10A and 10B are set to be the same, but due to variations in the linear power supplies, the output voltage may vary from the standard value. be. For example, it varies by ±2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, as well as variations in the input offset voltage of the error amplifier.
　仮に出力端子ＴoＡ，ＴｏＢ間を直接的に接続した構成の場合、ばらつきにより例えば出力電圧ＶｏＡがＶｏＢよりも高い場合、リニア電源装置１０Ｂ側の出力トランジスタＭ１０Ｂはオフを維持され、出力端ＴｏＢから出力電流ＩｏｕｔＢは出力されず、負荷電流Ｉｏｕｔは、リニア電源装置１０Ａにおける出力端子ＴoＡから出力される出力電流ＩｏｕｔＡのみにより供給される。従って、出力電流が片側のリニア電源装置に集中してしまう。 In the case of a configuration in which the output terminals ToA and ToB are directly connected, for example, if the output voltage VoA is higher than VoB due to variations, the output transistor M10B on the linear power supply 10B side is kept off, and the output is output from the output terminal ToB. The current IoutB is not output, and the load current Iout is supplied only by the output current IoutA output from the output terminal ToA of the linear power supply device 10A. Therefore, the output current is concentrated on one linear power supply device.
　これに対し、図１に示す本比較例に係る構成では、例えば出力電圧ＶｏＡがＶｏＢよりも高い場合、負荷電流Ｉｏｕｔが０Ａより徐々に増加するにつれ、出力電圧ＶｏＡが抵抗Ｒａにより電圧降下され、抵抗Ｒａ，Ｒｂの各第２端が接続されるノードに発生する出力電圧Ｖｏは、徐々に低下する。そして、出力電圧Ｖｏが出力電圧ＶｏＢに到達すると、リニア電源装置１０Ｂ側の出力トランジスタＭ１０Ｂが動作を開始し、出力端ＴｏＢから出力電流ＩｏｕｔＢの出力が開始される。すなわち、出力電流ＩｏｕｔＡ，ＩｏｕｔＢの両方により負荷電流Ｉｏｕｔが供給される並列動作が開始される。なお、抵抗Ｒａ，Ｒｂは、抵抗における電圧降下が、出力電圧のばらつきによる最大値と最小値の間の電圧差以上となるような抵抗値に設定すればよい。 On the other hand, in the configuration according to the present comparative example shown in FIG. 1, for example, when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0 A, the output voltage VoA is dropped by the resistor Ra. The output voltage Vo generated at the node to which the second ends of the resistors Ra and Rb are connected gradually decreases. Then, when the output voltage Vo reaches the output voltage VoB, the output transistor M10B on the linear power supply device 10B side starts operating, and the output of the output current IoutB is started from the output terminal ToB. That is, a parallel operation is started in which the load current Iout is supplied by both the output currents IoutA and IoutB. Note that the resistors Ra and Rb may be set to such resistance values that the voltage drop across the resistors is greater than or equal to the voltage difference between the maximum and minimum values due to variations in the output voltage.
　このように、本比較例の構成であれば、２つのリニア電源装置を並列接続して用いる場合において、出力電圧のばらつきがある場合でも、並列動作が可能となる。しかしながら、このような本比較例では、抵抗Ｒａ，Ｒｂによる損失・発熱が発生すること、出力電流ＩｏｕｔＡ，ＩｏｕｔＢが均等にならないといった課題を有している。また、負荷電流Ｉｏｕｔが変化すると抵抗Ｒａ，Ｒｂによる電圧降下により出力電圧Ｖｏが変化してしまい、レギュレータとしての機能に課題が生じる。 As described above, with the configuration of this comparative example, when two linear power supply devices are connected in parallel and used, parallel operation is possible even when there are variations in output voltage. However, this comparative example has problems in that loss and heat generation occur due to the resistors Ra and Rb, and that the output currents IoutA and IoutB are not equal. Further, when the load current Iout changes, the output voltage Vo changes due to the voltage drop caused by the resistors Ra and Rb, causing a problem in the function as a regulator.
＜２．第１実施形態＞
　以下では、上記の課題を解決できる各種実施形態について説明する。図２は、第１実施形態に係る電源システム５の構成を示す図である。電源システム５は、リニア電源装置１Ａと、リニア電源装置１Ｂと、を備える。電源システム５は、２つのリニア電源装置１Ａ，１Ｂを用いて負荷ＲＬに対して負荷電流Ｉｏｕｔを供給する。 <2. First embodiment>
Below, various embodiments that can solve the above problems will be described. FIG. 2 is a diagram showing the configuration of the power supply system 5 according to the first embodiment. The power supply system 5 includes a linear power supply device 1A and a linear power supply device 1B. The power supply system 5 supplies a load current Iout to the load RL using two linear power supplies 1A and 1B.
　リニア電源装置１Ａ，１Ｂは、それぞれ入力電圧Ｖｉｎを降圧して所望の出力電圧ＶｏＡ，ＶｏＢを生成するリニアレギュレータである。なお、リニア電源装置１Ａとリニア電源装置１Ｂは、同一の構成のＩＣであり、それぞれの対応する構成要素には、同一の符号に対して“Ａ”または“Ｂ”を付して図示している。以下では、リニア電源装置１Ａの構成について代表的に説明する。 The linear power supplies 1A and 1B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively. Note that the linear power supply device 1A and the linear power supply device 1B are ICs with the same configuration, and corresponding components are shown with "A" or "B" attached to the same reference numerals. There is. Below, the configuration of the linear power supply device 1A will be representatively explained.
　図２に示すように、リニア電源装置１Ａは、出力トランジスタＭ１Ａと、ミラートランジスタＭ２Ａと、エラーアンプＡＰ１Ａと、帰還抵抗Ｒ１Ａ，Ｒ２Ａ，Ｒ３Ａ，Ｒ４Ａと、バイパススイッチＢＰＡと、センス抵抗ＲｓＡと、コンパレータＣＰＡと、ＮＭＯＳトランジスタ（ＮチャネルＭＯＳＦＥＴ）ＮＭＡと、抵抗ＲＡと、ＮＭＯＳスイッチＮＳ１Ａ，ＮＳ２Ａと、ＰＭＯＳスイッチＰＭＡと、を備え、これらを１チップに集積したＩＣである。また、リニア電源装置１Ａは、外部との電気的接続を確立するために、出力端子ＴｏＡ、電圧情報送受信端子ＴｖＡ等の外部端子を有している。 As shown in FIG. 2, the linear power supply device 1A includes an output transistor M1A, a mirror transistor M2A, an error amplifier AP1A, feedback resistors R1A, R2A, R3A, R4A, a bypass switch BPA, a sense resistor RsA, and a comparator. This IC includes a CPA, an NMOS transistor (N-channel MOSFET) NMA, a resistor RA, NMOS switches NS1A, NS2A, and a PMOS switch PMA, and these are integrated into one chip. Furthermore, the linear power supply device 1A has external terminals such as an output terminal ToA and a voltage information transmission/reception terminal TvA in order to establish electrical connection with the outside.
　ＰＭＯＳトランジスタとして構成される出力トランジスタＭ１Ａのソースは、入力電圧Ｖｉｎの印加端に接続される。出力トランジスタＭ１Ａのドレインは、帰還抵抗Ｒ１Ａの第１端に接続される。出力トランジスタＭ１Ａのドレインは、出力電圧ＶｏＡを出力するための出力端子ＴｏＡに接続される。帰還抵抗Ｒ１Ａの第２端は、帰還抵抗Ｒ２Ａの第１端に接続される。帰還抵抗Ｒ２Ａの第２端は、帰還抵抗Ｒ３Ａの第１端に接続される。帰還抵抗Ｒ３Ａの第２端は、帰還抵抗Ｒ４Ａの第１端に接続される。帰還抵抗Ｒ４Ａの第２端は、接地端に接続される。 The source of the output transistor M1A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin. The drain of output transistor M1A is connected to the first end of feedback resistor R1A. The drain of the output transistor M1A is connected to an output terminal ToA for outputting an output voltage VoA. A second end of feedback resistor R1A is connected to a first end of feedback resistor R2A. A second end of feedback resistor R2A is connected to a first end of feedback resistor R3A. A second end of feedback resistor R3A is connected to a first end of feedback resistor R4A. A second end of the feedback resistor R4A is connected to a ground terminal.
　エラーアンプＡＰ１Ａの非反転入力端（＋）は、抵抗Ｒ２ＡとＲ３Ａとが接続される接続ノード（＝帰還電圧ＶｆｂＡの印加端）に接続されている。エラーアンプＡＰ１Ａの反転入力端（－）は、基準電圧ＶｒｅｆＡの印加端に接続されている。エラーアンプＡＰ１Ａの出力端は、出力トランジスタＭ１Ａのゲートに接続されている。 The non-inverting input terminal (+) of the error amplifier AP1A is connected to the connection node (=the application terminal of the feedback voltage VfbA) to which the resistors R2A and R3A are connected. The inverting input terminal (-) of the error amplifier AP1A is connected to the application terminal of the reference voltage VrefA. The output terminal of the error amplifier AP1A is connected to the gate of the output transistor M1A.
　ＮＭＯＳトランジスタにより構成されるバイパススイッチＢＰＡのドレインは、帰還抵抗Ｒ４Ａの第１端に接続される。バイパススイッチＢＰＡのソースは、帰還抵抗Ｒ４Ａの第２端に接続される。バイパススイッチＢＰＡのゲートは、制御信号ＳｃＡの印加端に接続される。これにより、制御信号ＳｃＡに応じてバイパススイッチＢＰＡのオン状態／オフ状態が切り替えられる。バイパススイッチＢＰＡがオン状態の場合、帰還抵抗Ｒ４Ａの両端間がショートされ、帰還抵抗Ｒ４Ａはバイパスされる。一方、バイパススイッチＢＰＡがオフ状態の場合、帰還抵抗Ｒ４Ａは有効となる。 The drain of the bypass switch BPA constituted by an NMOS transistor is connected to the first end of the feedback resistor R4A. The source of bypass switch BPA is connected to the second end of feedback resistor R4A. A gate of bypass switch BPA is connected to an application terminal of control signal ScA. Thereby, the on state/off state of the bypass switch BPA is switched according to the control signal ScA. When the bypass switch BPA is in the on state, both ends of the feedback resistor R4A are short-circuited, and the feedback resistor R4A is bypassed. On the other hand, when the bypass switch BPA is in the off state, the feedback resistor R4A is enabled.
　帰還抵抗Ｒ４Ａがバイパスされている場合は、上記したエラーアンプＡＰ１Ａは、出力電圧ＶｏＡに応じた帰還電圧ＶｆｂＡ（＝ＶｏＡ×｛Ｒ３Ａ／（Ｒ１Ａ＋Ｒ２Ａ＋Ｒ３Ａ）｝）が所定の基準電圧ＶｒｅｆＡと一致するように、出力トランジスタＭ１Ａのゲート制御を行う。すなわち、出力トランジスタＭ１Ａは、出力電圧ＶｏＡがその目標値（＝ＶｒｅｆＡ×｛（Ｒ１Ａ＋Ｒ２Ａ＋Ｒ３Ａ）／（Ｒ３Ａ）｝）と一致するように、オン抵抗値が連続的に制御される。 When the feedback resistor R4A is bypassed, the error amplifier AP1A described above operates so that the feedback voltage VfbA (=VoA×{R3A/(R1A+R2A+R3A)}) corresponding to the output voltage VoA matches the predetermined reference voltage VrefA. , controls the gate of the output transistor M1A. That is, the on-resistance value of the output transistor M1A is continuously controlled so that the output voltage VoA matches its target value (=VrefA×{(R1A+R2A+R3A)/(R3A)}).
　帰還抵抗Ｒ４Ａがバイパスされていない場合は、上記したエラーアンプＡＰ１Ａは、出力電圧ＶｏＡに応じた帰還電圧ＶｆｂＡ（＝ＶｏＡ×｛（Ｒ３Ａ＋Ｒ４Ａ）／（Ｒ１Ａ＋Ｒ２Ａ＋Ｒ３Ａ＋Ｒ４Ａ）｝）が所定の基準電圧ＶｒｅｆＡと一致するように、出力トランジスタＭ１Ａのゲート制御を行う。すなわち、出力トランジスタＭ１Ａは、出力電圧ＶｏＡがその目標値（＝ＶｒｅｆＡ×｛（Ｒ１Ａ＋Ｒ２Ａ＋Ｒ３Ａ＋Ｒ４Ａ）／（Ｒ３Ａ＋Ｒ４Ａ）｝）と一致するように、オン抵抗値が連続的に制御される。 When the feedback resistor R4A is not bypassed, the error amplifier AP1A described above has a feedback voltage VfbA (=VoA×{(R3A+R4A)/(R1A+R2A+R3A+R4A)}) corresponding to the output voltage VoA that matches the predetermined reference voltage VrefA. The gate of the output transistor M1A is controlled as follows. That is, the on-resistance value of the output transistor M1A is continuously controlled so that the output voltage VoA matches its target value (=VrefA×{(R1A+R2A+R3A+R4A)/(R3A+R4A)}).
　ＰＭＯＳトランジスタとして構成されるミラートランジスタＭ２Ａのソースは、入力電圧Ｖｉｎの印加端に接続される。ミラートランジスタＭ２Ａのドレインは、センス抵抗ＲｓＡの第１端に接続される。ミラートランジスタＭ２Ａのゲートは、エラーアンプＡＰ１Ａの出力端に接続される。センス抵抗ＲｓＡの第２端は、接地端に接続される。センス抵抗ＲｓＡの第１端は、ＮＭＯＳトランジスタとして構成されるＮＭＯＳスイッチＮＳ１Ａのドレインに接続される。ＮＭＯＳスイッチＮＳ１Ａのソースは、電圧情報送受信端子ＴｖＡに接続される。ＮＭＯＳスイッチＮＳ１Ａのゲートは、制御信号ＳｃＡの印加端に接続される。制御信号ＳｃＡによりＮＭＯＳスイッチＮＳ１Ａのオン状態／オフ状態が切り替えられる。 The source of the mirror transistor M2A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin. The drain of mirror transistor M2A is connected to the first end of sense resistor RsA. The gate of mirror transistor M2A is connected to the output terminal of error amplifier AP1A. A second end of the sense resistor RsA is connected to a ground terminal. A first end of the sense resistor RsA is connected to the drain of an NMOS switch NS1A configured as an NMOS transistor. The source of the NMOS switch NS1A is connected to the voltage information transmission/reception terminal TvA. The gate of the NMOS switch NS1A is connected to the application terminal of the control signal ScA. The on/off state of the NMOS switch NS1A is switched by the control signal ScA.
　出力トランジスタＭ１Ａに流れる電流のミラー電流Ｉｍ２ＡがミラートランジスタＭ２Ａを流れる。ミラー電流Ｉｍ２Ａは、例えば出力トランジスタＭ１Ａを流れる電流の数百分の１、あるいは数千分の１である。ＮＭＯＳスイッチＮＳ１Ａがオン状態の場合、ミラー電流Ｉｍ２Ａをセンス抵抗ＲｓＡにより電流／電圧変換して得られる電圧情報ＶｍｏｎがＮＭＯＳスイッチＮＳ１Ａを介して電圧送受信端子ＴｖＡから外部へ出力可能となる。 A mirror current Im2A of the current flowing through the output transistor M1A flows through the mirror transistor M2A. The mirror current Im2A is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1A. When the NMOS switch NS1A is in the on state, voltage information Vmon obtained by converting the mirror current Im2A into a current/voltage by the sense resistor RsA can be outputted to the outside from the voltage transmitting/receiving terminal TvA via the NMOS switch NS1A.
　コンパレータＣＰＡは、ＰＭＯＳトランジスタＰ１，Ｐ２と、ＮＭＯＳトランジスタＮ１，Ｎ２と、を有する。ＰＭＯＳトランジスタＰ１，Ｐ２のソースは、ＰＭＯＳスイッチＰＭＡのドレインに接続される。ＰＭＯＳトランジスタＰ１のゲートは、電圧情報送受信端子ＴｖＡに接続される。ＰＭＯＳトランジスタＰ２のゲートは、センス抵抗ＲｓＡの第１端に接続される。ＰＭＯＳトランジスタＰ１のドレインは、ＮＭＯＳトランジスタＮ１のドレインに接続される。ＮＭＯＳトランジスタＮ１のドレインとゲートは短絡される。ＮＭＯＳトランジスタＮ１，Ｎ２のゲート同士は接続される。ＮＭＯＳトランジスタＮ１，Ｎ２のソースは、接地端に接続される。ＮＭＯＳトランジスタＮ２のドレインとＰＭＯＳトランジスタＰ２のドレインは、ノードＮｄで接続される。なお、ＮＭＯＳトランジスタＮ２のゲートとドレイン間には、位相補償用のコンデンサＣ１が接続される。 The comparator CPA includes PMOS transistors P1 and P2 and NMOS transistors N1 and N2. The sources of PMOS transistors P1 and P2 are connected to the drain of PMOS switch PMA. The gate of PMOS transistor P1 is connected to voltage information transmission/reception terminal TvA. The gate of PMOS transistor P2 is connected to the first end of sense resistor RsA. The drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1. The drain and gate of NMOS transistor N1 are shorted. The gates of NMOS transistors N1 and N2 are connected to each other. The sources of NMOS transistors N1 and N2 are connected to a ground terminal. The drain of the NMOS transistor N2 and the drain of the PMOS transistor P2 are connected at a node Nd. Note that a phase compensation capacitor C1 is connected between the gate and drain of the NMOS transistor N2.
　ＮＭＯＳトランジスタＮＭＡのゲートは、ノードＮｄに接続される。ＮＭＯＳトランジスタＮＭＡのソースは、抵抗ＲＡを介して接地端に接続される。ＮＭＯＳトランジスタＮＭＡのドレインは、帰還抵抗Ｒ１Ａ，Ｒ２Ａが接続されるノードＮＤＡに接続される。なお、ＮＭＯＳトランジスタＮＭＡのゲートとドレイン間には、位相補償用のコンデンサＣ２が接続される。 The gate of NMOS transistor NMA is connected to node Nd. The source of the NMOS transistor NMA is connected to a ground terminal via a resistor RA. The drain of the NMOS transistor NMA is connected to a node NDA to which feedback resistors R1A and R2A are connected. Note that a phase compensation capacitor C2 is connected between the gate and drain of the NMOS transistor NMA.
　ＮＭＯＳスイッチＮＳ２Ａのドレインは、ＮＭＯＳトランジスタＮＭＡのゲートに接続される。ＮＭＯＳスイッチＮＳ２Ａのソースは、接地端に接続される。ＰＭＯＳスイッチＰＭＡのゲートおよびＮＭＯＳスイッチＮＳ２Ａのゲートは、制御信号ＳｃＡの印加端に接続される。制御信号ＳｃＡによりＰＭＯＳスイッチＰＭＡおよびＮＭＯＳスイッチＮＳ２Ａのオン状態／オフ状態が切り替えられる。 The drain of the NMOS switch NS2A is connected to the gate of the NMOS transistor NMA. The source of NMOS switch NS2A is connected to the ground terminal. The gate of the PMOS switch PMA and the gate of the NMOS switch NS2A are connected to the application terminal of the control signal ScA. The control signal ScA switches the on state/off state of the PMOS switch PMA and the NMOS switch NS2A.
　制御信号ＳｃＡがローレベルの場合、ＮＭＯＳスイッチＮＳ１Ａはオフ状態、ＰＭＯＳスイッチＰＭＡはオン状態、ＮＭＯＳスイッチＮＳ２Ａはオフ状態となる。この場合、外部から電圧情報送受信端子ＴｖＡに入力された電圧情報ＶｍｏｎがＰＭＯＳトランジスタＰ１のゲートに印加され、ミラー電流Ｉｍ２Ａをセンス抵抗ＲｓＡにより電流電圧変換して得られる電圧情報ＶｓがＰＭＯＳトランジスタＰ２のゲートに印加される。コンパレータＣＰＡにより電圧情報ＶｓとＶｍｏｎの比較が行われ、比較結果に基づきＮＭＯＳトランジスタＮＭＡのゲートが駆動される。ＮＭＯＳトランジスタＮＭＡのドレインはノードＮＤＡに接続されているため、電圧情報ＶｓとＶｍｏｎが一致するように出力電圧ＶｏＡが制御される。 When the control signal ScA is at a low level, the NMOS switch NS1A is in the off state, the PMOS switch PMA is in the on state, and the NMOS switch NS2A is in the off state. In this case, voltage information Vmon input from the outside to the voltage information transmitting/receiving terminal TvA is applied to the gate of the PMOS transistor P1, and voltage information Vs obtained by converting the mirror current Im2A into a voltage by the sense resistor RsA is applied to the gate of the PMOS transistor P2. Applied to the gate. The voltage information Vs and Vmon are compared by the comparator CPA, and the gate of the NMOS transistor NMA is driven based on the comparison result. Since the drain of the NMOS transistor NMA is connected to the node NDA, the output voltage VoA is controlled so that the voltage information Vs and Vmon match.
　図３は、リニア電源装置１Ａに備えられるＯＲ回路Ｏｒを示す図である。ＯＲ回路Ｏｒには、保護信号Ｐ１～Ｐｎ、イネーブル信号Ｅｎ、およびマスター／スレーブ選択信号ＭＳが入力される。ＯＲ回路Ｏｒから制御信号ＳｃＡが出力される。保護信号Ｐ１～Ｐｎ、イネーブル信号Ｅｎ、およびマスター／スレーブ選択信号ＭＳのいずれかがハイレベルの場合に、制御信号ＳｃＡがハイレベルとなる。なお、ＯＲ回路に限らず、ＮＡＮＤ回路等、他の論理回路により構成してもよい。 FIG. 3 is a diagram showing an OR circuit Or provided in the linear power supply device 1A. The protection signals P1 to Pn, the enable signal En, and the master/slave selection signal MS are input to the OR circuit Or. A control signal ScA is output from the OR circuit Or. When any one of the protection signals P1 to Pn, the enable signal En, and the master/slave selection signal MS is at a high level, the control signal ScA is at a high level. Note that the configuration is not limited to the OR circuit, but may be configured using other logic circuits such as a NAND circuit.
　図２に示す電源システム５では、リニア電源装置１Ａの出力端子ＴｏＡとリニア電源装置１Ｂの出力端子ＴｏＢが負荷ＲＬに共通接続される。すなわち、２つのリニア電源装置が負荷ＲＬに対して並列接続される。また、リニア電源装置１Ａの電圧情報送受信端子ＴｖＡとリニア電源装置１Ｂの電圧情報送受信端子ＴｖＢとが接続される。 In the power supply system 5 shown in FIG. 2, the output terminal ToA of the linear power supply device 1A and the output terminal ToB of the linear power supply device 1B are commonly connected to the load RL. That is, two linear power supplies are connected in parallel to the load RL. Further, the voltage information transmitting/receiving terminal TvA of the linear power supply device 1A and the voltage information transmitting/receiving terminal TvB of the linear power supply device 1B are connected.
　リニア電源装置１Ａ，１Ｂのうち一方がマスターに設定され、他方がスレーブに設定される。ここでは、リニア電源装置１Ａがマスターに、リニア電源装置１Ｂがスレーブに設定されるとする。 One of the linear power supply devices 1A and 1B is set as a master, and the other is set as a slave. Here, it is assumed that the linear power supply device 1A is set as the master and the linear power supply device 1B is set as the slave.
　マスター／スレーブ選択信号ＭＳをハイレベルとすることでリニア電源装置１Ａがマスターに設定される（図２）。この場合、制御信号ＳｃＡがハイレベルとなり、ＮＭＯＳスイッチＮＳ１Ａがオン状態、ＰＭＯＳスイッチＰＭＡがオフ状態、ＮＭＯＳスイッチＮＳ２Ａがオン状態となる。これにより、電圧情報Ｖｍｏｎを電圧情報送受信端子ＴｖＡから出力可能となる。また、コンパレータＣＰＡに電流が供給されずコンパレータＣＰＡが無効となり、ＮＭＯＳトランジスタＮＭＡのゲートはローベルとなる。また、バイパススイッチＢＰＡがオン状態となり、帰還抵抗Ｒ４Ａがバイパスされる。 By setting the master/slave selection signal MS to a high level, the linear power supply device 1A is set as the master (FIG. 2). In this case, the control signal ScA becomes high level, the NMOS switch NS1A is turned on, the PMOS switch PMA is turned off, and the NMOS switch NS2A is turned on. This allows the voltage information Vmon to be output from the voltage information transmission/reception terminal TvA. Further, no current is supplied to the comparator CPA, making the comparator CPA ineffective, and the gate of the NMOS transistor NMA becomes a low level. Further, the bypass switch BPA is turned on, and the feedback resistor R4A is bypassed.
　マスター／スレーブ選択信号ＭＳをローレベルとすることでリニア電源装置１Ｂがスレーブに設定される（図２）。この場合、制御信号ＳｃＢがローレベルとなり、ＮＭＯＳスイッチＮＳ１Ｂがオフ状態、ＰＭＯＳスイッチＰＭＢがオン状態、ＮＭＯＳスイッチＮＳ２Ｂがオフ状態となる。これにより、コンパレータＣＰＢに電流が供給されてコンパレータＣＰＢが有効となり、電圧情報ＶｓとＶｍｏｎの比較が可能となる。ＮＭＯＳトランジスタＮＭＢは有効となる。また、バイパススイッチＢＰＢがオフ状態となり、帰還抵抗Ｒ４Ｂが有効となる。 By setting the master/slave selection signal MS to a low level, the linear power supply device 1B is set as a slave (FIG. 2). In this case, the control signal ScB becomes a low level, the NMOS switch NS1B is turned off, the PMOS switch PMB is turned on, and the NMOS switch NS2B is turned off. As a result, a current is supplied to the comparator CPB, and the comparator CPB becomes valid, making it possible to compare the voltage information Vs and Vmon. NMOS transistor NMB becomes valid. Further, the bypass switch BPB is turned off, and the feedback resistor R4B is enabled.
　帰還抵抗Ｒ４Ｂはバイパスされないため、バイパスされる場合よりも出力電圧ＶｏＢは低い目標値に制御される。帰還抵抗Ｒ４Ａ，Ｒ４Ｂは、出力電圧のばらつきによる最大値と最小値の間の電圧差以上となるような抵抗値に設定すればよい。これにより、出力電圧ＶｏＡ，ＶｏＢにばらつきがあっても、出力電圧ＶｏＢをＶｏＡよりも低く設定することができる。 Since the feedback resistor R4B is not bypassed, the output voltage VoB is controlled to a lower target value than when it is bypassed. The feedback resistors R4A and R4B may be set to a resistance value that is greater than or equal to the voltage difference between the maximum value and the minimum value due to variations in the output voltage. Thereby, even if there are variations in the output voltages VoA and VoB, the output voltage VoB can be set lower than VoA.
　これにより、負荷電流Ｉｏｕｔを０Ａから流し始めても、リニア電源装置１Ｂにおける出力端子ＴｏＢから出力電流ＩｏｕｔＢは出力されず、リニア電源装置１Ａにおける出力端子ＴｏＡから出力される出力電流ＩｏｕｔＡのみにより負荷電流Ｉｏｕｔが供給される。 As a result, even if the load current Iout starts to flow from 0A, the output current IoutB is not output from the output terminal ToB of the linear power supply 1B, and the load current Iout is caused only by the output current IoutA output from the output terminal ToA of the linear power supply 1A. is supplied.
　このとき、マスターであるリニア電源装置１Ａの電圧情報送受信端子ＴｖＡから出力されてスレーブであるリニア電源装置１Ｂの電圧情報送受信端子ＴｖＢに入力された電圧情報Ｖｍｏｎと、電圧情報Ｖｓとがリニア電源装置１ＢにおけるコンパレータＣＰＢにより比較される。リニア電源装置１Ｂにおいてミラー電流Ｉｍ２Ｂが流れないため、Ｖｓ＝０となり、ＮＭＯＳトランジスタＮＭＢの駆動により出力電圧ＶｏＢは上昇するように制御される。 At this time, the voltage information Vmon outputted from the voltage information transmitting/receiving terminal TvA of the master linear power supply 1A and input to the voltage information transmitting/receiving terminal TvB of the slave linear power supply 1B and the voltage information Vs are connected to the linear power supply Comparison is made by comparator CPB in 1B. Since the mirror current Im2B does not flow in the linear power supply device 1B, Vs=0, and the output voltage VoB is controlled to rise by driving the NMOS transistor NMB.
　負荷電流Ｉｏｕｔが増加し、出力電流ＩｏｕｔＡひいてはミラー電流Ｉｍ２Ａが増加するにつれ、出力電圧ＶｏＢが上昇する。そして、出力電圧ＶｏＢがＶｏＡに到達すると、リニア電源装置１Ｂにおける出力端子ＴｏＢから出力電流ＩｏｕｔＢが出力され始める。すなわち、リニア電源装置１Ａ，１Ｂの並列動作が開始される。 As the load current Iout increases and the output current IoutA and thus the mirror current Im2A increase, the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
　出力電流ＩｏｕｔＢが流れ始めると、ミラー電流Ｉｍ２Ｂも流れ始め、電圧情報ＶｓとＶｍｏｎの比較によりＮＭＯＳトランジスタＮＭＢの駆動により、電圧情報ＶｓとＶｍｏｎが一致するように、すなわち出力電流ＩｏｕｔＢとＩｏｕｔＡが一致するように制御される。 When the output current IoutB starts flowing, the mirror current Im2B also starts flowing, and by driving the NMOS transistor NMB by comparing the voltage information Vs and Vmon, the voltage information Vs and Vmon match, that is, the output currents IoutB and IoutA match. controlled as follows.
　これにより、リニア電源装置１Ａ，１Ｂで出力電圧のばらつきがあった場合でも、並列動作を可能とし、出力電流を均等に近づけることができる。また、負荷電流の変化に対する出力電圧の変化を抑制できる。さらに、先述の比較例のような電圧降下のための抵抗が不要であり、損失・発熱を抑制することができる。また、このような効果を同一品番のリニア電源装置により実現することができる。 As a result, even if there are variations in output voltage between the linear power supplies 1A and 1B, parallel operation is possible and the output currents can be made close to equal. Further, changes in output voltage due to changes in load current can be suppressed. Furthermore, there is no need for a resistor for voltage drop as in the above-mentioned comparative example, and loss and heat generation can be suppressed. Moreover, such an effect can be achieved using linear power supply devices of the same product number.
　なお、図４に示す電源システム５のように、負荷ＲＬに対して３つのリニア電源装置を並列接続してもよい。図４に示すリニア電源装置１Ａ，１Ｂ，１Ｃの出力端子ＴｏＡ，ＴｏＢ，ＴｏＣは、負荷ＲＬに共通接続される。また、リニア電源装置１Ａ，１Ｂ，１Ｃの電圧情報送受信端子ＴｖＡ，ＴｖＢ，ＴｖＣが接続される。 Note that, like the power supply system 5 shown in FIG. 4, three linear power supply devices may be connected in parallel to the load RL. Output terminals ToA, ToB, and ToC of linear power supplies 1A, 1B, and 1C shown in FIG. 4 are commonly connected to a load RL. Further, voltage information transmitting/receiving terminals TvA, TvB, and TvC of the linear power supplies 1A, 1B, and 1C are connected.
　図４に示すような構成において、例えばリニア電源装置１Ａがマスターに、リニア電源装置１Ｂ，１Ｃがスレーブに設定される。リニア電源装置１Ａ，１Ｂ，１Ｃの出力電流ＩｏｕｔＡ，ＩｏｕｔＢ，ＩｏｕｔＣが一致するように制御される（すなわち出力電流ＩｏｕｔＡ，ＩｏｕｔＢ，ＩｏｕｔＣはそれぞれ負荷電流Ｉｏｕｔの１／３に制御される）。 In the configuration shown in FIG. 4, for example, the linear power supply device 1A is set as a master, and the linear power supply devices 1B and 1C are set as slaves. The output currents IoutA, IoutB, and IoutC of the linear power supplies 1A, 1B, and 1C are controlled to match (that is, the output currents IoutA, IoutB, and IoutC are each controlled to ⅓ of the load current Iout).
　図４に示す構成における起動時の概略的な電流波形を図５に示す。図５に示すように、まずマスターであるリニア電源装置１Ａの出力電流ＩｏｕｔＡが立ち上がってから、出力電流ＩｏｕｔＢ，ＩｏｕｔＣが立ち上がる。そして、出力電流ＩｏｕｔＡ，ＩｏｕｔＢ，ＩｏｕｔＣが一致するように制御される。 FIG. 5 shows a schematic current waveform at startup in the configuration shown in FIG. 4. As shown in FIG. 5, first, the output current IoutA of the master linear power supply device 1A rises, and then the output currents IoutB and IoutC rise. Then, the output currents IoutA, IoutB, and IoutC are controlled to match.
　なお、スレーブに設定されるリニア電源装置を３つ以上設けてもよい。すなわち、マスターに設定されるリニア電源装置に対してスレーブに設定されるリニア電源装置を２つ以上設けることが可能である。マスターのリニア電源装置から出力される電圧情報Ｖｍｏｎは、電流ではなく電圧の信号であるため、２つ以上のスレーブのリニア電源装置によって信号が分割されることはなく、各リニア電源装置の出力電流を均等にすることができる。 Note that three or more linear power supply devices may be provided as slaves. That is, it is possible to provide two or more linear power supply devices that are set as slaves for a linear power supply device that is set as a master. Since the voltage information Vmon output from the master linear power supply is a voltage signal rather than a current signal, the signal is not divided by two or more slave linear power supply devices, and the output current of each linear power supply can be made equal.
＜３．第２実施形態＞
　図６は、第２実施形態に係る電源システム５の構成を示す図である。ここでは、本実施形態に係る構成の第１実施形態（図２）との相違点について主に述べる。また、リニア電源装置１Ａ，１Ｂのうちリニア電源装置１Ａの構成について代表的に説明する。 <3. Second embodiment>
FIG. 6 is a diagram showing the configuration of a power supply system 5 according to the second embodiment. Here, differences between the configuration of this embodiment and the first embodiment (FIG. 2) will be mainly described. Furthermore, the configuration of the linear power supply device 1A among the linear power supply devices 1A and 1B will be representatively explained.
　図６に示すリニア電源装置１Ａでは、ＮＭＯＳスイッチＮＳ１Ａは設けず、センス抵抗ＲｓＡの第１端が外部端子である電圧ソース端子ＴｓｒＡに接続される。電圧ソース端子ＴｓｒＡは、ミラー電流Ｉｍ２Ａをセンス抵抗ＲｓＡにより電流電圧変換して得られる電圧情報ＶｍｏｎＡを外部へ出力するための端子である。 In the linear power supply device 1A shown in FIG. 6, the NMOS switch NS1A is not provided, and the first end of the sense resistor RsA is connected to the voltage source terminal TsrA, which is an external terminal. The voltage source terminal TsrA is a terminal for outputting to the outside voltage information VmonA obtained by converting the mirror current Im2A into a current voltage using the sense resistor RsA.
　また、ＰＭＯＳトランジスタＰ１のゲートは、電圧シンク端子ＴｓｋＡに接続される。電圧シンク端子ＴｓｋＡは、電圧情報Ｖｍｏｎを外部から入力するための端子である。電圧ソース端子ＴｓｒＡと電圧シンク端子ＴｓｋＡは、別個の端子である。 Furthermore, the gate of the PMOS transistor P1 is connected to the voltage sink terminal TskA. The voltage sink terminal TskA is a terminal for inputting voltage information Vmon from the outside. Voltage source terminal TsrA and voltage sink terminal TskA are separate terminals.
　また、図６に示すリニア電源装置１Ａでは、帰還抵抗Ｒ４ＡおよびバイパススイッチＢＰＡは設けない。 Further, in the linear power supply device 1A shown in FIG. 6, the feedback resistor R4A and the bypass switch BPA are not provided.
　リニア電源装置１Ａの電圧ソース端子ＴｓｒＡは、リニア電源装置１Ｂの電圧シンク端子ＴｓｋＢに接続される。これにより、電圧ソース端子ＴｓｒＡから出力された電圧情報ＶｍｏｎＡは電圧シンク端子ＴｓｋＢに入力される。リニア電源装置１Ｂにおいて、ミラー電流Ｉｍ２Ｂをセンス抵抗ＲｓＢにより電流電圧変換して得られる電圧情報ＶｓＢと、ＶｍｏｎＡとがコンパレータＣＰＢにより比較される。 The voltage source terminal TsrA of the linear power supply device 1A is connected to the voltage sink terminal TskB of the linear power supply device 1B. Thereby, the voltage information VmonA output from the voltage source terminal TsrA is input to the voltage sink terminal TskB. In the linear power supply device 1B, a comparator CPB compares voltage information VsB obtained by converting the mirror current Im2B into a current voltage using a sense resistor RsB and VmonA.
　リニア電源装置１Ｂの電圧ソース端子ＴｓｒＢは、リニア電源装置１Ａの電圧シンク端子ＴｓｋＡに接続される。これにより、電圧ソース端子ＴｓｒＢから出力された電圧情報ＶｍｏｎＢは電圧シンク端子ＴｓｋＡに入力される。リニア電源装置１Ａにおいて、ミラー電流Ｉｍ２Ａをセンス抵抗ＲｓＡにより電流電圧変換して得られる電圧情報ＶｓＡと、ＶｍｏｎＢとがコンパレータＣＰＡにより比較される。 The voltage source terminal TsrB of the linear power supply device 1B is connected to the voltage sink terminal TskA of the linear power supply device 1A. Thereby, the voltage information VmonB output from the voltage source terminal TsrB is input to the voltage sink terminal TskA. In the linear power supply device 1A, a comparator CPA compares voltage information VsA obtained by converting a mirror current Im2A into a current voltage using a sense resistor RsA and VmonB.
　ここで、リニア電源装置のばらつきによりリニア電源装置１Ａの出力電圧ＶｏＡがリニア電源装置１Ｂの出力電圧ＶｏＢよりも高いとする。これにより、負荷電流Ｉｏｕｔを０Ａから流し始めても、初期にリニア電源装置１Ｂにおける出力端子ＴｏＢから出力電流ＩｏｕｔＢは出力されず、リニア電源装置１Ａにおける出力端子ＴｏＡから出力される出力電流ＩｏｕｔＡのみにより負荷電流Ｉｏｕｔが供給される。 Here, it is assumed that the output voltage VoA of the linear power supply device 1A is higher than the output voltage VoB of the linear power supply device 1B due to variations in the linear power supply device. As a result, even if the load current Iout starts flowing from 0A, the output current IoutB is not initially output from the output terminal ToB of the linear power supply 1B, and the load is caused only by the output current IoutA output from the output terminal ToA of the linear power supply 1A. A current Iout is supplied.
　このとき、ミラー電流Ｉｍ２Ａが流れ、ミラー電流Ｉｍ２Ａに基づく電圧情報ＶｍｏｎＡが電圧ソース端子ＴｓｒＡから出力されて電圧シンク端子ＴｓｋＢに入力される。リニア電源装置１Ｂにおいて、ミラー電流Ｉｍ２Ｂは流れず、電圧情報ＶｓＢとＶｍｏｎＡとがコンパレータＣＰＢにより比較されてＮＭＯＳトランジスタＮＭＢが駆動され、リニア電源装置１Ｂの出力電圧ＶｏＢが上昇する。 At this time, mirror current Im2A flows, and voltage information VmonA based on mirror current Im2A is output from voltage source terminal TsrA and input to voltage sink terminal TskB. In linear power supply device 1B, mirror current Im2B does not flow, voltage information VsB and VmonA are compared by comparator CPB, NMOS transistor NMB is driven, and output voltage VoB of linear power supply device 1B is increased.
　負荷電流Ｉｏｕｔが増加し、出力電流ＩｏｕｔＡひいてはミラー電流Ｉｍ２Ａが増加するにつれ、出力電圧ＶｏＢが上昇する。そして、出力電圧ＶｏＢがＶｏＡに到達すると、リニア電源装置１Ｂにおける出力端子ＴｏＢから出力電流ＩｏｕｔＢが出力され始める。すなわち、リニア電源装置１Ａ，１Ｂの並列動作が開始される。 As the load current Iout increases and the output current IoutA and thus the mirror current Im2A increase, the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
　出力電流ＩｏｕｔＢが流れ始めると、ミラー電流Ｉｍ２Ｂも流れ始め、電圧情報ＶｓＢとＶｍｏｎＡの比較によりＮＭＯＳトランジスタＮＭＢが駆動され、電圧情報ＶｓＢとＶｍｏｎＡが一致するように制御される。一方、リニア電源装置１Ａでは、電圧情報ＶｓＡとＶｍｏｎＢの比較によりＮＭＯＳトランジスタＮＭＡが駆動され、電圧情報ＶｓＡとＶｍｏｎＢが一致するように制御される。これにより、出力電流ＩｏｕｔＡとＩｏｕｔＢが一致するように制御される。 When the output current IoutB starts to flow, the mirror current Im2B also starts to flow, and the NMOS transistor NMB is driven by comparing the voltage information VsB and VmonA, and is controlled so that the voltage information VsB and VmonA match. On the other hand, in the linear power supply device 1A, the NMOS transistor NMA is driven by comparing the voltage information VsA and VmonB, and is controlled so that the voltage information VsA and VmonB match. Thereby, the output currents IoutA and IoutB are controlled to match.
　図７は、第２実施形態に係るリニア電源装置を３つ、負荷ＲＬに対して並列接続して電源システム５を構成した場合を示す図である。ここでは、リニア電源装置１Ａの電圧ソース端子ＴｓｒＡをリニア電源装置１Ｂの電圧シンク端子ＴｓｋＢに接続し、リニア電源装置１Ｂの電圧ソース端子ＴｓｒＢをリニア電源装置１Ｃの電圧シンク端子ＴｓｋＣに接続し、リニア電源装置１Ｃの電圧ソース端子ＴｓｒＣをリニア電源装置１Ａの電圧シンク端子ＴｓｋＡに接続している。 FIG. 7 is a diagram showing a case where three linear power supply devices according to the second embodiment are connected in parallel to a load RL to configure a power supply system 5. Here, the voltage source terminal TsrA of the linear power supply 1A is connected to the voltage sink terminal TskB of the linear power supply 1B, the voltage source terminal TsrB of the linear power supply 1B is connected to the voltage sink terminal TskC of the linear power supply 1C, and the linear A voltage source terminal TsrC of the power supply device 1C is connected to a voltage sink terminal TskA of the linear power supply device 1A.
　このような構成により、リニア電源装置１Ａ，１Ｂ，１Ｃの出力電流ＩｏｕｔＡ，ＩｏｕｔＢ，ＩｏｕｔＣを均等に制御することができる。なお、４つ以上のリニア電源装置１を負荷ＲＬに対して並列接続しても、各出力電流を均等に制御することができる。 With such a configuration, the output currents IoutA, IoutB, and IoutC of the linear power supply devices 1A, 1B, and 1C can be equally controlled. Note that even if four or more linear power supply devices 1 are connected in parallel to the load RL, each output current can be controlled equally.
＜４．その他＞
　なお、本開示に係る種々の技術的特徴は、上記実施形態の他、その技術的創作の主旨を逸脱しない範囲で種々の変更を加えることが可能である。すなわち、上記実施形態は、全ての点で例示であって、制限的なものではないと考えられるべきであり、本発明の技術的範囲は、上記実施形態に限定されるものではなく、特許請求の範囲と均等の意味および範囲内に属する全ての変更が含まれると理解されるべきである。また、上記の各実施形態は、矛盾のない限り、適宜に組み合わせて実施してもよい。 <4. Others＞
Note that the various technical features of the present disclosure can be modified in addition to the embodiments described above without departing from the spirit of the technical creation. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above embodiments, and the claims It is to be understood that the meaning and equivalents of the range and all changes falling within the range are included. Furthermore, the above embodiments may be combined as appropriate unless there is a contradiction.
＜５．付記＞
　以上の通り、例えば、本開示に係るリニア電源装置（１Ａ）は、
　入力電圧（Ｖｉｎ）の印加端に接続可能に構成される第１主電極と、第２主電極と、を有する出力トランジスタ（Ｍ１Ａ）と、
　前記第２主電極に接続される出力端子（ＴｏＡ）と、
　前記出力端子に発生する出力電圧（ＶｏＡ）に基づく帰還電圧（ＶｆｂＡ）と、基準電圧（ＶｒｅｆＡ）とが入力され、前記出力トランジスタの制御端を駆動可能に構成されるエラーアンプ（ＡＰ１Ａ）と、
　前記出力トランジスタに流れる電流のミラー電流（Ｉｍ２Ａ）を生成可能に構成されるミラートランジスタ（Ｍ２Ａ）と、
　前記ミラー電流を第１電圧情報（Ｖｍｏｎ，Ｖｓ）に変換する電流／電圧変換部（ＲｓＡ）と、
　前記第１電圧情報（Ｖｍｏｎ）を外部に対して出力可能に構成される電圧情報出力端子（ＴｖＡ）と、
　第２電圧情報（Ｖｍｏｎ）を外部から入力可能に構成される電圧情報入力端子（ＴｖＡ）と、
　前記第２電圧情報（Ｖｍｏｎ）と前記第１電圧情報（Ｖｓ）とを比較するように構成される比較部（ＣＰＡ）と、
　前記比較部の比較結果に基づき駆動され、前記第２電圧情報と前記第１電圧情報の差が小さくなるように制御する制御トランジスタ（ＮＭＡ）と、
を備える構成としている（第１の構成）。 <5. Additional notes＞
As mentioned above, for example, the linear power supply device (1A) according to the present disclosure,
an output transistor (M1A) having a first main electrode configured to be connectable to an application end of the input voltage (Vin) and a second main electrode;
an output terminal (ToA) connected to the second main electrode;
an error amplifier (AP1A) configured to receive a feedback voltage (VfbA) based on the output voltage (VoA) generated at the output terminal and a reference voltage (VrefA) and to be able to drive a control end of the output transistor;
a mirror transistor (M2A) configured to be able to generate a mirror current (Im2A) of the current flowing through the output transistor;
a current/voltage converter (RsA) that converts the mirror current into first voltage information (Vmon, Vs);
a voltage information output terminal (TvA) configured to be able to output the first voltage information (Vmon) to the outside;
a voltage information input terminal (TvA) configured to be able to input second voltage information (Vmon) from the outside;
a comparison unit (CPA) configured to compare the second voltage information (Vmon) and the first voltage information (Vs);
a control transistor (NMA) that is driven based on the comparison result of the comparison section and controls so that the difference between the second voltage information and the first voltage information becomes small;
(first configuration).
　また、上記第１の構成において、前記制御トランジスタ（ＮＭＡ）の第１主電極は、前記出力トランジスタ（Ｍ１Ａ）の第２主電極に接続される帰還抵抗部（Ｒ１Ａ，Ｒ２Ａ，Ｒ３Ａ，Ｒ４Ａ）に接続される構成としてもよい（第２の構成）。 Further, in the first configuration, the first main electrode of the control transistor (NMA) is connected to the feedback resistor section (R1A, R2A, R3A, R4A) connected to the second main electrode of the output transistor (M1A). A configuration in which they are connected may also be used (second configuration).
　また、上記第１または第２の構成において、前記電圧情報出力端子と前記電圧情報入力端子は同一の端子（ＴｖＡ）であり、
　前記第１電圧情報を前記電圧情報出力端子から出力するか否かを切り替える第１スイッチ（ＮＳ１Ａ）をさらに備え、
　前記第１電圧情報（Ｖｍｏｎ）が外部へ出力される場合、前記第２電圧情報（Ｖｍｏｎ）と前記第１電圧情報（Ｖｓ）の差が小さくなるような制御は機能せず、
　前記第１電圧情報が外部へ出力されない場合、外部から入力された前記第２電圧情報と前記第１電圧情報の差が小さくなるような制御が機能する構成としてもよい（第３の構成）。 Further, in the first or second configuration, the voltage information output terminal and the voltage information input terminal are the same terminal (TvA),
further comprising a first switch (NS1A) for switching whether or not to output the first voltage information from the voltage information output terminal;
When the first voltage information (Vmon) is output to the outside, control that reduces the difference between the second voltage information (Vmon) and the first voltage information (Vs) does not function,
When the first voltage information is not output to the outside, a configuration may be adopted in which control functions such that the difference between the second voltage information input from the outside and the first voltage information becomes small (third configuration).
　また、上記第３の構成において、前記出力トランジスタ（Ｍ１Ａ）の第２主電極に接続される帰還抵抗部の一部の帰還抵抗（Ｒ４Ａ）をバイパスするか否かを切り替える第２スイッチ（ＢＰＡ）をさらに備え、前記第２スイッチは、前記第１スイッチと連動する構成としてもよい（第４の構成）。 Further, in the third configuration, a second switch (BPA) switches whether or not to bypass a part of the feedback resistor (R4A) of the feedback resistor section connected to the second main electrode of the output transistor (M1A). The second switch may be configured to operate in conjunction with the first switch (fourth configuration).
　また、上記第３または第４の構成において、前記比較部（ＣＰＡ）に電流を供給するか否かを切り替える第３スイッチ（ＰＭＡ）をさらに備え、前記第３スイッチは、前記第１スイッチと連動する構成としてもよい（第５の構成）。 Further, in the third or fourth configuration, the third switch (PMA) is further provided for switching whether or not to supply current to the comparing section (CPA), and the third switch is interlocked with the first switch. (fifth configuration).
　また、上記第３から第５のいずれかの構成において、前記制御トランジスタ（ＮＭＡ）の制御端と接地端との間に接続される第４スイッチ（ＮＳ２Ａ）をさらに備え、
　前記第４スイッチは、前記第１スイッチと連動する構成としてもよい（第６の構成）。 Further, in any one of the third to fifth configurations, further comprising a fourth switch (NS2A) connected between the control terminal and the ground terminal of the control transistor (NMA),
The fourth switch may be configured to work in conjunction with the first switch (sixth configuration).
　また、上記第１または第２の構成において、前記電圧情報出力端子（ＴｓｒＡ）と前記電圧情報入力端子（ＴｓｋＡ）は別個の端子である構成としてもよい（第７の構成）。 Furthermore, in the first or second configuration, the voltage information output terminal (TsrA) and the voltage information input terminal (TskA) may be separate terminals (seventh configuration).
　また、本開示の一態様に係る電源システム（５）は、前記第１スイッチ（ＮＳ１Ａ）がオン状態に設定される上記第３の構成のリニア電源装置であるマスターリニア電源装置（１Ａ）と、
　前記第１スイッチがオフ状態に設定される上記第３の構成のリニア電源装置である１つ以上のスレーブリニア電源装置（１Ｂ）と、を備え、
　前記マスターリニア電源装置の前記出力端子（ＴｏＡ）と前記スレーブリニア電源装置の前記出力端子（ＴｏＢ）は、負荷に共通接続可能であり、
　前記マスターリニア電源装置の前記電圧情報出力端子（ＴｖＡ）と前記スレーブリニア電源装置の前記電圧情報入力端子（ＴｖＢ）が接続可能である構成としている（第８の構成）。 Further, a power supply system (5) according to an aspect of the present disclosure includes a master linear power supply device (1A) that is a linear power supply device having the third configuration, in which the first switch (NS1A) is set to an on state;
one or more slave linear power supply devices (1B), which are linear power supply devices of the third configuration, in which the first switch is set to an off state;
The output terminal (ToA) of the master linear power supply device and the output terminal (ToB) of the slave linear power supply device can be commonly connected to a load,
The voltage information output terminal (TvA) of the master linear power supply device and the voltage information input terminal (TvB) of the slave linear power supply device are connectable (eighth configuration).
　また、上記第８の構成において、前記スレーブリニア電源装置は、２つ以上である構成としてもよい（第９の構成）。 Furthermore, in the eighth configuration, the number of slave linear power supply devices may be two or more (ninth configuration).
　また、本開示の一態様に係る電源システム（５）は、複数の上記第７の構成に記載のリニア電源装置を備え、
　前記複数のリニア電源装置（１Ａ，１Ｂ）におけるそれぞれの前記出力端子（ＴｏＡ，ＴｏＢ）は、負荷に共通接続可能であり、
　前記複数のリニア電源装置において（１Ａ，１Ｂ）、異なる前記リニア電源装置の間で前記電圧情報出力端子（ＴｓｒＡ，ＴｓｒＢ）と前記電圧情報入力端子（ＴｓｋＢ，ＴｓｋＡ）とが順次接続される構成としている（第１０の構成）。 Further, a power supply system (5) according to one aspect of the present disclosure includes a plurality of linear power supply devices according to the seventh configuration,
The respective output terminals (ToA, ToB) in the plurality of linear power supply devices (1A, 1B) can be commonly connected to a load,
In the plurality of linear power supply devices (1A, 1B), the voltage information output terminals (TsrA, TsrB) and the voltage information input terminals (TskB, TskA) are sequentially connected between different linear power supply devices. (10th configuration).
　本開示は、各種機器に搭載される電源システムに利用することが可能である。 The present disclosure can be used in power supply systems installed in various devices.
　　　１Ａ，１Ｂ，１Ｃ　リニア電源装置
　　　５　　　電源システム
　　　１０Ａ，１０Ｂ　リニア電源装置
　　　５０　　　電源システム
　　　ＡＰ１０Ａ　　エラーアンプ
　　　ＡＰ１Ａ　　　エラーアンプ
　　　ＢＰＡ　　　バイパススイッチ
　　　Ｃ１　　　コンデンサ
　　　Ｃ２　　　コンデンサ
　　　ＣＰＡ　　　コンパレータ
　　　Ｍ１０Ａ　　　出力トランジスタ
　　　Ｍ１０Ｂ　　　出力トランジスタ
　　　Ｍ１Ａ　　　出力トランジスタ
　　　Ｍ２Ａ　　　ミラートランジスタ
　　　Ｎ１，Ｎ２　　ＮＭＯＳトランジスタ
　　　ＮＭＡ　　　ＮＭＯＳトランジスタ
　　　ＮＳ１Ａ，ＮＳ２Ａ　ＮＭＯＳスイッチ
　　　Ｏｒ　　　ＯＲ回路
　　　Ｐ１，Ｐ２　　ＰＭＯＳトランジスタ
　　　ＰＭＡ　　　ＰＭＯＳスイッチ
　　　Ｒ１１Ａ，１２Ａ　抵抗
　　　Ｒ１Ａ，Ｒ２Ａ，Ｒ３Ａ，Ｒ４Ａ　帰還抵抗
　　　ＲＡ　　　抵抗
　　　ＲＬ　　　負荷
　　　Ｒａ，Ｒｂ　　抵抗
　　　ＲｓＡ　　　センス抵抗
　　　ＴｏＡ　　　出力端子
　　　ＴｓｒＡ　　　電圧ソース端子
　　　ＴｓｋＡ　　　電圧シンク端子
　　　ＴｖＡ　　　電圧情報送受信端子 1A, 1B, 1C Linear power supply 5 Power supply system 10A, 10B Linear power supply 50 Power supply system AP10A Error amplifier AP1A Error amplifier BPA Bypass switch C1 Capacitor C2 Capacitor CPA Comparator M10A Output transistor M10B Output transistor M1A Output transistor M2A Mirror transistor N1, N2 NMOS transistor NMA NMOS transistor NS1A, NS2A NMOS switch Or OR circuit P1, P2 PMOS transistor PMA PMOS switch R11A, 12A Resistor R1A, R2A, R3A, R4A Feedback resistor RA Resistor RL Load Ra, Rb Resistor RsA Sense resistor ToA Output terminal TsrA voltage Source terminal TskA Voltage sink terminal TvA Voltage information transmission/reception terminal

Claims (10)

  1. 　入力電圧の印加端に接続可能に構成される第１主電極と、第２主電極と、を有する出力トランジスタと、
    　前記第２主電極に接続される出力端子と、
    　前記出力端子に発生する出力電圧に基づく帰還電圧と、基準電圧とが入力され、前記出力トランジスタの制御端を駆動可能に構成されるエラーアンプと、
    　前記出力トランジスタに流れる電流のミラー電流を生成可能に構成されるミラートランジスタと、
    　前記ミラー電流を第１電圧情報に変換する電流／電圧変換部と、
    　前記第１電圧情報を外部に対して出力可能に構成される電圧情報出力端子と、
    　第２電圧情報を外部から入力可能に構成される電圧情報入力端子と、
    　前記第２電圧情報と前記第１電圧情報とを比較するように構成される比較部と、
    　前記比較部の比較結果に基づき駆動され、前記第２電圧情報と前記第１電圧情報の差が小さくなるように制御する制御トランジスタと、
    を備える、リニア電源装置。     an output transistor having a first main electrode configured to be connectable to an input voltage application end and a second main electrode;
    an output terminal connected to the second main electrode;
    an error amplifier configured to receive a feedback voltage based on the output voltage generated at the output terminal and a reference voltage, and to be able to drive a control end of the output transistor;
    a mirror transistor configured to be able to generate a mirror current of the current flowing through the output transistor;
    a current/voltage converter that converts the mirror current into first voltage information;
    a voltage information output terminal configured to be able to output the first voltage information to the outside;
    a voltage information input terminal configured to allow input of second voltage information from the outside;
    a comparison unit configured to compare the second voltage information and the first voltage information;
    a control transistor that is driven based on the comparison result of the comparison section and is controlled so that the difference between the second voltage information and the first voltage information is small;
    A linear power supply equipped with.
  2. 　前記制御トランジスタの第１主電極は、前記出力トランジスタの第２主電極に接続される帰還抵抗部に接続される、請求項１に記載のリニア電源装置。 The linear power supply device according to claim 1, wherein the first main electrode of the control transistor is connected to a feedback resistor connected to the second main electrode of the output transistor.
  3. 　前記電圧情報出力端子と前記電圧情報入力端子は同一の端子であり、
    　前記第１電圧情報を前記電圧情報出力端子から出力するか否かを切り替える第１スイッチをさらに備え、
    　前記第１電圧情報が外部へ出力される場合、前記第２電圧情報と前記第１電圧情報の差が小さくなるような制御は機能せず、
    　前記第１電圧情報が外部へ出力されない場合、外部から入力された前記第２電圧情報と前記第１電圧情報の差が小さくなるような制御が機能する、請求項１または請求項２に記載のリニア電源装置。     The voltage information output terminal and the voltage information input terminal are the same terminal,
    further comprising a first switch that switches whether or not to output the first voltage information from the voltage information output terminal,
    When the first voltage information is output to the outside, control that reduces the difference between the second voltage information and the first voltage information does not function,
    3 . The control according to claim 1 , wherein when the first voltage information is not outputted to the outside, a control is performed such that a difference between the second voltage information inputted from the outside and the first voltage information is reduced. Linear power supply.
  4. 　前記出力トランジスタの第２主電極に接続される帰還抵抗部の一部の帰還抵抗をバイパスするか否かを切り替える第２スイッチをさらに備え、
    　前記第２スイッチは、前記第１スイッチと連動する、請求項３に記載のリニア電源装置。     further comprising a second switch for switching whether or not to bypass a part of the feedback resistance of the feedback resistance section connected to the second main electrode of the output transistor,
    The linear power supply device according to claim 3, wherein the second switch operates in conjunction with the first switch.
  5. 　前記比較部に電流を供給するか否かを切り替える第３スイッチをさらに備え、
    　前記第３スイッチは、前記第１スイッチと連動する、請求項３または請求項４に記載のリニア電源装置。     further comprising a third switch that switches whether or not to supply current to the comparison section,
    The linear power supply device according to claim 3 or 4, wherein the third switch is interlocked with the first switch.
  6. 　前記制御トランジスタの制御端と接地端との間に接続される第４スイッチをさらに備え、
    　前記第４スイッチは、前記第１スイッチと連動する、請求項３から請求項５のいずれか１項に記載のリニア電源装置。     further comprising a fourth switch connected between the control end and the ground end of the control transistor,
    The linear power supply device according to any one of claims 3 to 5, wherein the fourth switch is interlocked with the first switch.
  7. 　前記電圧情報出力端子と前記電圧情報入力端子は別個の端子である、請求項１または請求項２に記載のリニア電源装置。 The linear power supply device according to claim 1 or 2, wherein the voltage information output terminal and the voltage information input terminal are separate terminals.
  8. 　前記第１スイッチがオン状態に設定される請求項３に記載のリニア電源装置であるマスターリニア電源装置と、
    　前記第１スイッチがオフ状態に設定される請求項３に記載のリニア電源装置である１つ以上のスレーブリニア電源装置と、
    　を備え、
    　前記マスターリニア電源装置の前記出力端子と前記スレーブリニア電源装置の前記出力端子は、負荷に共通接続可能であり、
    　前記マスターリニア電源装置の前記電圧情報出力端子と前記スレーブリニア電源装置の前記電圧情報入力端子が接続可能である、電源システム。     A master linear power supply device that is a linear power supply device according to claim 3, wherein the first switch is set to an on state;
    one or more slave linear power supplies that are the linear power supplies according to claim 3, wherein the first switch is set to an off state;
    Equipped with
    The output terminal of the master linear power supply device and the output terminal of the slave linear power supply device can be commonly connected to a load,
    A power supply system, wherein the voltage information output terminal of the master linear power supply device and the voltage information input terminal of the slave linear power supply device are connectable.
  9. 　前記スレーブリニア電源装置は、２つ以上である、請求項８に記載の電源システム。 The power supply system according to claim 8, wherein the number of slave linear power supply devices is two or more.
  10. 　複数の請求項７に記載のリニア電源装置を備え、
    　前記複数のリニア電源装置におけるそれぞれの前記出力端子は、負荷に共通接続可能であり、
    　前記複数のリニア電源装置において、異なる前記リニア電源装置の間で前記電圧情報出力端子と前記電圧情報入力端子とが順次接続される、電源システム。     comprising a plurality of linear power supply devices according to claim 7,
    The output terminals of each of the plurality of linear power supply devices can be commonly connected to a load,
    In the plurality of linear power supply devices, the voltage information output terminal and the voltage information input terminal are sequentially connected between different linear power supply devices.
PCT/JP2023/025292 2022-07-21 2023-07-07 Linear power supply device and power supply system WO2024018927A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171811A (en) * 1988-10-31 1990-07-03 Nixdorf Comput Ag Power distribution type power source system
JPH1020947A (en) * 1996-06-28 1998-01-23 Sony Corp Redundant stabilized power source device
JP2021061655A (en) * 2019-10-03 2021-04-15 株式会社豊田自動織機 Power supply device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171811A (en) * 1988-10-31 1990-07-03 Nixdorf Comput Ag Power distribution type power source system
JPH1020947A (en) * 1996-06-28 1998-01-23 Sony Corp Redundant stabilized power source device
JP2021061655A (en) * 2019-10-03 2021-04-15 株式会社豊田自動織機 Power supply device

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