CN104049668B - Low pressure difference linear voltage regulator - Google Patents

Abstract

Low pressure difference linear voltage regulator disclosed by the invention, belongs to the technical field of integrated circuit.Low pressure difference linear voltage regulator, comprise: output mos pipe, be serially connected in the voltage sampling circuit on output mos tube current outflow end, comparison sampled signal, reference voltage value obtain the voltage comparator circuit of error signal, by the Buffer driving circuit of error signal drives output mos pipe work, voltage comparator circuit comprises: the first depletion type NMOS tube, the first enhancement mode NMOS tube, voltage compare function is realized with reference voltage generating circuit, reduce chip area, there is the advantage of low-power consumption, low noise, high PSRR.

Description

Low pressure difference linear voltage regulator

Technical field

The invention discloses low pressure difference linear voltage regulator, the LDO (LowDropoutRegulator, low pressure difference linear voltage regulator) of especially a kind of low-power consumption, low noise, belongs to the technical field of integrated circuit.

Background technology

No matter mancarried electronic aid is powered by AC adapter, or battery-powered, and in the course of work, supply voltage all will in very large range change, and in order to ensure that supply voltage is stablized constant, nearly all electronic equipment all adopts voltage stabilizer to power.Miniature precision electronic equipment also requires power supply very clean (ripple-free, noiseless), normally works in order to avoid affect electronic equipment.Therefore LDO circuit generally will meet the requirements such as wide operating voltage range, voltage stabilizing output, low noise, high PSRR, high transient response speed and lower quiescent dissipation.At present, LDO circuit many employings band gap reference adds the structure of amplifier, is realized the accurate control of voltage by amplifier negative feedback.

As shown in Figure 1, common LDO circuit comprises band gap reference BGR, operational amplifier A MP, Correctional tube PMOSFETMP0, resistance R1 and R2.Shown in above-mentioned, circuit structure produces the reference voltage of anti-PVT by band gap reference BGR, and operational amplifier A MP also adjusts actual output voltage according to the ratio-dependent of resistance R1 and R2, actual output voltage computing formula: V _oUT=V _rEF(1+R1/R2).

The voltage stabilizing that foregoing circuit structure can realize degree of precision exports, but owing to containing band gap reference BGR and operational amplifier A MP in whole circuit framework, the overall power of circuit is higher, if pursue higher PSRR, faster response speed and lower output noise, then the power consumption that circuit needs can be higher.Portable type electronic product of today requires higher to the standby time of battery, the processor of portable product is generally all provided with several different duty, reduce the consumption to battery capacity by a series of different energy saver mode (free time, sleep, deep sleep etc.), require to provide the quiescent dissipation of the LDO of stabilized voltage supply self low as far as possible to processor simultaneously.The quiescent dissipation of LDO circuit is proportional with performance, and should run a good foot by horse, and yet won't feed it, this is the dilemma that fish and bear's paw can not get both.

Based on above reason, find that a kind of structure is simple, excellent performance, the circuit that the quiescent current simultaneously consumed is extremely low is again necessary.

Summary of the invention

Technical matters to be solved by this invention is the deficiency for above-mentioned background technology, provides low pressure difference linear voltage regulator.

The present invention adopts following technical scheme for achieving the above object:

Low pressure difference linear voltage regulator, comprise: output mos pipe, be serially connected in the voltage sampling circuit on output mos tube current outflow end, compare sampled signal, voltage comparator circuit that reference voltage value obtains error signal, by the Buffer driving circuit of error signal drives output mos pipe work

Described voltage comparator circuit comprises: the first depletion type NMOS tube DN1, the first enhancement mode NMOS tube MN1, described first depletion type NMOS tube DN1 drain electrode connects input power, meet the first enhancement mode NMOS tube MN1 after the grid of the first depletion type NMOS tube DN1, source shorted to drain, first enhancement mode NMOS tube MN1 source ground, first enhancement mode NMOS tube MN1 grid connects sampled signal, the first enhancement mode NMOS tube MN1 drain electrode output error signal.

As the further prioritization scheme of described low pressure difference linear voltage regulator, Buffer driving circuit comprises: the first enhancement mode PMOS MP1, the first resistance R3, the second enhancement mode NMOS tube MN2, described first enhancement mode PMOS MP1 source electrode connects input power, one end of the first resistance R3 is connect after the grid of the first enhancement mode PMOS MP1, the short circuit that drains, another termination second enhancement mode of first resistance R3 NMOS tube MN2 drains, second enhancement mode NMOS tube MN2 grid meets the first enhancement mode NMOS tube MN1 and drains, the second enhancement mode NMOS tube MN2 source ground.

Further, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS MP2, 3rd enhancement mode NMOS tube MN3, second depletion type NMOS tube DN2, described second enhancement mode PMOS MP2 source electrode meets the first enhancement mode PMOS MP1 and drains, second enhancement mode PMOS MP2 grid meets the second enhancement mode NMOS tube MN2 and drains, second enhancement mode PMOS MP2 drain electrode meets the second depletion type NMOS tube DN2 and drains, second depletion type NMOS tube DN2 grid, ground connection after source shorted, 3rd enhancement mode NMOS tube MN3 drain electrode meets the first enhancement mode NMOS tube MN1 and drains, 3rd enhancement mode NMOS tube MN3 grid meets the second depletion type NMOS tube DN2 and drains, 3rd enhancement mode NMOS tube MN3 source ground.

Further, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS MP2, 3rd enhancement mode NMOS tube MN3, current-limiting resistance, described second enhancement mode PMOS MP2 source electrode meets the first enhancement mode PMOS MP1 and drains, second enhancement mode PMOS MP2 grid meets the second enhancement mode NMOS tube MN2 and drains, second enhancement mode PMOS MP2 drains, 3rd enhancement mode NMOS tube MN3 grid all connects current-limiting resistance one end, 3rd enhancement mode NMOS tube MN3 source electrode, the equal ground connection of the current-limiting resistance other end, 3rd enhancement mode NMOS tube MN3 drain electrode meets the first enhancement mode NMOS tube MN1 and drains.

Further, described low pressure difference linear voltage regulator also comprises the compensation branch road be connected between the first enhancement mode NMOS tube MN1 drain electrode, source electrode.

As the further prioritization scheme of described compensation branch road, compensate branch road and comprise compensating resistance R0, building-out capacitor C0, described compensating resistance R0 mono-termination first enhancement mode NMOS tube MN1 drains, another termination building-out capacitor of compensating resistance R0 C0 positive plate, building-out capacitor C0 negative plate connects the first enhancement mode NMOS tube MN1 source electrode.

The present invention adopts technique scheme, has following beneficial effect: realize voltage compare function with reference voltage generating circuit, reduce chip area, has the advantage of low-power consumption, low noise, high PSRR.

Accompanying drawing explanation

Fig. 1 is the LDO circuit theory diagrams of prior art.

Fig. 2 is circuit theory diagrams of the present invention.

Fig. 3 is reference voltage generating circuit schematic diagram of the present invention.

Number in the figure illustrates: MP0, MP1, MP2 are enhancement mode PMOS, and DN1, DN2 are depletion type NMOS tube, and MN1, MN2, MN3 are enhancement mode NMOS tube, and R1, R2, R3 are resistance, and R0 is compensating resistance, and C0 is building-out capacitor.

Embodiment

Be described in detail below in conjunction with the technical scheme of accompanying drawing to invention.

Specific embodiment one

Low pressure difference linear voltage regulator as shown in Figure 2, comprise: enhancement mode PMOS MP0 (output mos pipe), be serially connected in the voltage sampling circuit on output mos tube current outflow end (being enhancement mode PMOS MP0 to drain), comparison sampled signal, reference voltage value obtain the voltage comparator circuit of error signal, by the Buffer driving circuit of error signal drives output mos pipe work.Voltage sampling circuit is made up of resistance R1, the R2 be connected in series, and the tie point A point of resistance R1, R2 exports sampled signal VA.

Voltage comparator circuit comprises: depletion type NMOS tube DN1, enhancement mode NMOS tube MN1, depletion type NMOS tube DN1 drain electrode meets input power VIN, meet enhancement mode NMOS tube MN1 after the grid of depletion type NMOS tube DN1, source shorted to drain, enhancement mode NMOS tube MN1 source ground, enhancement mode NMOS tube MN1 grid connects sampled signal, and enhancement mode NMOS tube MN1 drains (B point) output error signal.

Depletion type NMOS tube DN1 forms reference voltage generating circuit with enhancement mode NMOS tube MN1, reference voltage generating circuit schematic diagram is as shown in Figure 3: drain electrode, the grid of the gate-source short circuit heel enhancement mode NMOS tube MN1 of depletion type NMOS tube DN1 are received together, then can obtain reference voltage V ref:

$V_{\mathrm{ref}}=V_{\mathrm{TN}}-\sqrt{\frac{k_{\mathrm{DN}1}}{k_{\mathrm{MN}1}}}{V}_{\mathrm{TD}}---\left(1\right),$

In formula (1), V _tNwith V _tDrepresent the threshold voltage of enhancement mode NMOS tube MN1 and depletion type NMOS tube DN1 respectively, k _dN1=μ _nc _oX(W/L) _dN1, k _mN1=μ _nc _oX(W/L) _mN1, the threshold value of depletion type NMOS is negative, and depletion type NMOS follows the threshold value of enhancement mode NMOS all in negative temperature coefficient, by the breadth length ratio (W/L) of choose reasonable enhancement mode NMOS tube MN1 _mN1and the breadth length ratio DN1 of depletion type NMOS tube (W/L) _dN1, the reference voltage V ref of zero-temperature coefficient can be obtained.In this example, reference voltage generating circuit has voltage compare effect concurrently, reduces chip area.

Specific embodiment two

On the basis of embodiment one, further optimal design is done to Buffer driving circuit.Buffer driving circuit comprises: enhancement mode PMOS MP1, resistance R3, enhancement mode NMOS tube MN2, enhancement mode PMOS MP1 source electrode connects input power, one end (D point) of connecting resistance R3 after the grid of enhancement mode PMOS MP1, the short circuit that drains, another termination enhancement mode of resistance R3 NMOS tube MN2 drains (C point), enhancement mode NMOS tube MN2 grid meets enhancement mode NMOS tube MN1 and drains, enhancement mode NMOS tube MN2 source ground.

In circuit shown in Fig. 2, with drain electrode separately, the grid of enhancement mode NMOS tube MN1 is connected to resistance R1 with between resistance R2, the grid voltage V of enhancement mode NMOS tube MN1 as the input end of voltage comparator circuit for the grid of enhancement mode NMOS tube MN1 _a=R2*VOUT/ (R1+R2); If V _alower than reference voltage V ref, then the output voltage V of voltage comparator circuit _b(being error signal) raises, V _bcontrol the grid of enhancement mode NMOS tube MN2, V _braise then enhancement mode PMOS MP1 and follow the grid voltage V of enhancement mode PMOS MP0 _dreduce, V _dreducing to make VOUT voltage raise then VOUT sampled voltage V _aand then raise; If otherwise VOUT sampled voltage V _ahigher than reference voltage V ref, then V _breduce, V _draise, thus reduction VOUT voltage makes V _avoltage stabilization is at reference voltage value Vref.

In Buffer driving circuit, enhancement mode PMOS MP1 can copy the electric current of enhancement mode PMOS MP0, and the size of copy current is by (W/L) _mP1/ (W/L) _mP0ratio determine, if (W/L) _mP1/ (W/L) _mP0=1/1000, the electric current flowing through voltage sampling circuit is 1 μ A, and when VOUT is unloaded, the electric current of Buffer driving circuit is only 1/1000 μ A (1nA); Along with the increase of load current, Buffer drive current also and then increases, such Buffer driving circuit self-adaptation can choose suitable drive current to obtain optimum transient response and PSRR performance, and alap quiescent dissipation, while taking into account transient response and PSRR performance, greatly reduce the standby current of LDO.

Specific embodiment three

In order to the output current limiting enhancement mode PMOS MP0 is excessive, the feature that the present invention utilizes enhancement mode PMOS MP1 in Buffer driving circuit can copy enhancement mode PMOS MP0 electric current devises current-limiting protection circuit.Current-limiting protection circuit comprises: enhancement mode PMOS MP2, enhancement mode NMOS tube MN3, depletion type NMOS tube DN2, enhancement mode PMOS MP2 source electrode meets enhancement mode PMOS MP1 and drains, enhancement mode PMOS MP2 grid meets enhancement mode NMOS tube MN2 and drains, enhancement mode PMOS MP2 drain electrode meets depletion type NMOS tube DN2 and drains (E point), depletion type NMOS tube DN2 grid, ground connection after source shorted, enhancement mode NMOS tube MN3 drain electrode meets enhancement mode NMOS tube MN1 and drains, enhancement mode NMOS tube MN3 grid meets depletion type NMOS tube DN2 and drains, enhancement mode NMOS tube MN3 source ground.By resistance R3, the electric current of copy is converted to the switch of Control of Voltage enhancement mode PMOS MP2, the cut-off current I of enhancement mode PMOS MP0 _mP0can be drawn by formula (2) estimation:

$I_{\mathrm{MP}0}=\frac{{\left(\frac{W}{L}\right)}_{\mathrm{MP}0}}{{\left(\frac{W}{L}\right)}_{\mathrm{MP}1}}*\frac{V_{\mathrm{TP}}}{R3}---\left(2\right),$

In formula (2), V _tPrepresent the threshold value of enhancement mode PMOS MP2, (W/L) _mP0,(W/L) _mP1be respectively the breadth length ratio of enhancement mode PMOS MP0, enhancement mode PMOS MP1.

In current-limiting protection circuit, depletion type NMOS tube DN2 as the current source loads of enhancement mode PMOS MP2, when the current value of enhancement mode PMOS MP0 reaches the cut-off current of setting, I _mP1* R3=V _tP, enhancement mode PMOS MP2 opens, E point voltage V _eraise, open enhancement mode NMOS tube MN3, vise the output voltage V of voltage comparator circuit _b, the gate voltage of enhancement mode NMOS tube MN2 cannot raise further, and the gate voltage of enhancement mode PMOS MP0 cannot be reduced further, and the output current of enhancement mode PMOS MP0 cannot increase further after reaching the cut-off current of setting, achieves current-limiting function.

In addition, in this example, depletion type NMOS tube DN2 can also be substituted with current-limiting resistance, current-limiting resistance one termination E point, other end ground connection.

Specific embodiment four

On the basis of embodiment noted earlier, devise the compensation branch road be connected between enhancement mode NMOS tube MN1 drain electrode, source electrode, to provide enough phase margins, ensure the stability of whole loop.As shown in Figure 2, the compensating resistance R0 that branch road is serial connection and building-out capacitor C0 is compensated.

In the present invention, reference voltage generating circuit has only used DN1 with MN1 two transistors with voltage comparator circuit, chip area is very little, the electric current consumed also very little (lower than 1 μ A), there is not the intrinsic Resistance Thermal Noise of band-gap reference in the reference voltage that this circuit produces, by preferred DN1 with MN1 size, the 1/f noise of metal-oxide-semiconductor can be reduced further, so the noise of this reference voltage is far below traditional bandgap benchmark.The overall quiescent dissipation of LDO of the present invention is less than 2 μ A, and the performances such as its output noise, transient response and PSRR can match in excellence or beauty with the LDO of 100 μ A power consumptions of prior art.

Above-described embodiment is only several embodiments that the present invention enumerates, but is not limiting the scope of the invention, and the equivalent replacement form of the every embodiment and above-described embodiment that meet invention aim of the present invention all falls into protection scope of the present invention.

In sum, the present invention has following beneficial effect:

(1) improve traditional reference voltage generating circuit, the grid of output reference voltage metal-oxide-semiconductor no longer with drain electrode short circuit, have the function producing reference voltage, comparative voltage concurrently, reduce chip area, power consumption is little, noise is low;

(2) the enhancement mode type PMOS in Buffer driving circuit and output mos pipe MP0 form current mirror, have the function of copy power tube MP0 electric current, self-adaptation can choose suitable drive current to obtain optimum transient response and PSRR performance;

(3) electric current that copies to using the enhancement mode PMOS in Buffer driving circuit of current-limiting circuit is as drive singal, reaches clamp voltage comparator circuit output voltage and then realize current-limiting protection in limited time at the output current of output power pipe.

Claims (5)

1. low pressure difference linear voltage regulator, comprise: output mos pipe, be serially connected in the voltage sampling circuit on output mos tube current outflow end, compare sampled signal, voltage comparator circuit that reference voltage value obtains error signal, by the Buffer driving circuit of error signal drives output mos pipe work

It is characterized in that, described voltage comparator circuit comprises: the first depletion type NMOS tube (DN1), the first enhancement mode NMOS tube (MN1), described first depletion type NMOS tube (DN1) drain electrode connects input power, the first enhancement mode NMOS tube (MN1) drain electrode is connect after the grid of the first depletion type NMOS tube (DN1), source shorted, first enhancement mode NMOS tube (MN1) source ground, first enhancement mode NMOS tube (MN1) grid connects sampled signal, and the first enhancement mode NMOS tube (MN1) drains output error signal;

Described Buffer driving circuit comprises: the first enhancement mode PMOS (MP1), first resistance (R3), second enhancement mode NMOS tube (MN2), described first enhancement mode PMOS (MP1) source electrode connects input power, the grid of the first enhancement mode PMOS (MP1), one end of the first resistance (R3) is connect after drain electrode short circuit, another termination second enhancement mode NMOS tube (MN2) of first resistance (R3) drains, second enhancement mode NMOS tube (MN2) grid connects the first enhancement mode NMOS tube (MN1) drain electrode, second enhancement mode NMOS tube (MN2) source ground.

2. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS (MP2), 3rd enhancement mode NMOS tube (MN3), second depletion type NMOS tube (DN2), described second enhancement mode PMOS (MP2) source electrode connects the first enhancement mode PMOS (MP1) drain electrode, second enhancement mode PMOS (MP2) grid connects the second enhancement mode NMOS tube (MN2) drain electrode, second enhancement mode PMOS (MP2) drain electrode connects the second depletion type NMOS tube (DN2) drain electrode, second depletion type NMOS tube (DN2) grid, ground connection after source shorted, 3rd enhancement mode NMOS tube (MN3) drain electrode connects the first enhancement mode NMOS tube (MN1) drain electrode, 3rd enhancement mode NMOS tube (MN3) grid connects the second depletion type NMOS tube (DN2) drain electrode, 3rd enhancement mode NMOS tube (MN3) source ground.

3. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS (MP2), 3rd enhancement mode NMOS tube (MN3), current-limiting resistance, described second enhancement mode PMOS (MP2) source electrode connects the first enhancement mode PMOS (MP1) drain electrode, second enhancement mode PMOS (MP2) grid connects the second enhancement mode NMOS tube (MN2) drain electrode, second enhancement mode PMOS (MP2) drain electrode, 3rd enhancement mode NMOS tube (MN3) grid all connects current-limiting resistance one end, 3rd enhancement mode NMOS tube (MN3) source electrode, the equal ground connection of the current-limiting resistance other end, 3rd enhancement mode NMOS tube (MN3) drain electrode connects the first enhancement mode NMOS tube (MN1) drain electrode.

4. the low pressure difference linear voltage regulator according to Claims 2 or 3, is characterized in that, described low pressure difference linear voltage regulator also comprises the compensation branch road be connected between the first enhancement mode NMOS tube (MN1) drain electrode, source electrode.

5. low pressure difference linear voltage regulator according to claim 4, it is characterized in that, described compensation branch road comprises compensating resistance (R0), building-out capacitor (C0), described compensating resistance (R0) one termination first enhancement mode NMOS tube (MN1) drains, another termination building-out capacitor (C0) positive plate of compensating resistance (R0), building-out capacitor (C0) negative plate connects the first enhancement mode NMOS tube (MN1) source electrode.