CN104049668A - Low-dropout linear voltage stabilizer - Google Patents
Low-dropout linear voltage stabilizer Download PDFInfo
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- CN104049668A CN104049668A CN201410330954.9A CN201410330954A CN104049668A CN 104049668 A CN104049668 A CN 104049668A CN 201410330954 A CN201410330954 A CN 201410330954A CN 104049668 A CN104049668 A CN 104049668A
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- enhancement mode
- nmos pipe
- pipe
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- mode nmos
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Abstract
The invention discloses a low-dropout linear voltage stabilizer, and belongs to the technical field of integrated circuits. The low-dropout linear voltage stabilizer comprises an output MOS tube, a voltage sampling circuit connected to the current outflow end of the output MOS tube in series, a voltage comparison circuit comparing a sampled signal with a standard voltage value to obtain an error signal, and a Buffer drive circuit driving the output MOS tube to work through the error signal. The voltage comparison circuit comprises a first depletion type NMOS tube and a first enhancement type NMOS tube. The voltage comparison function is achieved through a standard voltage generation circuit, and the domain area is reduced. The low drop-out linear voltage stabilizer has the advantages of being low in power consumption, low in noise and high in PSRR.
Description
Technical field
The invention discloses low pressure difference linear voltage regulator, especially a kind of low-power consumption, low noise LDO (Low Dropout Regulator, low pressure difference linear voltage regulator), belong to the technical field of integrated circuit.
Background technology
Mancarried electronic aid is no matter be to be powered by AC adapter, or battery-powered, and in the course of work, supply voltage all will in very large range change, in order to ensure that supply voltage stablizes constant, nearly all electronic equipment and all adopt voltage stabilizer power supply.Miniature precision electronic equipment also requires very clean (ripple-free, noiseless) of power supply, normally works in order to avoid affect electronic equipment.Therefore LDO circuit generally will meet the requirements such as wide operating voltage range, voltage stabilizing output, low noise, high PSRR, high transient response speed and lower quiescent dissipation.At present, LDO circuit adopts band gap reference to add the structure of amplifier more, realizes the accurate control of voltage by amplifier negative feedback.
As shown in Figure 1, common LDO circuit comprises band gap reference BGR, operational amplifier A MP, adjusts pipe PMOS FET MP0, resistance R 1 and R2.Circuit structure shown in above-mentioned produces the reference voltage of anti-PVT by band gap reference BGR, operational amplifier A MP is according to the ratio-dependent of resistance R 1 and R2 and adjust actual output voltage, actual output voltage computing formula: V
oUT=V
rEF(1+R1/R2).
Foregoing circuit structure can realize the voltage stabilizing output of degree of precision, but owing to having comprised band gap reference BGR and operational amplifier A MP in whole circuit framework, the overall power of circuit is higher, if pursue higher PSRR, faster response speed and lower output noise, the power consumption that circuit needs can be higher.Portable type electronic product of today is had relatively high expectations to the standby time of battery, the processor of portable product is generally all provided with several different duties, reduce the consumption to battery capacity by a series of different energy saver modes (free time, sleep, deep sleep etc.), require provides the quiescent dissipation of LDO self of stabilized voltage supply low as far as possible to processor simultaneously.The quiescent dissipation of LDO circuit is proportional with performance, should run a good foot by horse, and yet won't feed it, and this is the dilemma that fish and bear's paw can not get both.
Based on above reason, find a kind of simple in structure, excellent performance, the quiescent current simultaneously consuming again extremely low circuit is necessary.
Summary of the invention
Technical matters to be solved by this invention is for the deficiency of above-mentioned background technology, and low pressure difference linear voltage regulator is provided.
The present invention adopts following technical scheme for achieving the above object:
Low pressure difference linear voltage regulator, comprise: output mos pipe, be serially connected in the voltage sampling circuit on output mos tube current outflow end, relatively sampled signal, reference voltage value obtain the voltage comparator circuit of error signal, by the Buffer driving circuit of error signal drives output mos pipe work
Described voltage comparator circuit comprises: the first depletion type NMOS pipe DN1, the first enhancement mode NMOS pipe MN1, described the first depletion type NMOS pipe DN1 drain electrode connects input power, after the grid of the first depletion type NMOS pipe DN1, source shorted, connect the first enhancement mode NMOS pipe MN1 drain electrode, the first enhancement mode NMOS pipe MN1 source ground, the first enhancement mode NMOS pipe MN1 grid connects sampled signal, the first enhancement mode NMOS pipe MN1 drain electrode output error signal.
As the further prioritization scheme of described low pressure difference linear voltage regulator, Buffer driving circuit comprises: the first enhancement mode PMOS pipe MP1, the first resistance R 3, the second enhancement mode NMOS pipe MN2, described the first enhancement mode PMOS pipe MP1 source electrode connects input power, after the grid of the first enhancement mode PMOS pipe MP1, the short circuit that drains, connect one end of the first resistance R 3, first resistance R 3 another termination second enhancement mode NMOS pipe MN2 drain electrodes, the second enhancement mode NMOS pipe MN2 grid connects the first enhancement mode NMOS pipe MN1 drain electrode, the second enhancement mode NMOS pipe MN2 source ground.
Further, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS pipe MP2, the 3rd enhancement mode NMOS pipe MN3, the second depletion type NMOS pipe DN2, described the second enhancement mode PMOS pipe MP2 source electrode connects the first enhancement mode PMOS pipe MP1 drain electrode, the second enhancement mode PMOS pipe MP2 grid connects the second enhancement mode NMOS pipe MN2 drain electrode, the second enhancement mode PMOS pipe MP2 drain electrode connects the second depletion type NMOS pipe DN2 drain electrode, the second depletion type NMOS pipe DN2 grid, ground connection after source shorted, the 3rd enhancement mode NMOS pipe MN3 drain electrode connects the first enhancement mode NMOS pipe MN1 drain electrode, the 3rd enhancement mode NMOS pipe MN3 grid connects the second depletion type NMOS pipe DN2 drain electrode, the 3rd enhancement mode NMOS pipe MN3 source ground.
Further, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS pipe MP2, the 3rd enhancement mode NMOS pipe MN3, current-limiting resistance, described the second enhancement mode PMOS pipe MP2 source electrode connects the first enhancement mode PMOS pipe MP1 drain electrode, the second enhancement mode PMOS pipe MP2 grid connects the second enhancement mode NMOS pipe MN2 drain electrode, the second enhancement mode PMOS pipe MP2 drain electrode, the 3rd enhancement mode NMOS pipe MN3 grid all connects current-limiting resistance one end, the 3rd enhancement mode NMOS pipe MN3 source electrode, the equal ground connection of the current-limiting resistance other end, the 3rd enhancement mode NMOS pipe MN3 drain electrode connects the first enhancement mode NMOS pipe MN1 drain electrode.
Further, described low pressure difference linear voltage regulator also comprises the compensation branch road being connected between the first enhancement mode NMOS pipe MN1 drain electrode, source electrode.
As the further prioritization scheme of described compensation branch road, compensation branch road comprises compensating resistance R0, building-out capacitor C0, described compensating resistance R0 mono-termination the first enhancement mode NMOS pipe MN1 drain electrode, another termination building-out capacitor of compensating resistance R0 C0 positive plate, building-out capacitor C0 negative plate connects the first enhancement mode NMOS pipe MN1 source electrode.
The present invention adopts technique scheme, has following beneficial effect: realize voltage comparing function with reference voltage generating circuit, reduced chip area, have advantages of low-power consumption, low noise, high PSRR.
Brief description of the drawings
Fig. 1 is the LDO circuit theory diagrams of prior art.
Fig. 2 is circuit theory diagrams of the present invention.
Fig. 3 is reference voltage generating circuit schematic diagram of the present invention.
Number in the figure explanation: MP0, MP1, MP2 are enhancement mode PMOS pipe, DN1, DN2 are depletion type NMOS pipe, and MN1, MN2, MN3 are enhancement mode NMOS pipe, and R1, R2, R3 are resistance, and R0 is compensating resistance, C0 is building-out capacitor.
Embodiment
Below in conjunction with accompanying drawing, the technical scheme of invention is elaborated.
Specific embodiment one
Low pressure difference linear voltage regulator as shown in Figure 2, comprise: enhancement mode PMOS pipe MP0 (output mos pipe), be serially connected in the voltage sampling circuit on output mos tube current outflow end (being enhancement mode PMOS pipe MP0 drain electrode), relatively sampled signal, reference voltage value obtain the voltage comparator circuit of error signal, by the Buffer driving circuit of error signal drives output mos pipe work.Voltage sampling circuit is made up of the resistance R 1, the R2 that are connected in series, the tie point A point output sampled signal VA of resistance R 1, R2.
Voltage comparator circuit comprises: depletion type NMOS pipe DN1, enhancement mode NMOS pipe MN1, depletion type NMOS pipe DN1 drain electrode meets input power VIN, after the grid of depletion type NMOS pipe DN1, source shorted, connect enhancement mode NMOS pipe MN1 drain electrode, enhancement mode NMOS pipe MN1 source ground, enhancement mode NMOS pipe MN1 grid connects sampled signal, enhancement mode NMOS pipe MN1 drain electrode (B point) output error signal.
Depletion type NMOS pipe DN1 forms reference voltage generating circuit with enhancement mode NMOS pipe MN1, reference voltage generating circuit schematic diagram is as shown in Figure 3: drain electrode, the grid of the gate-source short circuit heel enhancement mode NMOS pipe MN1 of depletion type NMOS pipe DN1 are received together, can obtain reference voltage V ref:
In formula (1), V
tNwith V
tDrepresent respectively the threshold voltage of enhancement mode NMOS pipe MN1 and depletion type NMOS pipe DN1, k
dN1=μ
nc
oX(W/L)
dN1, k
mN1=μ
nc
oX(W/L)
mN1, the threshold value of depletion type NMOS is negative, and depletion type NMOS is all negative temperature coefficient with the threshold value of enhancement mode NMOS, by the breadth length ratio (W/L) of choose reasonable enhancement mode NMOS pipe MN1
mN1and the breadth length ratio DN1 (W/L) of depletion type NMOS pipe
dN1, can obtain the reference voltage V ref of zero-temperature coefficient.In this example, reference voltage generating circuit has voltage ratio concurrently and acts on, and has reduced chip area.
Specific embodiment two
On the basis of embodiment mono-, Buffer driving circuit is done to further optimal design.Buffer driving circuit comprises: enhancement mode PMOS pipe MP1, resistance R 3, enhancement mode NMOS manage MN2, enhancement mode PMOS pipe MP1 source electrode connects input power, one end (D point) of connecting resistance R3 after the grid of enhancement mode PMOS pipe MP1, the short circuit that drains, resistance R 3 another termination enhancement mode NMOS pipe MN2 drain electrodes (C point), enhancement mode NMOS pipe MN2 grid connects enhancement mode NMOS pipe MN1 drain electrode, enhancement mode NMOS pipe MN2 source ground.
In circuit shown in Fig. 2, with drain electrode separately, the grid of enhancement mode NMOS pipe MN1 is connected to resistance R 1 with between resistance R 2 as the input end of voltage comparator circuit to the grid of enhancement mode NMOS pipe MN1, the grid voltage V of enhancement mode NMOS pipe MN1
a=R2*VOUT/ (R1+R2); If V
alower than reference voltage V ref, the output voltage V of voltage comparator circuit
b(being error signal) raises, V
bcontrol the grid of enhancement mode NMOS pipe MN2, V
bthe enhancement mode PMOS pipe MP1 that raises follows enhancement mode PMOS to manage the grid voltage V of MP0
dreduce V
dreduction will make the VOUT voltage VOUT sampled voltage V that raises
aand then raise; If otherwise VOUT sampled voltage V
ahigher than reference voltage V ref, V
breduce V
draise, make V thereby reduce VOUT voltage
avoltage stabilization is at reference voltage value Vref.
In Buffer driving circuit, enhancement mode PMOS pipe MP1 can copy the electric current of enhancement mode PMOS pipe MP0, and the size of copy current is by (W/L)
mP1/ (W/L)
mP0ratio determine, if (W/L)
mP1/ (W/L)
mP0=1/1000, the electric current that flows through voltage sampling circuit is 1 μ A, and in the time that VOUT is unloaded, the electric current of Buffer driving circuit is only 1/1000 μ A (1nA); Along with the increase of load current, Buffer drive current also and then increases, Buffer driving circuit can self-adaptation be chosen suitable drive current to obtain optimum transient response and PSRR performance like this, and alap quiescent dissipation, in taking into account transient response and PSRR performance, greatly reduce the standby current of LDO.
Specific embodiment three
Excessive in order to limit the output current of enhancement mode PMOS pipe MP0, the feature that the present invention utilizes enhancement mode PMOS pipe MP1 in Buffer driving circuit can copy enhancement mode PMOS pipe MP0 electric current has designed current-limiting protection circuit.Current-limiting protection circuit comprises: enhancement mode PMOS manages MP2, enhancement mode NMOS manages MN3, depletion type NMOS manages DN2, enhancement mode PMOS pipe MP2 source electrode connects enhancement mode PMOS pipe MP1 drain electrode, enhancement mode PMOS pipe MP2 grid connects enhancement mode NMOS pipe MN2 drain electrode, enhancement mode PMOS pipe MP2 drain electrode connects depletion type NMOS pipe DN2 drain electrode (E point), depletion type NMOS pipe DN2 grid, ground connection after source shorted, enhancement mode NMOS pipe MN3 drain electrode connects enhancement mode NMOS pipe MN1 drain electrode, enhancement mode NMOS pipe MN3 grid connects depletion type NMOS pipe DN2 drain electrode, enhancement mode NMOS pipe MN3 source ground.Be the switch of Control of Voltage enhancement mode PMOS pipe MP2 by the current conversion of copy by resistance R 3, the cut-off current I of enhancement mode PMOS pipe MP0
mP0can be drawn by formula (2) estimation:
In formula (2), V
tPrepresent the threshold value of enhancement mode PMOS pipe MP2, (W/L)
mP0,(W/L)
mP1be respectively the breadth length ratio of enhancement mode PMOS pipe MP0, enhancement mode PMOS pipe MP1.
In current-limiting protection circuit, depletion type NMOS pipe DN2 manages the current source loads of MP2 as enhancement mode PMOS, in the time that the current value of enhancement mode PMOS pipe MP0 reaches the cut-off current of setting, and I
mP1* R3=V
tP, enhancement mode PMOS pipe MP2 opens, E point voltage V
eraise, open enhancement mode NMOS pipe MN3, the output voltage V of vising voltage comparator circuit
b, the gate voltage of enhancement mode NMOS pipe MN2 cannot further raise, and the gate voltage of enhancement mode PMOS pipe MP0 cannot further be reduced, and the output current of enhancement mode PMOS pipe MP0, reaching after the cut-off current of setting and cannot further increasing, has been realized current-limiting function.
In addition,, in this example, can also substitute depletion type NMOS pipe DN2, current-limiting resistance 1 termination E point, other end ground connection with current-limiting resistance.
Specific embodiment four
On the basis of embodiment noted earlier, design the compensation branch road being connected between enhancement mode NMOS pipe MN1 drain electrode, source electrode, so that enough phase margins to be provided, ensure the stability of whole loop.As shown in Figure 2, compensation branch road is compensating resistance R0 and the building-out capacitor C0 of serial connection.
In the present invention, reference voltage generating circuit has only used DN1 with two transistors of MN1 with voltage comparator circuit, chip area is very little, also very little (lower than the 1 μ A) of electric current consuming, there is not the intrinsic Resistance Thermal Noise of band-gap reference in the reference voltage that this circuit produces, follow MN1 size by preferred DN1, can further reduce the 1/f noise of metal-oxide-semiconductor, so the noise of this reference voltage is far below traditional band-gap reference.LDO entirety quiescent dissipation of the present invention is less than 2 μ A, and the performances such as its output noise, transient response and PSRR can match in excellence or beauty with the LDO of 100 μ A power consumptions of prior art.
Several embodiments that above-described embodiment is only enumerated for the present invention, but be not limiting the scope of the invention, everyly meet the embodiment of invention aim of the present invention and the replacement form that is equal to of above-described embodiment all falls into protection scope of the present invention.
In sum, the present invention has following beneficial effect:
(1) improve traditional reference voltage generating circuit, the grid of output reference voltage metal-oxide-semiconductor no longer with drain electrode short circuit, have the function that produces reference voltage, comparative voltage concurrently, reduce chip area, power consumption is little, noise is low;
(2) pipe of the enhancement mode type PMOS in Buffer driving circuit forms current mirror with output mos pipe MP0, has the function of copy power tube MP0 electric current, can self-adaptation choose suitable drive current to obtain optimum transient response and PSRR performance;
(3) electric current that current-limiting circuit copies to using the enhancement mode PMOS pipe in Buffer driving circuit, as driving signal, reaches and prescribes a time limit clamp voltage comparator circuit output voltage and then realize current-limiting protection at the output current of output power pipe.
Claims (6)
1. low pressure difference linear voltage regulator, comprise: output mos pipe, be serially connected in the voltage sampling circuit on output mos tube current outflow end, relatively sampled signal, reference voltage value obtain the voltage comparator circuit of error signal, by the Buffer driving circuit of error signal drives output mos pipe work
It is characterized in that, described voltage comparator circuit comprises: the first depletion type NMOS pipe (DN1), the first enhancement mode NMOS pipe (MN1), described the first depletion type NMOS pipe (DN1) drain electrode connects input power, after the grid of the first depletion type NMOS pipe (DN1), source shorted, connect the first enhancement mode NMOS pipe (MN1) drain electrode, first enhancement mode NMOS pipe (MN1) source ground, first enhancement mode NMOS pipe (MN1) grid connects sampled signal, the first enhancement mode NMOS pipe (MN1) drain electrode output error signal.
2. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described Buffer driving circuit comprises: the first enhancement mode PMOS pipe (MP1), the first resistance (R3), the second enhancement mode NMOS pipe (MN2), described first enhancement mode PMOS pipe (MP1) source electrode connects input power, the grid of the first enhancement mode PMOS pipe (MP1), after drain electrode short circuit, connect one end of the first resistance (R3), another termination second enhancement mode NMOS pipe (MN2) drain electrode of the first resistance (R3), second enhancement mode NMOS pipe (MN2) grid connects the first enhancement mode NMOS pipe (MN1) drain electrode, second enhancement mode NMOS pipe (MN2) source ground.
3. low pressure difference linear voltage regulator according to claim 2, it is characterized in that, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS pipe (MP2), the 3rd enhancement mode NMOS pipe (MN3), the second depletion type NMOS pipe (DN2), described second enhancement mode PMOS pipe (MP2) source electrode connects the first enhancement mode PMOS pipe (MP1) drain electrode, second enhancement mode PMOS pipe (MP2) grid connects the second enhancement mode NMOS pipe (MN2) drain electrode, the second enhancement mode PMOS pipe (MP2) drain electrode connects the second depletion type NMOS pipe (DN2) drain electrode, second depletion type NMOS pipe (DN2) grid, ground connection after source shorted, the 3rd enhancement mode NMOS pipe (MN3) drain electrode connects the first enhancement mode NMOS pipe (MN1) drain electrode, the 3rd enhancement mode NMOS pipe (MN3) grid connects the second depletion type NMOS pipe (DN2) drain electrode, the 3rd enhancement mode NMOS pipe (MN3) source ground.
4. low pressure difference linear voltage regulator according to claim 2, it is characterized in that, described low pressure difference linear voltage regulator also comprises current-limiting protection circuit, described current-limiting protection circuit comprises: the second enhancement mode PMOS pipe (MP2), the 3rd enhancement mode NMOS pipe (MN3), current-limiting resistance, described second enhancement mode PMOS pipe (MP2) source electrode connects the first enhancement mode PMOS pipe (MP1) drain electrode, second enhancement mode PMOS pipe (MP2) grid connects the second enhancement mode NMOS pipe (MN2) drain electrode, the second enhancement mode PMOS pipe (MP2) drain electrode, the 3rd enhancement mode NMOS pipe (MN3) grid all connects current-limiting resistance one end, the 3rd enhancement mode NMOS pipe (MN3) source electrode, the equal ground connection of the current-limiting resistance other end, the 3rd enhancement mode NMOS pipe (MN3) drain electrode connects the first enhancement mode NMOS pipe (MN1) drain electrode.
5. according to the low pressure difference linear voltage regulator described in claim 3 or 4, it is characterized in that, described low pressure difference linear voltage regulator also comprises the compensation branch road being connected between the first enhancement mode NMOS pipe (MN1) drain electrode, source electrode.
6. low pressure difference linear voltage regulator according to claim 5, it is characterized in that, described compensation branch road comprises compensation electricity (R0), building-out capacitor (C0), described compensating resistance (R0) termination first enhancement mode NMOS pipe (MN1) drain electrode, another termination building-out capacitor (C0) positive plate of compensating resistance (R0), building-out capacitor (C0) negative plate connects first enhancement mode NMOS pipe (MN1) source electrode.
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| CN104793689A (en) * | 2015-04-10 | 2015-07-22 | 无锡中星微电子有限公司 | Reference voltage source circuit |
| CN112462835A (en) * | 2020-11-04 | 2021-03-09 | 昂维格(厦门)科技有限公司 | Low-voltage linear voltage stabilizer |
| CN113031691A (en) * | 2021-03-15 | 2021-06-25 | 江苏硅国微电子有限公司 | Wide-input wide-output depletion tube reference voltage source |
| CN114115425A (en) * | 2022-01-26 | 2022-03-01 | 江苏长晶科技股份有限公司 | Linear voltage stabilizer integrating reference and operational amplifier |
| CN115454188A (en) * | 2022-09-20 | 2022-12-09 | 南京英锐创电子科技有限公司 | Low-power-consumption power supply circuit |
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|---|---|
| CN104049668B (en) | 2015-12-09 |
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