CN210534613U - Low dropout linear voltage stabilizing circuit and integrated circuit - Google Patents
Low dropout linear voltage stabilizing circuit and integrated circuit Download PDFInfo
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- CN210534613U CN210534613U CN201921079856.7U CN201921079856U CN210534613U CN 210534613 U CN210534613 U CN 210534613U CN 201921079856 U CN201921079856 U CN 201921079856U CN 210534613 U CN210534613 U CN 210534613U
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Abstract
A low dropout linear voltage regulator circuit and an integrated circuit, the low dropout linear voltage regulator circuit comprising: the power supply end of the mirror image circuit is used for being connected with a power supply, the input end of the mirror image circuit is connected with a bias current, and the output end of the mirror image circuit respectively outputs a reference current; and a bias circuit comprising a first transistor and a first load that are turned on at a near zero or negative voltage, the bias circuit being self-conducting to form the bias current at the input of the mirror circuit. By means of the characteristic that the threshold voltage of the first transistor is close to zero or negative, the transistor can be conducted automatically to form the bias current at the input end of the mirror circuit, and the mirror circuit copies and generates the reference current according to the bias current.
Description
Technical Field
The application belongs to the technical field of CMOS integrated circuit design, and particularly relates to a low dropout linear voltage stabilizing circuit and an integrated circuit.
Background
Whether the portable electronic equipment is powered by rectified alternating current commercial power or by a storage battery pack, the power supply voltage can be changed in a large range in the working process. The output voltages of the various rectifiers are affected not only by mains voltage variations but also by load variations. In order to ensure that the power supply voltage is stable and constant, almost all electronic equipment is supplied with power by a voltage stabilizer. Small precision electronic devices also require a very clean power supply to avoid affecting the normal operation of the electronic device. In order to meet the requirements of precision electronic equipment, a Low Dropout Regulator (LDO) should be added to the input terminal of the power supply.
The traditional low dropout linear voltage regulator circuit consists of a reference circuit and a control loop. The traditional low dropout linear voltage stabilizing circuit generally consists of a self-biased current mirror, a resistor and a starting circuit, a degenerated bias point irrelevant to a power supply exists, and under the condition of adding a power supply voltage, the traditional low dropout linear voltage stabilizing circuit can be stabilized in a zero working state that each tube is switched off and can also be stabilized in a normal working state. Since the circuit can be stabilized in any one of the above two operating states, a starting circuit is required to generate a starting voltage to enable the circuit to get rid of a zero operating state in which each tube is turned off, so that the circuit structure is more complicated, and the starting circuit also brings extra power consumption.
Disclosure of Invention
An object of the application is to provide a low dropout linear voltage regulator circuit and an integrated circuit, which aim to solve the problems of complex circuit structure and high power consumption of the traditional low dropout linear voltage regulator circuit due to the need of a starting circuit.
A first aspect of an embodiment of the present application provides a low dropout linear voltage regulator circuit, including:
the power supply terminal is used for accessing a power supply;
a common potential terminal for connecting a common potential;
a power supply end of the mirror image circuit is connected with the power supply terminal, and an input end of the mirror image circuit is connected with a bias current;
a bias circuit comprising a first transistor and a first load, wherein the first transistor is turned on at a near-zero voltage or a negative voltage, a first turn-on terminal of the first transistor is connected with an input terminal of the mirror circuit, a second turn-on terminal of the first transistor is connected with a first terminal of the first load, a second terminal of the first load, a gate of the first transistor and a substrate of the transistor are connected with a common potential terminal, and the bias circuit can be turned on by itself to form the bias current at the input terminal of the mirror circuit;
a second load connected between an output terminal of the mirror circuit and a common potential terminal, the mirror circuit mirroring the bias current and acting on the second load to generate a reference voltage at an output terminal;
and an output control loop connected to an output terminal of the mirror circuit, the power supply terminal, and the common potential terminal, the output control loop being configured to generate an output voltage from the reference voltage and output the output voltage at an output terminal.
In one embodiment, the first transistor is a Native NMOS transistor, a drain of the Native NMOS transistor serves as the first pass terminal, and a source of the Native NMOS transistor serves as the second pass terminal.
In one embodiment, the mirror circuit includes a second transistor and a third transistor having the same attribute, a first conduction terminal of the second transistor and a first conduction terminal of the third transistor are used as power supply terminals of the mirror circuit, a second conduction terminal of the second transistor is used as an input terminal of the mirror circuit, a second conduction terminal of the third transistor is used as an output terminal of the mirror circuit, and a gate of the second transistor and a gate of the third transistor are connected in common with the second conduction terminal of the second transistor.
In one embodiment, the second transistor and the third transistor are PMOS transistors, the source of the PMOS transistor serves as the first conduction terminal, and the drain of the PMOS transistor serves as the second conduction terminal.
In one embodiment, the first load and the second load are at least one of a resistor, a capacitor, an inductor, and a transistor.
In one embodiment, the second load includes a fourth transistor which is diode-connected between the output terminal of the mirror circuit and a common potential terminal.
In one embodiment, the output control loop includes an operational amplifier, a feedback network and a power transistor, an inverting input terminal of the operational amplifier is connected to the output terminal of the mirror circuit, a non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback network, a control terminal of the power transistor is connected to the output terminal of the operational amplifier, a first conducting terminal of the power transistor is connected to the power terminal, a second conducting terminal of the power transistor is connected to the first terminal of the feedback network and serves as the output control loop output terminal, and a second terminal of the feedback network is connected to a common potential terminal.
In one embodiment, the feedback network includes a first voltage dividing module and a second voltage dividing module, a first end of the first voltage dividing module is used as a first end of the feedback network, a second end of the first voltage dividing module and a first end of the second voltage dividing module are connected in common and used as an output end of the feedback network, and a second end of the second voltage dividing module is used as a second end of the feedback network.
In one embodiment, the power transistor is a PMOS transistor, and a gate, a source, and a drain of the PMOS transistor are respectively used as the control terminal, the first conducting terminal, and the second conducting terminal.
A second aspect of the embodiments of the present application provides an integrated circuit including the aforementioned low dropout linear voltage regulator circuit.
The reference circuit in the low dropout linear voltage stabilizing circuit is enabled to be self-conducted by means of the characteristic that the threshold voltage of the first transistor is close to zero or negative, so that the bias current is formed at the input end of the mirror circuit, the mirror bias current of the mirror circuit generates the reference current and the reference voltage, and the reference voltage is connected to the output control loop to generate the low dropout linear output voltage.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a circuit diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present application;
FIG. 2 is an exemplary circuit schematic diagram of a reference circuit in the low dropout linear voltage regulator circuit of FIG. 1 providing a reference current;
FIG. 3 is an exemplary circuit schematic of a low dropout linear voltage regulator circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, a low dropout linear voltage regulator circuit that can be integrated in an integrated circuit according to an embodiment of the present application includes a reference circuit and an output control loop.
The reference circuit includes a power supply terminal VCC, a common potential terminal VSS, the mirror circuit 100, the bias circuit 200, and a second load 302.
The power supply terminal VCC is for connection to a power supply, and the common potential terminal VSS is for connection to a common potential, such as ground. The power supply terminal of the mirror circuit 100 is connected to the power supply terminal VCC, the input of the mirror circuit 100The terminal is connected to a bias current Iq, and the mirror circuit 100 mirrors the bias current Iq to output a reference current I _uat an output terminalREF(ii) a The bias circuit 200 includes a first transistor 201 and a first load 202 which are turned on at a near-zero voltage or a negative voltage, a first conducting terminal of the first transistor 201 is connected to the input terminal of the mirror circuit 100, a second conducting terminal of the first transistor 201 is connected to the first terminal of the first load 202, a second terminal of the first load 202, a gate of the first transistor 201, and a substrate of the transistor are connected to a common potential terminal VSS, and the bias circuit 200 can be turned on to form a bias current Iq at the input terminal of the mirror circuit 100. The second load 302 is connected between the output terminal of the mirror circuit 100 and the common potential terminal VSS, and the mirror circuit 100 mirrors the bias current Iq to obtain the reference current I _REFAnd acts on the second load 302 to generate the reference voltage V at the output terminalREF. An output control loop 400 is connected to the output terminal of the mirror circuit 100, the power supply terminal VCC, and the common potential terminal VSS, the output control loop 400 being arranged according to a feedback network and a reference voltage VREFGenerating an output voltage VLDOAnd output at an output terminal, where the output terminal of the output control loop 400 is the output terminal of the low dropout linear voltage regulator circuit. Therefore, the reference circuit can be only stabilized in a normal working state under the condition of adding a power supply, the circuit has no degenerated bias point, a starting circuit is not needed, and the energy consumption is low.
In one embodiment, the first transistor 201 is a Native NMOS transistor NB0, the drain of the Native NMOS transistor NB0 serves as the first turn-on terminal of the first transistor 201, the source of the Native NMOS transistor NB0 serves as the second turn-on terminal of the first transistor 201, and the threshold voltage VT of the Native NMOS transistor NB0Native NMOSThe voltage is a positive voltage or a negative voltage close to zero, and the voltage can be directly conducted under the condition that the reference circuit is connected with a power supply, and the starting circuit is not required to drive. In other embodiments, the first transistor 201 may be another self-turn-on device. The first load 202 and the second load 302 may be active impedances or passive impedances, and the passive impedance resistor RB0 is used as an example in this embodiment. In other embodiments, the first load 202 and the second load 302 may be at least one of a resistor, a capacitor, an inductor, a transistor, and the like.
In one embodiment, referring to fig. 2, the mirror circuit 100 includes a second transistor 101 and a third transistor 102 having the same property, a first conduction terminal of the second transistor 101 and a first conduction terminal of the third transistor 102 are used as power terminals of the mirror circuit 100, a second conduction terminal of the second transistor 101 is used as an input terminal of the mirror circuit 100, a second conduction terminal of the third transistor 102 is used as an output terminal of the mirror circuit 100, and a gate of the second transistor 101 and a gate of the third transistor 102 are connected to a second conduction terminal of the second transistor 101. For example, the second transistor 101 and the third transistor 102 constitute a bipolar basic current mirror, a MOS basic current mirror, or a cascade current mirror.
In one embodiment, the second transistor 101 and the third transistor 102 are PMOS transistors PB0 and PB1, the sources of the PMOS transistors PB0 and PB1 are first conduction terminals, and the drains of the PMOS transistors PB0 and PB1 are second conduction terminals.
The reference circuit acts on a resistor RB0 through the source end of a Native NMOS tube NB0 with the grid grounded, and the threshold voltage VT of the Native NMOS tube NB0 is utilizedNative NMOSNear zero or negative characteristics, resulting in a bias current Iq. The reference current I _uwith different magnitudes is generated by the PMOS tube PB1 mirror bias current IqREF，I_REFN — Iq (n — 1,2,3 …), specifically, a bias current Iq and a reference current I \uREFRespectively as follows:
in one embodiment, referring to fig. 3, the second load 302 is an active impedance, and includes a fourth transistor, which is diode-connected between the output terminal of the mirror circuit 100 and the common potential terminal VSS. Specifically, a first conduction terminal and a gate of the fourth transistor are connected to the output terminal of the mirror circuit 100, and a second conduction terminal of the fourth transistor is connected to the common potential terminal VSS. For example, the fourth transistor is an NMOS transistor NB1, a drain of the NMOS transistor NB1 serves as a first pass terminal of the fourth transistor, and a source of the NMOS transistor NB1 serves as a second pass terminal of the fourth transistor. In other embodiments, the second load 302 may be at least one of a resistor, a capacitor, an inductor, other forms of transistors, and the like.
In this example, the second load 302 is an NMOS transistor, and a mirror bias current n × Iq (n is 1,2,3 …) is applied to the diode-connected NMOS transistor NB1 through the PMOS transistor PB1, thereby generating a reference voltage VREFThe calculation formula is as follows:
wherein KPNB1The device process parameters of the NMOS tube NB 1;
the width-to-length ratio of the NMOS tube NB 1; VTNN1Is the device threshold voltage of the NMOS transistor NB 1.
Referring to fig. 3, the output control loop 400 includes an operational amplifier OPB, a feedback network 402, and a power transistor PB2, wherein an inverting input terminal of the operational amplifier OPB is connected to the output terminal of the mirror circuit 100, a non-inverting input terminal of the operational amplifier OPB is connected to the output terminal of the feedback network 402, a control terminal of the power transistor PB2 is connected to the output terminal of the operational amplifier OPB, a first conductive terminal of the power transistor PB2 is connected to the power terminal VCC, and a second conductive terminal of the power transistor PB2 is connected to the first terminal of the feedback network 402 and serves as the output terminal of the output control loop 400 for outputting an output voltage VLDOThe second terminal of the feedback network 402 is connected to the common potential terminal VSS. The operational amplifier OPB is used to detect and generate an error correction signal, the feedback network 402 is used to detect an output, and the power transistor PB2 is used to regulate and conduct a load current from an unregulated input terminal (i.e., the power supply terminal VCC) to a regulated output terminal (i.e., the output terminal of the low dropout linear voltage regulator circuit).
In one embodiment, the feedback network 402 includes a first voltage dividing module and a second voltage dividing module, a first end of the first voltage dividing module is used as a first end of the feedback network 402, a second end of the first voltage dividing module and a first end of the second voltage dividing module are connected in common and used as an output end of the feedback network 402, and a second end of the second voltage dividing module is used as a second end of the feedback network 402. The first voltage division module and the second voltage division module may be at least one of a resistor, a capacitor, an inductor, other transistors, and the like.
In this embodiment, the first voltage division module and the second voltage division module are exemplified by resistors RB1 and RB2, the power transistor PB2 is exemplified by a PMOS transistor, and a gate, a source, and a drain of the PMOS transistor are exemplified by the control terminal, the first conduction terminal, and the second conduction terminal, respectively. Thus, the output voltage V of the low dropout linear voltage stabilizing circuitLDOThe formula is as follows:
the reference circuit in the low dropout linear voltage regulator circuit is enabled to be self-conducted by virtue of the characteristic that the threshold voltage of the first transistor 201 is close to zero or negative, so that the bias current Iq is formed at the input end of the mirror circuit 100, and the mirror circuit 100 copies and generates the reference current according to the bias current Iq. As can be seen from the above formulas, the reference current and the reference voltage generated by the low dropout linear voltage regulator circuit are independent of the voltage of the power supply terminal VCC.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A low dropout linear voltage regulator circuit, comprising:
the power supply terminal is used for accessing a power supply;
a common potential terminal for connecting a common potential;
a power supply end of the mirror image circuit is connected with the power supply terminal, and an input end of the mirror image circuit is connected with a bias current;
a bias circuit comprising a first transistor and a first load, wherein the first transistor is turned on at a near-zero voltage or a negative voltage, a first turn-on terminal of the first transistor is connected with an input terminal of the mirror circuit, a second turn-on terminal of the first transistor is connected with a first terminal of the first load, a second terminal of the first load, a gate of the first transistor and a substrate of the transistor are connected with a common potential terminal, and the bias circuit can be turned on by itself to form the bias current at the input terminal of the mirror circuit;
a second load connected between an output terminal of the mirror circuit and a common potential terminal, the mirror circuit mirroring the bias current and acting on the second load to generate a reference voltage at the output terminal, the second load including a fourth transistor connected in a diode connection between the output terminal of the mirror circuit and the common potential terminal;
and an output control loop connected to an output terminal of the mirror circuit, the power supply terminal, and the common potential terminal, the output control loop being configured to generate an output voltage from the reference voltage and output the output voltage at an output terminal.
2. The low dropout linear voltage regulator circuit of claim 1 wherein the first transistor is a Native NMOS transistor, the drain of the Native NMOS transistor serves as the first pass terminal, and the source of the Native NMOS transistor serves as the second pass terminal.
3. The low dropout linear voltage regulator circuit of claim 1, wherein the mirror circuit comprises a second transistor and a third transistor of the same attribute, a first conduction terminal of the second transistor and a first conduction terminal of the third transistor are used as power supply terminals of the mirror circuit, a second conduction terminal of the second transistor is used as an input terminal of the mirror circuit, a second conduction terminal of the third transistor is used as an output terminal of the mirror circuit, and a gate of the second transistor and a gate of the third transistor are connected in common with a second conduction terminal of the second transistor.
4. The low dropout linear voltage regulator circuit of claim 3 wherein said second and third transistors are PMOS transistors, the source of said PMOS transistor serving as said first pass terminal and the drain of said PMOS transistor serving as said second pass terminal.
5. The low dropout linear voltage regulator circuit of claim 1 wherein said first load and said second load are at least one of a resistor, a capacitor, an inductor, and a transistor.
6. The low dropout linear voltage regulator circuit according to any one of claims 1 to 5, wherein the output control loop comprises an operational amplifier, a feedback network and a power transistor, wherein an inverting input terminal of the operational amplifier is connected to an output terminal of the mirror circuit, a non-inverting input terminal of the operational amplifier is connected to an output terminal of the feedback network, a control terminal of the power transistor is connected to an output terminal of the operational amplifier, a first conducting terminal of the power transistor is connected to the power terminal, a second conducting terminal of the power transistor is connected to a first terminal of the feedback network and serves as an output terminal of the output control loop, and a second terminal of the feedback network is connected to a common potential terminal.
7. The low dropout linear voltage regulator circuit of claim 6, wherein the feedback network comprises a first voltage divider module and a second voltage divider module, a first terminal of the first voltage divider module is used as a first terminal of the feedback network, a second terminal of the first voltage divider module and a first terminal of the second voltage divider module are connected in common and used as an output terminal of the feedback network, and a second terminal of the second voltage divider module is used as a second terminal of the feedback network.
8. The low dropout linear voltage regulator circuit of claim 6, wherein the power transistor is a PMOS transistor, and the gate, the source, and the drain of the PMOS transistor respectively serve as the control terminal, the first conduction terminal, and the second conduction terminal.
9. An integrated circuit comprising the low dropout linear voltage regulator circuit of any one of claims 1 to 8.
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| CN201921079856.7U CN210534613U (en) | 2019-07-10 | 2019-07-10 | Low dropout linear voltage stabilizing circuit and integrated circuit |
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| CN201921079856.7U CN210534613U (en) | 2019-07-10 | 2019-07-10 | Low dropout linear voltage stabilizing circuit and integrated circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377102A (en) * | 2019-07-10 | 2019-10-25 | 深圳市锐能微科技有限公司 | A kind of low-dropout linear voltage-regulating circuit and integrated circuit |
| CN114879795A (en) * | 2022-06-14 | 2022-08-09 | 北京芯格诺微电子有限公司 | Low dropout regulator capable of realizing voltage domain output |
| CN110377102B (en) * | 2019-07-10 | 2024-06-07 | 深圳市锐能微科技有限公司 | Low-dropout linear voltage stabilizing circuit and integrated circuit |
-
2019
- 2019-07-10 CN CN201921079856.7U patent/CN210534613U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377102A (en) * | 2019-07-10 | 2019-10-25 | 深圳市锐能微科技有限公司 | A kind of low-dropout linear voltage-regulating circuit and integrated circuit |
| CN110377102B (en) * | 2019-07-10 | 2024-06-07 | 深圳市锐能微科技有限公司 | Low-dropout linear voltage stabilizing circuit and integrated circuit |
| CN114879795A (en) * | 2022-06-14 | 2022-08-09 | 北京芯格诺微电子有限公司 | Low dropout regulator capable of realizing voltage domain output |
| CN114879795B (en) * | 2022-06-14 | 2022-11-08 | 北京芯格诺微电子有限公司 | Low dropout regulator capable of realizing voltage domain output |
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