CN108227815B - Self-adaptive dynamic bias LDO circuit applied to low-voltage output - Google Patents
Self-adaptive dynamic bias LDO circuit applied to low-voltage output Download PDFInfo
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- CN108227815B CN108227815B CN201810223884.5A CN201810223884A CN108227815B CN 108227815 B CN108227815 B CN 108227815B CN 201810223884 A CN201810223884 A CN 201810223884A CN 108227815 B CN108227815 B CN 108227815B
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application discloses an adaptive dynamic bias LDO circuit applied to low voltage output, which comprises: a control circuit, a reference voltage generating circuit, a feedback circuit, a load circuit, a power tube M12, the control circuit comprising: PMOS tubes M1, M2, M3, M4 and M12, NMOS tubes M5, M6, M7, M8 and M9 and capacitors C1 and C2, wherein the reference voltage generating circuit comprises: NMOS transistors M10, M11, an operational amplifier EA, a reference voltage circuit bandgap, and the feedback circuit comprises: NMOS tubes M13, M14, the load circuit includes: load capacitor C L Load resistor R L . The circuit structure provided by the application takes the control circuit as a core, and has good load transient response capability and strong adaptability to voltage output compared with the existing LDO circuit. The circuit structure can be widely applied to SoC chips.
Description
Technical Field
The application relates to a system for adjusting electric variable or magnetic variable, in particular to an LDO (Low Dropout Regulator, LDO, low dropout linear regulator) circuit.
Background
Low dropout linear regulator (Low Dropout Regulator, LDO) circuits are widely used in modern electronic devices to provide a regulated voltage that is not subject to supply voltage variations and load variations. Typical application scenarios such as biomedical applications, such devices are generally relatively small, and the power source is generally a storage battery, so that the service life of the storage battery is prolonged, and the application is particularly significant for such small electronic devices. The LDO circuit may provide ultra-low quiescent current to reduce power consumption when the device is in an idle state, standby mode, or sleep mode.
A typical LDO structure is shown in fig. 1, comprising: reference voltage V ref Error amplifier EA, power tube a1, resistor divider a2, current source a3. The LDO circuit automatically detects the output voltage Vout through a resistor divider a2, and an error amplifier EA continuously adjusts a current source a3 so as to maintain the output voltage Vout to be stable at the rated voltage. The LDO circuit with the structure has the problems that the load transient response capability is not strong and the output voltage cannot be quickly responded.
Disclosure of Invention
The purpose of the application is that: an LDO circuit with strong response and adaptability to voltage output is provided.
The application solves the technical problems as follows: an adaptive dynamic bias LDO circuit for low voltage output, comprising: the control circuit, the reference voltage generating circuit, the feedback circuit, the load circuit and the power tube M12; the control circuit includes: PMOS tubes M1, M2, M3, M4 and M12, NMOS tubes M5, M6, M7, M8 and M9, capacitors C1 and C2, wherein sources of the M1, M2, M3, M4 and M12 are all connected with a power supply VDD, a grid of the M1 is connected with a grid of the M2, a drain of the M1 is connected with a drain of the M8, a grid of the M2 is connected with a drain of the M2, a drain of the M2 is connected with a drain of the M5, a grid of the M5 is respectively connected with one end of the capacitor C1, a feedback voltage end a of a feedback circuit, and the capacitorThe other end of the C1 is connected with the drain electrode of the M12, the source electrode of the M5 is respectively connected with the source electrode of the M6 and the drain electrode of the M7, the drain electrode of the M6 is respectively connected with the drain electrode of the M3, the drain electrode of the M4 and the gate electrode of the M12, the gate electrode of the M6 is connected with the reference voltage end b of the reference voltage generating circuit, the gate electrode of the M3 is connected with the gate electrode of the M4, the gate electrode of the M3 is connected with the drain electrode of the M4, the drain electrode of the M4 is respectively connected with the drain electrode of the M9, one end of the C2 is connected with the gate electrode of the M9, the gate electrode of the M8 is connected with the drain electrode of the M8, the other ends of the M7, the M8, the M9 and the C2 are respectively connected with the ground, and the substrates of the M1, the M2, the M3, the M4 and the M12 are all connected with the power supply; the reference voltage generation circuit includes: NMOS tubes M10 and M11, an operational amplifier EA and a reference voltage circuit band, wherein the reference voltage circuit band can output a reference voltage of 1.25V, the output end of the reference voltage circuit band is connected with the non-inverting input end of the operational amplifier EA, the inverting input end of the operational amplifier EA is connected with the output end of the operational amplifier EA, the output end of the operational amplifier EA is respectively connected with the gate and the source of the M10, the gate of the M10 is connected with the gate of the M11, the source of the M10 is connected with the drain of the M11, the connection point of the source of the M10 and the drain of the M11 is the reference voltage end b of the reference voltage generation circuit 2, and the source of the M11 and the substrate of the M10 are respectively connected to the ground; the feedback circuit includes: the drain and the grid of the NMOS tube M13 are connected with the output end c of the self-adaptive dynamic bias LDO circuit applied to low-voltage output, the grid of the M13 is connected with the grid of the M14, the source of the M13 is connected with the drain of the M14, the connection point of the source of the M13 and the drain of the M14 is the feedback voltage end a, and the source of the M14, the substrate and the substrate of the M13 are respectively connected to the ground; the load circuit includes: load capacitor C L Load resistor R L The C is L One end of the filter is connected with the output end c, the other end of the filter is connected with the ground, and the R is L And C L And are connected in parallel.
Further, the M12 is a PMOS power tube.
Further, the reference voltage circuit bandgap is a bandgap reference circuit.
The beneficial effects of the application are as follows: the circuit structure provided by the application takes the control circuit as a core, and has good load transient response capability and strong adaptability to voltage output compared with the existing LDO circuit. The circuit structure can be widely applied to SoC chips.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings described are only some embodiments of the application, but not all embodiments, and that other designs and drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
FIG. 1 is a schematic diagram of a typical LDO circuit in the background art;
FIG. 2 is a schematic diagram of an LDO circuit according to the present application;
fig. 3 is a control loop variation of the control circuit when the output voltage Vout increases;
fig. 4 is a control loop variation of the control circuit when the output voltage Vout decreases.
Detailed Description
The conception, specific structure, and technical effects produced by the present application will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, features, and effects of the present application. It is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present application based on the embodiments of the present application. In addition, all coupling/connection relationships mentioned herein do not refer to direct connection of the components, but rather, refer to the fact that a more optimal coupling structure may be formed by adding or subtracting coupling aids depending on the particular implementation. The technical features in the application can be interactively combined on the premise of no contradiction and conflict.
Example 1 the application is further elucidated below with reference to the accompanying drawings.
Referring to fig. 2, an adaptive dynamic bias LDO circuit applied to low voltage output, comprising: the control circuit 1, the reference voltage generation circuit 2, the feedback circuit 3, the load circuit 4 and the power tube M12, wherein the M12 is a PMOS power tube; the control circuit 1 includes: the PMOS transistors M1, M2, M3, M4 and M12, the NMOS transistors M5, M6, M7, M8 and M9, the capacitors C1 and C2, the sources of M1, M2, M3, M4 and M12 are all connected with a power supply VDD, the grid electrode of M1 is connected with the grid electrode of M2, the drain electrode of M1 is connected with the drain electrode of M8, the grid electrode of M2 is connected with the drain electrode of M2, the drain electrode of M2 is connected with the drain electrode of M5, the grid electrode of M5 is respectively connected with one end of a capacitor C1, the feedback voltage end a of a feedback circuit 3, the other end of the capacitor C1 is connected with the drain electrode of M12, the sources of M5 are respectively connected with the source electrode of M6 and the drain electrode of M7, the drain electrode of M6 are respectively connected with the drain electrode of M3, the grid electrode of M4, the grid electrode of M12 is connected with the reference voltage generating circuit 2, the grid electrode of M3 is connected with the grid electrode b of M4, the grid electrode of M3 is connected with the grid electrode of M3, the grid electrode of M3 is connected with the grid electrode of M4, the grid electrode of M7 is connected with the grid electrode of M4, and the other ends of M4, and the drain electrode of M7 are respectively connected with the drain electrode of M8, the capacitors C7 and the drain electrode of M8 and the drain electrode of M3 is connected with the capacitors C3; the reference voltage generation circuit 2 includes: NMOS tubes M10 and M11, an operational amplifier EA and a reference voltage circuit band, wherein the reference voltage circuit band can output a reference voltage of 1.25V, the output end of the reference voltage circuit band is connected with the non-inverting input end of the operational amplifier EA, the inverting input end of the operational amplifier EA is connected with the output end of the operational amplifier EA, the output end of the operational amplifier EA is respectively connected with the gate and the source of the M10, the gate of the M10 is connected with the gate of the M11, the source of the M10 is connected with the drain of the M11, the connection point of the source of the M10 and the drain of the M11 is the reference voltage end b of the reference voltage generation circuit 2, and the source of the M11 and the substrate of the M10 are respectively connected to the ground; the feedback is provided withThe circuit 3 includes: the drain and the grid of the NMOS tube M13 are connected with the output end c of the self-adaptive dynamic bias LDO circuit applied to low-voltage output, the grid of the M13 is connected with the grid of the M14, the source of the M13 is connected with the drain of the M14, the connection point of the source of the M13 and the drain of the M14 is the feedback voltage end a, and the source of the M14, the substrate and the substrate of the M13 are respectively connected to the ground; the load circuit 4 includes: load capacitor C L Load resistor R L The C is L One end of the filter is connected with the output end c, the other end of the filter is connected with the ground, and the R is L And C L And are connected in parallel.
As an optimization, the reference voltage circuit bandgap is a band gap reference circuit. The voltage stability of the reference voltage circuit bandgap can be improved.
The following quantitatively analyzes the LDO circuit created by the application:
the feedback voltage Vfb at the feedback voltage terminal a is synchronously variable with the output voltage Vout at the output terminal c. As can be seen from fig. 2, M13 is connected in a diode connection manner, and thus in a saturation region, M14 may be in a saturation region or may be in a linear region.
1.1 assuming M14 is in the saturation region, the current I through M13 13 Current I through M14 14 。
V GS11 ＝V out (3)
V GS10 ＝V out -V fb (4)
I 13 ＝I 14 (5)
Wherein K is i ＝μ n,p C ox (W/L) i i＝1,2…
Obtained from (1), (2), (3), (4), (5)
Deriving (6)
1.2 when M14 is operating in triode region, its current formula is
V DS14 ＝V fb (9)
From (1) (5)
From (3) (4) (8) (9) (10)
Deriving (11)
Vout is output voltage, vfb is feedback voltage, V GS Is the gate-source voltage of MOS tube, V DS Is the drain-source voltage of the CMOS transistor. V (V) TH Is the threshold voltage of the CMOS transistor. μn is the mobility of the electron and μp is the mobility of the hole. Cox is the gate capacitance per unit area. W is the conduction channel width, L is the conduction channel length, and (W/L) is the aspect ratio of the CMOS transistor.
In formula (7) we can adjust the aspect ratio of M13 and M14 to a value greater than zero and formula (12) to a value greater than zero. Thus, as can be seen from equations (7) and (12), the derivative between the feedback voltage Vfb and the output voltage Vout is positive, and thus, there is a proportional relationship between them. The feedback voltage Vfb varies with the variation of the output voltage Vout.
Reference voltage generation circuit 2:
the circuit structures of M10, M11, M13 and M14 in the reference voltage generating circuit 2 are the same, the voltage provided by the reference voltage circuit bandgap is 1.25V, and M10 and M11 work in the saturation region, so that the voltage Vref of the reference voltage terminal b:
as can be seen from the equation (13), the reference voltage generating circuit 2 can generate the reference voltage Vref smaller than 1.25V. Thereby enabling the LDO circuit output voltage range to be free from the feedback coefficient limit.
Control circuit 1:
as shown in fig. 2, M5 and M2 are common-source circuits connected by diodes. The current flowing through M5 is
V GS5 ＝V fb (15)
The current flowing through M5 can be obtained by the formulas (14) (15) as
I 5 ＝I 8 (17)
As can be seen from an analysis of the feedback circuit 3, when the output voltage Vout increases, the feedback voltage Vfb of the feedback voltage terminal a increases, and the current flowing through M5 increases as can be seen from the equation (16); when the output voltage Vout decreases, the feedback voltage Vfb at the feedback voltage terminal a decreases, and the current flowing through M5 decreases as shown in equation (16).
Because M1 and M2 form a current mirror structure, the current flowing through M8 is equal to the current flowing through M5, and the current flowing through M5 is increased, the current flowing through M8 is increased, the current flowing through M5 is decreased, and the current flowing through M8 is decreased. The connection mode of M8 is diode connection, which is equivalent to a small signal resistance. Let the resistance of M8 be RM8, the gate voltage of M9 be
V GS9 ＝I 8 R M8 (18)
M9 and M4 form a common source stage circuit taking a current source as a load, wherein the output is the grid voltage of M7. M4 is equivalent to a current source, and has a resistance value of 1/g 4 The current flowing through M9 is
The gate voltage of M7 is
V GS7 ＝VDD-I 9 (1/g 4 ) (20)
From (17) (19) (20)
From equation (21), it is known that when the current flowing through M8 increases, the gate voltage of M7 decreases, and when the current of M8 decreases, the gate voltage of M7 increases.
The current flowing through M7 is
When the gate voltage of M7 increases, the current flowing through M7 increases; when the voltage of M7 decreases, the current flowing through M7 decreases.
It can be seen from FIG. 2 that the current flowing through M7 is equal to the sum of the current flowing through M5 and the current flowing through M6, i.e
I 7 ＝I 5 +I 6 (23)
From the above analysis, when the current flowing through M5 increases, the current flowing through M7 decreases, and as can be seen from equation (23), the current flowing through M6 decreases; when the current flowing through M5 decreases, the current flowing through M7 increases, and as is known from equation (23), the current flowing through M6 increases.
As can be seen from equation (23), when the current I7 flowing through M7 is unchanged, the current flowing through M5 increases, and the current flowing through M6 decreases, and vice versa. The grid voltage of M7 is a dynamic voltage, and the current change trend is the same as that of M6, so that the response to the change of the output voltage can be more flexible and rapid.
Power tube M12:
as can be seen from fig. 2, M3 is a diode connection mode, which can be regarded as a small signal resistor, and if the resistance value is RM3, the gate voltage of the power tube M12 is:
V GS12 ＝I 6 R M3 (24)
the current through M12 is:
and output voltage of
V out ＝I 12 ·Z out (26)
Zout is the output impedance.
Assuming that the current flowing through M6 is changed to ΔI6, the current is obtained by the formulas (24) (25) (26)
As can be seen from the formula (27), when the current I6 flowing through M6 decreases, Δi6 is negative, the output voltage decreases, and the normal state is restored; it can be seen that when the current I6 flowing through M6 increases, Δi6 is positive, the output voltage increases, and the normal state is restored.
In summary, referring to fig. 3, when the output voltage Vout increases, the control loop of the control circuit 1 changes as follows: from an analysis of the feedback circuit 3, it is known that the feedback voltage Vfb increases, and the gate voltage of M5 increases, and from equation (16), the current flowing through M5 increases. M1, M2 constitute a current mirror structure, and thus the current flowing through M8 increases. The current flowing through M8 increases, and the gate voltage of M7 decreases as shown in equation (21), so the current flowing through M7 decreases. Also, because the current flowing through M5 and the current flowing through M6 are equal to the current flowing through M7, when the current flowing through M5 increases, the current flowing through M6 decreases, and when the current flowing through M7 decreases, the current flowing through M6 decreases more rapidly. The current flowing through M6 decreases, and the output voltage Vout decreases and returns to normal as shown in equation (27). Wherein the arrow-up auxiliary mark in fig. 3 indicates an increase in current at the place, the arrow-down auxiliary mark indicates a decrease in current at the place, the upper bump auxiliary mark indicates an increase in voltage at the place, and the lower bump auxiliary mark indicates a decrease in voltage at the place.
Referring to fig. 4, when the output voltage Vout decreases, the control loop of the control circuit 1 changes as follows: from an analysis of the feedback circuit, it is seen that the feedback voltage Vfb decreases, and the gate voltage of M5 decreases, and from equation (16), the current flowing through M5 decreases. M1, M2 constitute a current mirror structure, so that the current flowing through M8 decreases. The current flowing through M8 decreases, and the gate voltage of M7 increases as shown in equation (21), so the current flowing through M7 increases. Also, because the current flowing through M5 and the current flowing through M6 are equal to the current flowing through M7, when the current flowing through M5 decreases, the current flowing through M6 increases, and when the current flowing through M7 increases, the current flowing through M6 increases more rapidly. The current flowing through M6 increases, and the output voltage Vout increases as shown in equation (27) and returns to normal. Wherein the arrow-up auxiliary mark in fig. 4 indicates an increase in current at the place, the arrow-down auxiliary mark indicates a decrease in current at the place, the upper bump auxiliary mark indicates an increase in voltage at the place, and the lower bump auxiliary mark indicates a decrease in voltage at the place.
As proved by simulation tests, compared with the traditional LDO circuit, the LDO circuit provided by the application has good load transient response capability and strong adaptability to voltage output.
While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (3)
1. An adaptive dynamic bias LDO circuit for low voltage output, comprising: a control circuit (1), a reference voltage generating circuit (2), a feedback circuit (3), a load circuit (4) and a power tube M12;
the control circuit (1) includes: the PMOS transistors M1, M2, M3, M4 and M12, the NMOS transistors M5, M6, M7, M8 and M9, the capacitors C1 and C2, the sources of the M1, M2, M3, M4 and M12 are all connected with a power supply VDD, the grid electrode of the M1 is connected with the grid electrode of the M2, the drain electrode of the M1 is connected with the drain electrode of the M8, the grid electrode of the M2 is connected with the drain electrode of the M2, the grid electrode of the M5 is respectively connected with one end of the capacitor C1, the feedback voltage end a of the feedback circuit (3), the other end of the capacitor C1 is connected with the drain electrode of the M12, the sources of the M5 are respectively connected with the source electrode of the M6 and the drain electrode of the M7, the drain electrode of the M6 are respectively connected with the drain electrode of the M3, the drain electrode of the M4, the grid electrode of the M12 is connected with the reference voltage end b of the reference voltage generating circuit (2), the grid electrode of the M3 is connected with the grid electrode of the M4, the grid electrode of the M4 is connected with the grid electrode of the M3, and the other ends of the M4, and the drain electrode of the M7, the M8 and the drain electrode of the capacitors C1, the capacitors C1 and M7 are respectively connected with the drain electrode of the capacitors C8 and M9;
the reference voltage generation circuit (2) includes: NMOS tubes M10 and M11, an operational amplifier EA and a reference voltage circuit band, wherein the reference voltage circuit band can output a reference voltage of 1.25V, the output end of the reference voltage circuit band is connected with the non-inverting input end of the operational amplifier EA, the inverting input end of the operational amplifier EA is connected with the output end of the operational amplifier EA, the output end of the operational amplifier EA is respectively connected with the gate and the source of the M10, the gate of the M10 is connected with the gate of the M11, the source of the M10 is connected with the drain of the M11, the connection point of the source of the M10 and the drain of the M11 is the reference voltage end b of the reference voltage generating circuit (2), and the source of the M11 and the substrate of the M10 are respectively connected with the ground;
the feedback circuit (3) comprises: the drain and the grid of the NMOS tube M13 are connected with the output end c of the self-adaptive dynamic bias LDO circuit applied to low-voltage output, the grid of the M13 is connected with the grid of the M14, the source of the M13 is connected with the drain of the M14, the connection point of the source of the M13 and the drain of the M14 is the feedback voltage end a, and the source of the M14, the substrate and the substrate of the M13 are respectively connected to the ground;
the load circuit (4) includes: load capacitor C L Load resistor R L The C is L One end of the filter is connected with the output end c, the other end of the filter is connected with the ground, and the R is L And C L And are connected in parallel.
2. The adaptive dynamic bias LDO circuit for low voltage output of claim 1, wherein: and M12 is a PMOS power tube.
3. The adaptive dynamic bias LDO circuit applied to low voltage output of claim 1 or 2, wherein: the reference voltage circuit bandgap is a band gap reference circuit.
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| CN110928350A (en) * | 2019-12-11 | 2020-03-27 | 国网山东省电力公司济南供电公司 | Power supply with wide input voltage |
| CN111880596B (en) * | 2020-07-07 | 2022-01-18 | 芯创智（北京）微电子有限公司 | Dynamic bias circuit applied to ultralow static current LDO |
| CN112698679B (en) * | 2020-12-18 | 2022-07-05 | 上海联影医疗科技股份有限公司 | Voltage self-adaptive adjusting system |
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| 段志奎 ; 胡建国 ; 丁一 ; 路崇 ; 丁颜玉 ; 王德明 ; 谭洪舟 .A novel dual-feed low-dropout regulator.Journal of Semiconductors.2015,全文. * |
| 马卓 ; 郭阳 ; 段志奎 ; 谢伦国 ; 陈吉华 ; 余金山 .A fast transient response low dropout regulator with current control methodology.半导体学报.2011,全文. * |
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