CN107783588A - A kind of push-pull type quick response LDO circuit - Google Patents
A kind of push-pull type quick response LDO circuit Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F7/00—Regulating magnetic variables
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a kind of push-pull type quick response LDO circuit, including：First control circuit, second control circuit, the 3rd control circuit, feedback circuit, load circuit, error amplifier EA, power tube MP；The circuit structure of the invention is relative to existing LDO circuit, good performance is respectively provided with the parameters index such as low-power consumption, large load current, high PSRR, transient response, especially had outstanding performance in terms of transient response, meet the development need of following LDO circuit.The circuit structure can be widely applied to SoC chip.
Description
Technical field
The present invention relates to a kind of system for adjusting electric variable or magnetic variable, more particularly to a kind of LDO (Low Dropout
Regulator, LDO, low pressure difference linear voltage regulator) circuit.
Background technology
Almost all of electronic circuit is required for a stable voltage source, and it is maintained in the range of certain tolerance, with true
Protect correct operation (typical cpu circuit only allows the maximum deviation of voltage source and rated voltage to be no more than ± 3%).Fixation electricity
Pressure is provided by some kinds of voltage-stablizer.LDO circuit is exactly a kind of voltage-stablizer therein.
As shown in figure 1, typical LDO circuit includes：Reference voltage Vref, error amplifier EA, power tube a1, resistance point
Depressor a2, current source a3.The LDO circuit passes through resitstance voltage divider a2 automatic detection output voltages Vout, error amplifier EA is continuous
Current source a3 is adjusted so as to maintain output voltage VoutStabilization is in rated voltage.Load transient sound be present in the LDO circuit of the structure
Should be able to power it is not high the problem of.However as the continuous development of integrated circuit, traditional LDO structures can not meet low-power consumption,
The requirement such as large load current, high PSRR, good transient response, therefore need badly and design new-type circuit.
The content of the invention
It is an object of the invention to provide a kind of LDO circuit that can quickly tackle load change, have good transient response.
The present invention solve its technical problem solution be：A kind of push-pull type quick response LDO circuit, including：First
Control circuit, second control circuit, the 3rd control circuit, feedback circuit, load circuit, error amplifier EA, power tube MP；Institute
State first control circuit by：PMOS M1, M3, NMOS tube M2, electric capacity C1, resistance R1 composition, the drain electrode of the M1 respectively with institute
State the draining of M2, the connection of the grid of the M3, electric capacity C1 one end, one end of the other end of the electric capacity C1 and the resistance R1
Connection, the grid of the M1 are connected with the output end of the error amplifier EA, the source electrode of the M1, the source electrode difference of the M3
It is connected with power vd D, the source electrode of the M2 is connected with ground GND, the drain other end with the resistance R1, the institute respectively of the M3
State power tube MPGrid connection, described M1, M3 substrate is connected with the power vd D respectively, the substrate of the M2 with it is described
Ground GND connections；The second control circuit by：PMOS M4, NMOS tube M5, M6 composition, the drain electrode of the M4 respectively with it is described
M5 drain electrode, grid connection, the grid of the M4 are connected with the output end of the error amplifier EA, the source electrode of the M4 and institute
Power vd D connections are stated, the grid of the M5 is connected with the grid of the M6, the drain electrode of the M6 and the MPGrid connection,
Described M5, M6 source electrode are connected with ground GND respectively, and the substrate of the M4 is connected with power vd D, described M5, M6 substrate difference
It is connected with ground GND；3rd control circuit by：PMOS M7, NMOS tube M8, M9, operational amplifier A MP compositions, the AMP
Inverting input the grid with the M4, the output end of the error amplifier EA are connected respectively, the output end of the AMP with
The grid connection of the M7, the source electrode of the M7 are connected with power vd D, the drain electrode and the leakage of the grid, M8 of the M9 of the M7
Pole connects, the drain electrode of the M9 and the MPDrain electrode connection, described M8, M9 source electrode with GND be connected, the substrate of the M7
It is connected with the power vd D, described M8, M9 substrate are connected with ground GND；The feedback circuit by：NMOS tube M10, M11 group
Grid into, M10 drain electrode, grid, the M11 connects the output voltage terminal of the push-pull type quick response LDO circuit,
The output voltage terminal and the MPDrain electrode connection, the source electrode of the M10 respectively with the draining of the M11, the error is put
Big device EA in-phase input end connection, source electrode connection the ground GND, the M11 of the M11 substrate are connected with ground GND；It is described negative
Carry circuit by：Load resistance RL, load capacitance CLComposition, the load resistance RLWith the load capacitance CLAnd connect, the load
Resistance RL, load capacitance CLOne end connect output voltage terminal connection, other end GND connections over the ground；The error amplifier
EA inverting input connection reference voltage Vref。
Further, the power tube MPFor PMOS.
Further, the reference voltage VrefFor the output voltage of band-gap reference circuit.
The beneficial effects of the invention are as follows：The circuit structure of the invention relative to existing LDO circuit, low-power consumption,
Good performance is respectively provided with the parameters index such as large load current, high PSRR, transient response, is especially rung in transient state
Answer aspect to have outstanding performance, meet the development need of following LDO circuit.The circuit structure can be widely applied to SoC chip.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described.Obviously, described accompanying drawing is the part of the embodiment of the present invention, rather than is all implemented
Example, those skilled in the art on the premise of not paying creative work, can also obtain other designs according to these accompanying drawings
Scheme and accompanying drawing.
Fig. 1 is the structural representation of the LDO circuit in background technology；
Fig. 2 is the structural representation of the LDO circuit of the invention；
Fig. 3 is to work as load voltage VoutThe situation of change of control loop during rise；
Fig. 4 is to work as load voltage VoutThe situation of change of control loop during reduction.
Embodiment
Carried out below with reference to the design of embodiment and accompanying drawing to the present invention, concrete structure and caused technique effect clear
Chu, it is fully described by, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is this hair
Bright part of the embodiment, rather than whole embodiments, based on embodiments of the invention, those skilled in the art is not paying
The other embodiment obtained on the premise of creative work, belongs to the scope of protection of the invention.In addition, be previously mentioned in text
All connection/annexations, not singly refer to component and directly connect, and refer to be added deduct by adding according to specific implementation situation
Few couple auxiliary, to form more excellent draw bail.Each technical characteristic in the invention, in not conflicting conflict
Under the premise of can be with combination of interactions.
Embodiment 1, with reference to figure 2, a kind of push-pull type quick response LDO circuit, including：First control circuit 1, second controls
Circuit 2, the 3rd control circuit 3, feedback circuit 4, load circuit 5, error amplifier EA, power tube MP；The power tube MPFor
PMOS, the first control circuit 1 by：PMOS M1, M3, NMOS tube M2, electric capacity C1, resistance R1 composition, the leakage of the M1
Pole respectively with the draining of the M2, the grid of the M3, electric capacity C1 one end are connected, the other end and the electricity of the electric capacity C1
R1 one end connection is hindered, the grid of the M1 is connected with the output end of the error amplifier EA, the source electrode of the M1, the M3
Source electrode be connected respectively with power vd D, the source electrode of the M2 be connected with ground GND, and the grid of the M2 connects reference voltage Vb1, institute
State the M3 other end with the resistance R1, the power tube M respectively of drainingPGrid connection, described M1, M3 substrate difference
It is connected with the power vd D, the substrate of the M2 is connected with described ground GND；The second control circuit 2 by：PMOS M4,
NMOS tube M5, M6 is formed, and the drain electrode with the M5, grid are connected respectively for the drain electrode of the M4, the grid of the M4 and the mistake
Poor amplifier EA output end connection, the source electrode of the M4 are connected with the power vd D, the grid of the grid of the M5 and the M6
Pole connects, the drain electrode of the M6 and the MPGrid connection, described M5, M6 source electrode is connected with ground GND respectively, the M4's
Substrate is connected with power vd D, and described M5, M6 substrate are connected with ground GND respectively；3rd control circuit 3 by：PMOS
M7, NMOS tube M8, M9, operational amplifier A MP compositions, the inverting input of the AMP grid with the M4, the mistake respectively
Poor amplifier EA output end connection, input in the same direction and the reference voltage V of the AMPb2Connection, the output end of the AMP with
The grid connection of the M7, the source electrode of the M7 are connected with power vd D, the drain electrode and the leakage of the grid, M8 of the M9 of the M7
Pole connects, the drain electrode of the M9 and the MPDrain electrode connection, the grid connection reference voltage V of the M8b3, described M8, M9's
Source electrode is connected with ground GND, and the substrate of the M7 is connected with the power vd D, and described M8, M9 substrate are connected with ground GND；It is described
Feedback circuit 4 by：NMOS tube M10, M11 forms, and the drain electrode of the M10, grid, the grid of the M11 connect the push-pull type
The output voltage terminal of quick response LDO circuit, the output voltage terminal and the MPDrain electrode connection, the source electrode of the M10 point
Not with the draining of the M11, the in-phase input end of the error amplifier EA is connected, the source electrode connection ground GND of the M11, institute
The substrate for stating M11 is connected with ground GND；The load circuit 5 by：Load resistance RL, load capacitance CLComposition, the load resistance
RLWith the load capacitance CLAnd connect, the load resistance RL, load capacitance CLOne end connect output voltage terminal connection,
Other end GND connections over the ground；The inverting input connection reference voltage V of the error amplifier EAref.The reference voltage Vref
For the output voltage of band-gap reference circuit, band-gap reference circuit can establish one it is unrelated with power supply and technique, there is temperature
The DC voltage of characteristic, so as to provide a stable voltage Vref for operational amplifier A MP, improve the performance of LDO circuit.
In order to facilitate description, the source electrode of the M10, the draining of the M11, the in-phase input end of the error amplifier EA
Intersection be point A, the output end of the error amplifier EA, the M1 grids, M4 grids, operational amplifier A MP it is anti-phase
The intersection of input is point B, the power tube MPGrid, the draining of the M3, the intersection of the drain electrode of the M6 is point
C.The operation principle of the invention is as follows：
Such as Fig. 3, when load changes, i.e., as output voltage VoutDuring rise, the voltage at point A raises, point A and error
Amplifier EA in-phase input end connection, therefore the voltage rise at point B, M1 grid voltage rise, the electric current for flowing through M1 subtract
Small, then M3 grid voltage reduces.M3 grid voltages reduce, then flow through M3 electric current increase；When point B voltage raise, M4's
Grid voltage increases, then the electric current for flowing through M5 reduces, M6 and M5 composition current mirrors, therefore the electric current for flowing through M6 also subtracts；M3 electricity
Stream increase, M6 electric current reduce, therefore the voltage rise at point C.Voltage rise at point C, then flow through MPElectric current reduce；When
Voltage rise at point B, because it is connected with operational amplifier A MP inverting input, therefore AMP output end voltage reduction,
M7 grid voltage is reduced, and M7 is changed into turning on from original closed mode, then M9 grid voltage rise, the electric current for flowing through M9 increase
Greatly；MPCircuit reduce, M9 electric current increase, by output voltage VoutDrag down, steady load voltage.
As Fig. 4 works as output voltage VoutDuring reduction, the voltage at point A reduces, then EA exit point B voltage reduces, then
M1 grid voltage reduces, and flows through M1 electric current increase, then M3 grid voltage rise.M3 grid voltage rise, flows through M3
Electric current reduce；When voltage at point B reduces, M4 grid voltages reduce, and flow through M4 electric current increase, then flow through M6 electric current
Increase；The electric current for flowing through M3 reduces, and flows through M6 electric current increase, then the voltage at point C reduces, and flows through MP electric current increase, will
Output voltage VoutDraw high, steady load voltage.When voltage at point B reduces, AMP output end voltage is high level, because
M7 is PMOS, so M7 is in closure state, is not worked.I.e. the 3rd control circuit 3 does not work, and is controlled in Fig. 4 with being not drawn into the 3rd
Circuit 3 processed is as prompting.
Quantitative analysis is carried out to circuit below：Term is explained：I1To flow through M1 electric current, I2To flow through M2 electric current, I3For
Flow through M3 electric current, I4To flow through M4 electric current, I5To flow through M5 electric current, I6To flow through M6 electric current, IPTo flow through MPElectricity
Stream, I8To flow through M8 electric current, I9To flow through M9 electric current, I10To flow through M10 electric current, I11To flow through M11 electric current；
1. feedback circuit 4
Voltage at point A is with output voltage VoutSynchronously change.M10 connected mode connects for diode as shown in Figure 2
Connect, therefore be in saturation region, M11 is likely to be at saturation region, it is also possible in linear zone.
1.1 hypothesis M11 are in saturation region
VGS11=Vout (3)
VGS10=Vout-VA (4)
I11=I10 (5)
Wherein Ki=μn,pCox(W/L)iI=1,2 ...
Obtained by formula (1) (2) (3) (4) (5)
Formula (6) derivation is obtained
1.2 when M11 is operated in triode region, and its current formula is
VDS11=VA (9)
It can be obtained by formula (1) (5)
It can be obtained by formula (3) (4) (8) (9) (10)
Formula (11) derivation can be obtained
VAIt is A point voltages, VGSIt is the gate source voltage of metal-oxide-semiconductor, VDSIt is the drain-source voltage of CMOS transistor.VTHIt is CMOS tube
Threshold voltage.μnIt is the mobility of electronics, μpIt is the mobility in hole.CoxIt is unit area gate capacitance.W is that conducting channel is wide
Degree, L is conducting channel length, and (W/L) is the breadth length ratio of CMOS transistor.
We can make its value be more than zero by adjusting M10 and M11 breadth length ratios in formula (7), and formula (12) its value is big
In zero.Therefore, the derivative between the voltage and output voltage at point A it can be seen from formula (7) and (12) is just, therefore they
Between proportional relation.Voltage at point A changes with the change of output.
2. control circuit part,
2.1 first control circuits 1
As shown in Fig. 2 M1 and M2 is the common-source circuits using current source load.Leaked if PMOS electric currents are flowed to by source electrode
Pole, the then electric current for flowing through PMOS M1 are
VGS1=VDD-VB (14)
The B voltage variety of setting up an office is Δ VB, then can be obtained by formula (13) (14)
The Δ V when point B voltage increaseBFor just, Δ V during reductionBIt is negative.Understood by formula (15) when point B voltage increases,
Electric current I1Reduce, when point B voltages reduce, electric current I1Increase.Again because M2 connection bias voltages, equivalent to one current source, its electricity
Flow constant, therefore work as I1M3 grid voltages reduce during reduction, I1M3 grid voltages increase during increase.
The electric current for flowing through M3 is
VGS1=VDD-VG3 (17)
If the variable quantity of M3 grid voltage is Δ VG3, then can be obtained by formula (16) (17)
From formula (18), the I when M3 grid voltages raise3Reduce, the I when M3 grid voltages reduce3Rise.
2.2 second control circuits 2
PMOS M4 in second control circuit 2 and the common-source stage that M5 connected mode is the load connected using diode
Circuit.It is that load is different from the circuit that M1 and M2 is formed, therefore M1 and M4 curent change situation is identical.
M4 load M5 is diode connected mode, so M5 can be equivalent to a small-signal resistance.M5 and M6 and structure
Into current mirror, therefore the electric current in M5 and M6 synchronously changes.
Therefore from the analysis to M1, M4 electric current I is flowed through when point B voltages raise4Reduce, when point B voltages reduce
Flow through M4 electric current I4Increase.As M6 with M5 curent changes, therefore I4I during reduction6Also I is reduced4I during increase6Also increase.
2.3 power tube MP
Flow through MPElectric current be
VGSP=VDD-VC (20)
Output voltage V againoutFor
Vout=Iout·Zout (21)
Iout=α IP (22)
ZoutFor output impedance.
The C voltage change of setting up an office is Δ VC, then can be obtained by formula (19) (20) (21) (22)
The I when a C voltage raises is understood by formula (23)outReduce, Δ VCFor just, output voltage VoutReduce, recover normal
State；I when point C voltage reducesoutIncrease, Δ VCFor just, output voltage VoutRise, recover normal condition, steady load voltage.
2.4 the 3rd control circuits 3
As shown in Fig. 2 M7 connects operational amplifier A MP output ends, M8 meets bias voltage Vb3.M7 and M8 compositions use current source
The common-source stage circuit of load.I8Current formula is
Understood to work as V by formula (24)GS8When smaller, I8Also it is smaller.
Under normal circumstances, the voltage of AMP outputs is vdd voltage, therefore M7 is in by area, because M7 is PMOS,
Only when gate source voltage VGS7 is less than threshold voltage, M7 can just be turned on.
When point B voltages raise, by operational amplifier inverting input, now AMP output voltages are zero, therefore M7 is led
Logical, the 3rd control circuit 3 is started working.Now M9 grid voltages increase.
M9 current formula is
If M7 grid voltages, which become, turns to Δ VGS9, then can be obtained by formula (25)
From formula (26), when M9 grid voltages raise, the electric current increase in M9, by output voltage VoutDrag down.
From analyzing feedback circuit 4, first control circuit 1, second control circuit 2, as output voltage VoutRise
When, the voltage rise at point B, the electric current I in M33Increase, the electric current I in M66Reduce, therefore the voltage at point C is driven high.Point C
The voltage rise at place, then flow through MPCurrent reduction.From the analysis to the 3rd control circuit 3, the voltage at point B raises,
Operational amplifier A MP output end voltage is reduced, and M7 grid voltage is reduced, and M7 turn-on control circuits are started working, therefore M9
Grid voltage be driven high, flow through M9 electric current increase.To sum up, as output voltage VoutDuring rise, MPIn electric current reduce, M9
In electric current increase, by output voltage VoutDrag down, return to normal condition, steady load voltage.
As output voltage VoutDuring reduction, the voltage at point B reduces, and the electric current in M3 reduces, the electric current increase in M6, because
Voltage at this point C is pulled low, and flows through MP electric current increase, output voltage VoutIt is driven high, recovers normal condition, steady load
Voltage.
By emulation, the LDO circuit of the invention within 8ns just the load voltage of LDO circuit can be able to recover
Normal condition, had a clear superiority relative to traditional LDO circuit.
The better embodiment of the present invention is illustrated above, but the invention is not limited to the implementation
Example, those skilled in the art can also make a variety of equivalent modifications on the premise of without prejudice to spirit of the invention or replace
Change, these equivalent modifications or replacement are all contained in the application claim limited range.
Claims (3)
- A kind of 1. push-pull type quick response LDO circuit, it is characterised in that including：First control circuit, second control circuit, Three control circuits, feedback circuit, load circuit, error amplifier EA, power tube MP；The first control circuit by：PMOS M1, M3, NMOS tube M2, electric capacity C1, resistance R1 composition, the drain electrode point of the M1 Not with the draining of the M2, the grid of the M3, electric capacity C1 one end are connected, the other end of the electric capacity C1 and the resistance R1 One end connection, the grid of the M1 is connected with the output end of the error amplifier EA, the source electrode of the M1, the source of the M3 Pole is connected with power vd D respectively, and the source electrode of the M2 is connected with ground GND, and the drain electrode of the M3 is another with the resistance R1 respectively One end, the power tube MPGrid connection, described M1, M3 substrate is connected with the power vd D respectively, the substrate of the M2 It is connected with described ground GND；The second control circuit by：PMOS M4, NMOS tube M5, M6 composition, the drain electrode leakage with the M5 respectively of the M4 Pole, grid connection, the grid of the M4 are connected with the output end of the error amplifier EA, the source electrode of the M4 and the power supply VDD connections, the grid of the M5 are connected with the grid of the M6, the drain electrode of the M6 and the MPGrid connection, the M5, M6 source electrode is connected with ground GND respectively, and the substrate of the M4 is connected with power vd D, described M5, M6 substrate respectively with ground GND Connection；3rd control circuit by：PMOS M7, NMOS tube M8, M9, operational amplifier A MP compositions, the AMP's is anti-phase defeated Entering end, the grid with the M4, the output end of the error amplifier EA are connected respectively, and the output end of the AMP is with the M7's Grid is connected, and the source electrode of the M7 is connected with power vd D, and the drain electrode of the M7 is connected with the drain electrode of the grid, M8 of the M9, institute State M9 drain electrode and the MPDrain electrode connection, described M8, M9 source electrode is connected with ground GND, the substrate of the M7 and the electricity Source VDD connections, described M8, M9 substrate are connected with ground GND；The feedback circuit by：NMOS tube M10, M11 forms, the drain electrode of the M10, grid, the M11 grid connection described in The output voltage terminal of push-pull type quick response LDO circuit, the output voltage terminal and the MPDrain electrode connection, the M10's Source electrode respectively with the draining of the M11, the in-phase input end of the error amplifier EA is connected, the source electrode connection ground of the M11 GND, described M10, M11 substrate are connected with ground GND；The load circuit by：Load resistance RL, load capacitance CLComposition, the load resistance RLWith the load capacitance CLAnd Connect, the load resistance RL, load capacitance CLOne end connect output voltage terminal connection, other end GND connections over the ground；The inverting input connection reference voltage V of the error amplifier EAref。
- A kind of 2. push-pull type quick response LDO circuit according to claim 1, it is characterised in that：The power tube MPFor PMOS.
- A kind of 3. push-pull type quick response LDO circuit according to claim 1 or 2, it is characterised in that：The reference voltage VrefFor the output voltage of band-gap reference circuit.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108227815A (en) * | 2018-03-19 | 2018-06-29 | 佛山科学技术学院 | Adaptive dynamic bias LDO circuit applied to low-voltage output |
| CN109062308A (en) * | 2018-09-29 | 2018-12-21 | 上海华虹宏力半导体制造有限公司 | Voltage-regulating circuit |
| CN111414037A (en) * | 2020-03-10 | 2020-07-14 | 佛山科学技术学院 | L DO voltage stabilizing circuit |
| CN117539318A (en) * | 2024-01-09 | 2024-02-09 | 龙骧鑫睿(厦门)科技有限公司 | Off-chip capacitor LDO circuit with high power supply rejection ratio |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108227815A (en) * | 2018-03-19 | 2018-06-29 | 佛山科学技术学院 | Adaptive dynamic bias LDO circuit applied to low-voltage output |
| CN108227815B (en) * | 2018-03-19 | 2023-11-28 | 佛山科学技术学院 | Self-adaptive dynamic bias LDO circuit applied to low-voltage output |
| CN109062308A (en) * | 2018-09-29 | 2018-12-21 | 上海华虹宏力半导体制造有限公司 | Voltage-regulating circuit |
| CN111414037A (en) * | 2020-03-10 | 2020-07-14 | 佛山科学技术学院 | L DO voltage stabilizing circuit |
| CN117539318A (en) * | 2024-01-09 | 2024-02-09 | 龙骧鑫睿(厦门)科技有限公司 | Off-chip capacitor LDO circuit with high power supply rejection ratio |
| CN117539318B (en) * | 2024-01-09 | 2024-03-26 | 龙骧鑫睿(厦门)科技有限公司 | Off-chip capacitor LDO circuit with high power supply rejection ratio |
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