TWI548964B - Flipped voltage zero compensation circuit - Google Patents

Description

Voltage flip type zero point compensation circuit

The invention relates to the technical field of zero pole/zero pole compensation, in particular to a voltage flip type zero point compensation circuit.

1 is a circuit diagram of a conventional low-dropout voltage regulator, which is, for example, a circuit diagram shown in the U.S. Patent No. 6,710,583. In FIG. 1, a first frequency compensation capacitor 116 is parallel to an upper resistor 30 in a voltage divider, wherein the voltage divider is composed of the upper resistor 30 and a lower resistor. 32 components. The first frequency compensation capacitor 106 and the voltage divider provide a zero/pole pair to increase the phase margin of the circuit at high current loads.

Although the circuit of FIG. 1 can provide a lead zero, however, when the ratio of the upper resistor 30 to the lower resistor 32 (R1/R2) is small, at this time, zero and pole (pole) ) is quite close, which reduces the effect of phase compensation.

"A Frequency Compensation" by Chaitanya K. Chava, José Silva-Martínez, et al. et al., IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 51, No. 6, pp. 1041-1050, 2004 In the paper for Scheme for LDO Voltage Regulators, it provides a low dropout voltage regulator (LDO voltage regulator) technology. FIG. 2 is a transconductance gain enhanced structure disclosed in the paper, which uses an operational transconductance amplifier (OTA) in a feedback to enhance transconductance. Figure 3 is a detailed circuit diagram of Figure 2. As shown in FIG. 3, it includes a diode-connected differential amplifier 310, a source follower 320, and a current mirror 330. The diode-connected differential amplifier 310 acts as a level-shifting buffer to down-shift the DC level to increase the output voltage application range while simultaneously compensating the zero point/ Pole separation. The source follower 320 produces a current associated with a compensation capacitor 340. The current mirror 330 produces a proportional output current.

Although the circuit of Figure 3 can provide excessive phase margin, the voltage headroom of the output voltage is greatly reduced, which limits its application range.

Figure 4 is a circuit diagram of another conventional low-dropout voltage regulator, which is, for example, a circuit diagram shown in U.S. Patent No. 7,746,047. In FIG. 4, a voltage controlled current source (VCCS) 210 is used to inject a small signal current into the node B, and the compensation capacitor 410 is used for zero/pole compensation. However, the voltage Vfb on the node B needs to be greater than 2×Vov, and Vov is the overdrive voltage of the transistors 420 and 430, which limits the application range of the voltage control current source 210. In addition, the poles generated by it are not separated from the zero point. Therefore, there is still room for improvement in the conventional zero pole compensation technique.

The object of the present invention is primarily to provide a voltage flip type zero point compensation circuit that provides better phase compensation to increase circuit stability.

According to a feature of the present invention, the present invention provides a voltage inversion zero compensation circuit for an output terminal for zero/pole compensation. The voltage inversion zero compensation circuit includes a capacitor, an amplifier, and a first current. a mirror and a second current mirror. The capacitor is coupled to the output to receive the voltage at the output. The amplifier is coupled to the capacitor to amplify the voltage at the output. A first current mirror is coupled to the amplifier (Mn1) to amplify the current of the amplifier. The second current mirror is coupled to the first current mirror to amplify the current of the first current mirror, wherein a first end of the second current mirror is coupled to the output via a first external resistor.

116‧‧‧First frequency compensation capacitor

30‧‧‧ Upper resistance

32‧‧‧lower resistance

310‧‧‧Diode connected differential amplifier

320‧‧‧Source follower

330‧‧‧current mirror

340‧‧‧Compensation capacitance

210‧‧‧Voltage Control Current Source

410‧‧‧Compensation capacitance

B‧‧‧ node

420, 430‧‧‧Optoelectronics

500‧‧‧Voltage flip zero compensation circuit

C1‧‧‧ capacitor

Mn1‧‧‧Amplifier

510‧‧‧First current mirror

520‧‧‧second current mirror

IA‧‧‧first current source

IB‧‧‧second current source

IC‧‧‧ third current source

Vbias‧‧‧ bias voltage

Vdd‧‧‧High potential

Gnd‧‧‧ low potential

Mn1‧‧‧First NMOS transistor

Mn2‧‧‧second NMOS transistor

Mn3‧‧‧ third NMOS transistor

Mp1‧‧‧First PMOS transistor

Mp2‧‧‧Second NMOS transistor

FB‧‧‧ first endpoint

Rf1‧‧‧ first external resistor

Rf2‧‧‧ second external resistor

710‧‧Amplifier

800‧‧‧Voltage flip zero compensation circuit

Vout‧‧‧ voltage

Figure 1 is a circuit diagram of a conventional low dropout voltage regulator.

Figure 2 is a conventional transconductance gain enhancement architecture.

Figure 3 is a detailed circuit diagram of Figure 2.

4 is a circuit diagram of another conventional low dropout voltage regulator.

Figure 5 is a circuit diagram of a voltage flip type zero point compensation circuit of the present invention.

6 is a schematic diagram of simulation of a voltage flip type zero point compensation circuit of the present invention and a conventional IEEE paper.

FIG. 7 is a schematic diagram of the operation of the voltage flip type zero point compensation circuit of the present invention.

FIG. 8 is another circuit diagram of a voltage flip type zero point compensation circuit of the present invention.

FIG. 5 is a circuit diagram of a voltage flip type zero point compensation circuit 500 for an output (Vout) for zero/pole compensation in accordance with a preferred embodiment of the present invention. As shown in FIG. 5, the voltage inversion zero compensation circuit 500 includes a capacitor C1, an amplifier Mn1, a first current mirror 510, a second current mirror 520, a first current source IA, and a second current source IB. And a third current source IC.

The capacitor C1 is connected to the output to receive the voltage Vout of the output. The amplifier Mn1 is connected to the capacitor C1 to amplify the voltage Vout at the output. In the preferred embodiment, the amplifier Mn1 is a first NMOS transistor Mn1, and the first NMOS transistor Mn1 is configured as a common gate to amplify the output voltage Vout.

The first current mirror 510 is coupled to the amplifier Mn1 to amplify the current of the amplifier Mn1. The first current mirror 510 is composed of a second NMOS transistor Mn2 and a third NMOS transistor Mn3. The current amplification ratio of the first current mirror 510 is 1:M. The width-to-length ratio (W2/L2) of the second NMOS transistor Mn2 and the aspect ratio (W3/L3) of the third NMOS transistor Mn3 can be achieved, so that the current amplification ratio of the first current mirror 510 can be 1:2.5 (= 2: 5). In the present embodiment, M may be a value greater than 0, preferably a value greater than 1, and M is not limited to an integer. The second current mirror 520 is coupled to the first current mirror 510 to amplify the current of the first current mirror 510. The second current mirror 520 is composed of a first PMOS transistor Mp1 and a second NMOS transistor Mp2. The current amplification ratio of the second current mirror 520 is 1:N, N is preferably a value greater than 1, and N is not limited to an integer. The first terminal FB of the second current mirror 520 is coupled to the output terminal via a first external resistor Rf1.

As shown in FIG. 5, one end of the first current source IA is connected to a high potential Vdd, and the other end is connected to the drain D of the first NMOS transistor Mn1, the gate G of the second NMOS transistor Mn2, and The gate G of the third NMOS transistor Mn3. The source S of the first NMOS transistor Mn1 is connected to one end of the capacitor C1 and the drain D of the second NMOS transistor Mn2. The gate G of the first NMOS transistor Mn1 is connected to a bias voltage Vbias. The other end of the capacitor C1 is connected to the output terminal (Vout).

The source S of the second NMOS transistor Mn2 is connected to a low potential Gnd, the source S of the third NMOS transistor Mn3 is connected to the low potential Gnd, and the drain D thereof is connected to one end of the second current source IB a drain D of the first PMOS transistor Mp1, a gate G of the first PMOS transistor Mp1, and a gate G of the second PMOS transistor Mp2, and the other end of the second current source IB is connected to the gate High potential Vdd.

The source S of the first PMOS transistor Mp1 is connected to the high potential Vdd. The source S of the second PMOS transistor Mp2 is connected to the high potential Vdd, and the drain D thereof is connected to one end of the third current source IC, one end of the first external resistor Rf1, and One end of a second external resistor Rf2. The other end of the third current source IC is connected to the low potential Gnd. The other end of the first external resistor Rf1 is connected to the output terminal. The other end of the second external resistor Rf2 is connected to the low potential Gnd.

As can be seen from FIG. 5, the current flowing through the third NMOS transistor Mn3 is M×IA, the current flowing through the first PMOS transistor Mp1 is M×IA-IB, and the current flowing through the second NMOS transistor Mp2. It is N × [M × IA - IB], so the current flowing through the third current source IC is N × [M × IA - IB].

It can be seen from the circuit analysis that the pole of the voltage inversion zero compensation circuit 500 is expressed by the following formula:

Where W _{p is} the pole, C _{1 is} the capacitance of the capacitor, g _{m1 is} the transconductance of the amplifier Mn1, r _{o1 is} the output impedance of the amplifier Mn1, and g _{m2 is} the second Transconductance of NMOS transistor Mn2.

The zero point of the voltage flip type zero point compensation circuit 500 is expressed by the following formula: Where W _{z is} the zero point, C _{1 is} the capacitance value of the capacitor, Rf1 is the resistance value of the first external resistor Rf1, M is the current amplification ratio of the first current mirror, and N is the current amplification of the second current mirror proportion.

It can be known from the formula (1) and the formula (2) that the ratio of the pole to the zero of the voltage flip type zero point compensation circuit 500 is:

It can be seen from the formula (3) that the pole of the voltage flip type zero point compensation circuit 500 is far from the zero point, and there is no problem that the zero point and the pole point are quite close in the prior art, so the technology of the present invention has phase compensation. effect.

Figure 6 is a diagram of the "A Frequency Compensation Scheme for LDO Voltage Regulators" published by the voltage flip type zero point compensation circuit 500 of the present invention and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 51, No. 6, pp. 1041-1050, 2004. Simulation diagram. As shown in FIG. 6, at a frequency of 37.96 KHz, the maximum compensation phase of the voltage inversion zero compensation circuit 500 of the present invention can reach 79.9°, whereas the maximum compensation phase of the prior art is only 8.2°, regardless of formula (3) or Is the analog knot As a result, the voltage inversion zero compensation circuit 500 of the present invention can separate the pole from the zero point and achieve the purpose of phase compensation, thereby increasing the stability of the system.

FIG. 7 is a schematic diagram of the operation of the voltage inversion zero compensation circuit 500 of the present invention. The voltage inversion zero compensation circuit 500 is applied to the feedback of an amplifier 710 to increase the stability of the amplifier 710.

FIG. 8 is a circuit diagram of a voltage flip type zero point compensation circuit 800 for an output (Vout) for zero/pole compensation in accordance with another preferred embodiment of the present invention. As shown in FIG. 8, the voltage inversion zero compensation circuit 800 includes a capacitor C1, an amplifier Mn1, a first current mirror 510, a second current mirror 520, a first current source IA, and a second current source IB. And a third current source IC.

One end of the capacitor C1 is connected to the output terminal to receive the voltage Vout of the output terminal. The source of the first NMOS transistor Mn1 is connected to the other end of the capacitor C1 to amplify the voltage Vout of the output terminal. The first current mirror 510 includes a second NMOS transistor Mn2 and a third NMOS transistor Mn3. The first current mirror 510 is connected to the first NMOS transistor Mn1, and the source of the second NMOS transistor Mn2 is connected. Up to a low potential Gnd, the source of the third NMOS transistor Mn3 is connected to the low potential Gnd to amplify the current of the amplifier Mn1.

One end of the first current source IA is connected to a high potential Vdd, and the other end is connected to the drain D of the first NMOS transistor Mn1, the gate G of the first NMOS transistor Mn1, and the second NMOS transistor Mn2. The gate G and the gate G of the third NMOS transistor Mn3. The second current mirror 520 includes a first PMOS transistor Mp1 and a second NMOS transistor Mp2. The source S of the first PMOS transistor Mp1 is connected to the high potential Vdd, and the source of the second PMOS transistor Mp2. The pole S is connected to the high potential Vdd.

One end of the second current source IB is connected to the drain D of the third NMOS transistor Mn3, the drain D of the first PMOS transistor Mp1, the gate G of the first PMOS transistor Mp1, and the second The gate G of the PMOS transistor Mp2 is connected to the high potential Vdd at the other end. One end of the third current source IC is connected to the drain D of the second PMOS transistor Mp2, one end of a first external resistor Rf1, and one end of a second external resistor Rf2. The other end of the first external resistor Rf1 is connected to the output terminal, and the other end of the second external resistor (Rf2) is connected to the low potential Gnd. The main difference between FIG. 8 and FIG. 5 is that, in FIG. 5, the gate G of the first NMOS transistor Mn1 is connected to a bias voltage Vbias, and in FIG. 8, the gate G of the first NMOS transistor Mn1 is connected. Connected to one end of the first current source IA, but both can achieve the effect of separating the pole from the zero point.

It can be seen from the foregoing description that the voltage inversion zero compensation circuit 500 of the present invention can separate the pole from the zero point and separate them far apart, and achieve the purpose of phase compensation, thereby increasing the stability of the system.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

500‧‧‧Voltage flip zero compensation circuit

C1‧‧‧ capacitor

Mn1‧‧‧Amplifier

510‧‧‧First current mirror

520‧‧‧second current mirror

IA‧‧‧first current source

IB‧‧‧second current source

IC‧‧‧ third current source

Vbias‧‧‧ bias voltage

Vdd‧‧‧High potential

Gnd‧‧‧ low potential

Mn1‧‧‧First NMOS transistor

Mn2‧‧‧second NMOS transistor

Mn3‧‧‧ third NMOS transistor

Mp1‧‧‧First PMOS transistor

Mp2‧‧‧Second NMOS transistor

FB‧‧‧ first endpoint

Rf1‧‧‧ first external resistor

Rf2‧‧‧ second external resistor

Vout‧‧‧ voltage

Claims (10)

A voltage flip type zero point compensation circuit is used for an output terminal for zero point/pole point compensation, the voltage flip type zero point compensation circuit includes: a capacitor connected to the output end to receive the voltage of the output end; an amplifier, Connected to the capacitor to amplify the voltage at the output; a first current mirror coupled to the amplifier to amplify the current of the amplifier; and a second current mirror coupled to the first current mirror to Current amplification of the first current mirror; wherein a first end of the second current mirror is coupled to the output via a first external resistor. The voltage flip type zero point compensation circuit of claim 1, further comprising a first current source connected to the first current mirror, a second current source connected to the first current mirror and the second current mirror And a third current source is coupled to the second current mirror. The voltage flip type zero point compensation circuit of claim 2, wherein the amplifier is a first NMOS transistor, and the first current mirror is a second NMOS transistor and a third NMOS transistor. The second current mirror is composed of a first PMOS transistor and a second NMOS transistor. The voltage flip type zero point compensation circuit of claim 3, wherein one end of the first current source is connected to a high potential, and the other end is connected to the drain of the first NMOS transistor, the second NMOS a gate of the transistor, and a gate of the third NMOS transistor, a source of the first NMOS transistor is connected to one end of the capacitor, and a drain of the second NMOS transistor, the first NMOS transistor The gate is connected to a bias voltage, and the other end of the capacitor is connected to the output. The voltage flip type zero point compensation circuit according to claim 4, wherein the first NMOS electro-crystal system has a common gate configuration to amplify the output terminal voltage. The voltage flip type zero point compensation circuit of claim 4, wherein the source of the second NMOS transistor is connected to a low potential, and the source of the third NMOS transistor is connected to the low potential, The drain is connected to one end of the second current source, the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor, and the second current source One end is connected to the high potential. The voltage flip type zero point compensation circuit of claim 6, wherein a source of the first PMOS transistor is connected to the high potential, and a source of the second PMOS transistor is connected to the high potential, The drain is connected to one end of the third current source, one end of the first external resistor, and one end of a second external resistor via the first end point, and the other end of the third current source is connected to the low potential, The other end of the first external resistor is connected to the output, and the other end of the second external resistor is connected to the low potential. The voltage flip type zero point compensation circuit described in claim 7 is characterized in that: the pole is represented by the following formula: Where W _{p is} the pole, C _{1 is} the capacitance of the capacitor, g _{m1 is} the transconductance of the amplifier, r _{o1 is} the output impedance of the amplifier, and g _{m2 is} the transconductance of the second NMOS transistor. The voltage flip type zero point compensation circuit according to claim 8, wherein the zero point is represented by the following formula: Where W _{z is} the zero point, C _{1 is} the capacitance value of the capacitor, Rf1 is the resistance value of the first external resistor, M is the current amplification ratio of the first current mirror, and N is the current amplification ratio of the second current mirror . A voltage flip type zero point compensation circuit is used for an output terminal for zero point/pole point compensation. The voltage flip type zero point compensation circuit comprises: a capacitor connected to the output end at one end to receive the voltage of the output end; a first NMOS transistor having a source connected to the other end of the capacitor to amplify the output voltage; a first current mirror comprising a second NMOS transistor and a third NMOS transistor, The source of the second NMOS transistor is connected to a low potential, the source of the third NMOS transistor is connected to the low potential to amplify the current of the first NMOS transistor; and a first current source is connected at one end thereof a high potential, the other end is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor; a second current mirror comprising a first PMOS transistor and a second NMOS transistor, a source of the first PMOS transistor connected to the high potential, and a source of the second PMOS transistor connected to the high potential a second current source, one end of which is connected to the first a drain of the NMOS transistor, a drain of the first PMOS transistor, a gate of the first PMOS transistor, and a gate of the second PMOS transistor, the other end of which is connected to the high potential; a three current source, one end of which is connected to the drain of the second PMOS transistor, one end of a first external resistor, and one end of a second external resistor, and the other end of the first external resistor is connected to the output end, The other end of the second external resistor is connected to the low potential.