CN207301846U - A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis - Google Patents
A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis Download PDFInfo
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Abstract
The utility model discloses a kind of more loop substrate dynamic bias LDO circuits of numerical model analysis, including：Power tube MP, pMOS pipe M1, M3, M5, nMOS pipes M2, M4, M6, M7, M8, operational amplifier A MP, NOT gate INV1, INV2, INV3, INV4, INV5, INV6, with door AND1, AND2.The LDO circuit that the utility model is created tackles the change of load voltage using three control loops, there is provided load transient response ability, by emulation, the LDO circuit that the utility model is created improves 10% load transient response ability with the contrast of existing LDO circuit.The LDO circuit structure that the utility model is created can be widely applied to SoC chip.
Description
Technical field
It the utility model is related to a kind of system for adjusting electric variable or magnetic variable, more particularly to a kind of LDO (Low
Dropout Regulator, LDO, low pressure difference linear voltage regulator) circuit.
Background technology
Almost all of electronic circuit is required for a stable voltage source, it is maintained in the range of certain tolerance, with true
Protect correct operation (typical cpu circuit only allows the maximum deviation of voltage source and rated voltage to be no more than ± 3%).Fixation electricity
Pressure is provided by some kinds of voltage-stablizer.LDO circuit is exactly a kind of voltage-stablizer therein.
As shown in Figure 1, current LDO circuit includes：Reference voltage V ref, error amplifier EA, power tube a1, resistance point
Depressor a2, current source a3.The LDO circuit detects output voltage Vout automatically by resitstance voltage divider a2, and error amplifier EA is not
Disconnected adjustment current source a3 is so as to maintain output voltage Vout stable in rated voltage.There is load wink in the LDO circuit of the structure
The problem of state responding ability is not high.
Utility model content
The purpose of this utility model is to provide a kind of high LDO circuit of load transient response ability.
The solution that the utility model solves its technical problem is：A kind of more loop substrate dynamic bias of numerical model analysis
LDO circuit, including：Power tube MP, pMOS pipe M1, M3, M5, nMOS pipes M2, M4, M6, M7, M8, operational amplifier A MP, NOT gate
INV1, INV2, INV3, INV4, INV5, INV6, with door AND1, AND2, the pMOS pipes M1, M3, power tube MPSource electrode point
It is not connected with power vd D, the grid of the pMOS pipes M1 is connected with the output terminal of the NOT gate INV3, and the NOT gate INV3's is defeated
Enter end to be connected with the output terminal with door AND2, it is described to connect with an input terminal of door AND2 and the output terminal of the NOT gate INV4
Connect, the input terminal with the NOT gate INV4, the output terminal of the NOT gate INV5 connect described and another input terminal of door AND2 respectively
Connect, the input terminal of the NOT gate INV4 is connected with the output terminal of the NOT gate INV5, the input terminal of the NOT gate INV5 with it is described
NOT gate INV6 output terminal connection, the input terminal of the NOT gate INV6, the nMOS pipes M4 source electrode, the nMOS pipes M6 leakage
The drain electrode of pole, the pMOS pipes M5 is all connected to section point, the draining of described nMOS pipes M2, M4, the power tube MPGrid
Pole, the draining of described pMOS pipes M1, M3, the input terminal of the NOT gate INV2 is all connected to first node, the NOT gate INV2's
Output terminal respectively the input terminal with the NOT gate INV1, it is described be connected with an input terminal of door AND1, the NOT gate INV1's is defeated
Outlet is connected with described with another input terminal of door AND1, described to connect with the output terminal of door AND1 and the grid of the nMOS pipes M2
Connect, the power tube MPDrain, the source electrode of the source electrode of the pMOS pipes M5, the nMOS pipes M7, described nMOS pipes M7, M8
Grid is all connected to the voltage output end of the LDO circuit, the source electrode of the nMOS pipes M7, the operational amplifier it is anti-phase defeated
Enter end, the drain electrode of the nMOS pipes M8 is all connected to the 3rd node, output terminal and the power tube of the operational amplifier A MP
MPSubstrate connection, the in-phase input end of the operational amplifier A MP is connected with reference voltage, described pMOS pipes M3, M5, nMOS
The grid of pipe M4, M6 are all connected with bias voltage, and the substrate of described pMOS pipes M1, M3 are connected with power vd D respectively, the nMOS pipes
The substrate of M2, M4, M6, M7, M8 are connected with ground GND respectively, and the source electrode of described nMOS pipes M2, M6, M8 are connected with ground GND respectively.
Further, the power tube MP manages for pMOS.
Further, the reference voltage is the output voltage of band-gap reference circuit.
The beneficial effects of the utility model are：The invention uses three different controls of digital and analog circuit mixing
Loop processed, improves the load response speed of LDO circuit.The circuit structure can be widely applied to SoC chip.
Brief description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing to be used is briefly described.Obviously, described attached drawing is the part of the embodiment of the utility model, rather than entirely
Portion's embodiment, those skilled in the art without creative efforts, can also obtain it according to these attached drawings
His designing scheme and attached drawing.
Fig. 1 is the structure diagram of the LDO circuit in background technology；
Fig. 2 is the structure diagram of the LDO circuit of the invention；
Fig. 3 is the sequence diagram of the 3rd control loop.
Embodiment
Carried out below with reference to the technique effect of the design of embodiment and attached drawing to the utility model, concrete structure and generation
Clearly and completely describe, to be completely understood by the purpose of this utility model, feature and effect.Obviously, described embodiment
It is the part of the embodiment of the utility model, rather than whole embodiments, the embodiment based on the utility model, the skill of this area
The other embodiment that art personnel are obtained without creative efforts, belongs to the model of the utility model protection
Enclose.In addition, all connection/connection relations being previously mentioned in text, not singly refer to component and directly connect, and refer to can be according to specific reality
Situation is applied, by adding or reducing couple auxiliary, to form more preferably draw bail.Each technology in the invention is special
Sign, can be with combination of interactions on the premise of not conflicting conflict.
Embodiment 1, with reference to figure 2, a kind of more loop substrate dynamic bias LDO circuits of numerical model analysis, including：Power tube MP、
PMOS pipe M1, M3, M5, nMOS pipes M2, M4, M6, M7, M8, operational amplifier A MP, NOT gate INV1, INV2, INV3, INV4,
INV5, INV6, with door AND1, AND2, the pMOS pipes M1, M3, power tube MPSource electrode be connected respectively with power vd D, as
Optimization, wherein power tube MPManaged using pMOS, the grid of the pMOS pipes M1 is connected with the output terminal of the NOT gate INV3, described
The input terminal of NOT gate INV3 is connected with the output terminal with door AND2, a described and input terminal of door AND2 and the NOT gate
The output terminal connection of INV4, the input terminal with the NOT gate INV4, the NOT gate respectively with another input terminal of door AND2
The output terminal connection of INV5, the input terminal of the NOT gate INV4 are connected with the output terminal of the NOT gate INV5, the NOT gate INV5
Input terminal be connected with the output terminal of the NOT gate INV6, the input terminal of the NOT gate INV6, the source electrode of the nMOS pipes M4, institute
State the draining of nMOS pipes M6, the drain electrode of the pMOS pipes M5 is all connected to section point B, the drain electrode of described nMOS pipes M2, M4, institute
State power tube MPGrid, the draining of described pMOS pipes M1, M3, the input terminal of the NOT gate INV2 is all connected to first node A,
The output terminal of the NOT gate INV2 respectively the input terminal with the NOT gate INV1, it is described be connected with an input terminal of door AND1, institute
The output terminal for stating NOT gate INV1 is connected with described with another input terminal of door AND1, it is described with the output terminal of door AND1 with it is described
The grid connection of nMOS pipes M2, the power tube MPDrain, the source electrode of the source electrode of the pMOS pipes M5, the nMOS pipes M7,
The grid of described nMOS pipes M7, M8 are all connected to the voltage output end b1 of the LDO circuit, the source electrode of the nMOS pipes M7, institute
The drain electrode for stating the inverting input, the nMOS pipes M8 of operational amplifier is all connected to the 3rd node C, the operational amplifier
The output terminal of AMP and the pMOS pipes MPSubstrate connection, the in-phase input end and reference voltage of the operational amplifier A MP
VrefConnection, as an optimization, the reference voltage VrefThere is provided by band-gap reference circuit, band-gap reference circuit can establish one and electricity
Source and technique are unrelated, have the DC voltage of temperature characteristic, so as to provide a stable voltage for operational amplifier A MP
Vref, improve the performance of LDO circuit.The grid of described pMOS pipes M3, M5 respectively with bias voltage Vbias1, bias voltage Vbias4Even
Connect, the grid of described nMOS pipes M4, M6 respectively with bias voltage Vbias2、Vbias3Connection, the substrate point of described pMOS pipes M1, M3
It is not connected with power vd D, the substrate of described nMOS pipes M2, M4, M6, M7, M8 are connected with ground GND respectively, the nMOS pipes M2,
M6, M8 are connected with ground GND respectively.
When the LDO circuit works, load resistance R is connected over the ground at voltage output end b1LWith load capacitance CL。
The numerical model analysis that the invention is proposed controls the operation principle of more loop substrate dynamic bias LDO circuits such as
Under：
Numerical model analysis controls more loop substrate dynamic bias LDO circuits to share three control loops：First control loop
11 by pMOS pipes MP, nMOS pipes M7, M8 and operational amplifier A MP composition；Second control loop 12 by pMOS pipes M3, M5,
NMOS pipes M4, M6, power tube MPComposition；3rd control loop 13 by pMOS pipes M1, M3, M5, power tube MP, nMOS pipe M2,
M4, M6 and door AND1, AND2, NOT gate INV1-INV6 compositions.
The operation principle of first control loop 11 is：
As the voltage V of voltage output end b1outDuring rise (load change), the voltage V at the 3rd node CCWith the voltage
VoutPlace's voltage synchronously changes, therefore voltage VCAlso increase, the voltage of the output terminal output of operational amplifier A MP becomes
It is low, therefore power tube MPUnderlayer voltage reduce, power tube MPThreshold voltage VTHRise, power tube MPElectric current IPReduce, into
And by voltage VoutPull back so that voltage VoutStablize, steady load voltage.Similarly, as voltage VoutDuring reduction, voltage VCDrop
It is low, the voltage rise of operational amplifier A MP outputs, the power tube MPThreshold voltage VTHReduce, power tube MPElectric current IPIncrease
Greatly, and then by voltage VoutDraw high so that voltage VoutStablize, steady load voltage.
The operation principle of second control loop 12 is as follows：
Under load voltage stable state (load does not change), the electric current I of nMOS pipes M6 is flowed through6Flow through pMOS pipes M3
Electric current I3Twice.As voltage VoutDuring rise, the electric current increase of M5 is flowed through, but it is constant because of the electric current for flowing through M6, therefore flow through
The electric current of M4 reduces, therefore the voltage rise at point A, flows through MPElectric current reduce, drag down the voltage of output, make voltage Vout
Recover normal, steady load voltage.As voltage VoutDuring reduction, the electric current for flowing through M5 reduces, and because flows through the electric current of M6 not
Become, therefore flow through the electric current increase of M4, therefore the voltage at point A reduces, and flows through MPElectric current increase, draw high output voltage,
Make voltage VoutRecover normal, steady load voltage.
The operation principle of 3rd control loop 13 is as follows：
PMOS pipes M1 and nMOS pipe M2 is in off state in the case of load is indeclinable.When load change, flow through M5's
Electric current reduces, because the electric current for flowing through M6 is constant, therefore, the electric current for flowing through M4 increases, and the voltage at point A reduces, the reduction amount
High level pulse is exported by NOT gate INV2, INV1 and with door AND1, turns on nMOS pipes M2.NMOS pipes M2 is dragged down at point A
Voltage, flows through the electric current increase of MP, draws high output voltage, make VoutRecover normal condition, steady load voltage.When load becomes
During change, the electric current for flowing through M5 reduces, and raises the voltage at point B, voltage VBVoltage variety by NOT gate INV6, INV5,
INV4 and door AND2, NOT gate INV3 export a low level pulse, turn on pMOS pipes M1.PMOS pipes M1 draws high the electricity at point A
Pressure, flows through MPElectric current reduce, drag down output voltage, make VoutRecover normal condition, steady load voltage.
Quantitative analysis is carried out to LDO circuit below：
First control loop 11：
1st, first we to voltage VCWith voltage VoutBetween relation analyzed：
NMOS pipes M7 is in saturation region as shown in Figure 2, and nMOS pipes M8's is likely to be at saturation region, it is also possible in linear
Area, below we analyzed in two kinds of situation.
1.1st, assume that nMOS pipes M8 is in saturation region, can must flow through the electric current I of nMOS pipes M7, M87、I8
VGS8=Vout (3)
VGS7=Vout-VC (4)
I7=I8 (5)
Wherein Ki=μn,pCox(W/L)iI=1,2...
VGSIt is the gate source voltage of metal-oxide-semiconductor, VTNIt is the threshold voltage of nMOS pipes.μ n are the mobilities of electronics, and μ p are holes
Mobility.CoxIt is unit area gate capacitance.W is conducting channel width, and L is conducting channel length.
Obtained by formula (1) (2) (3) (4) (5)
Formula (6) derivation can be obtained
(W/L)7It is the breadth length ratio of nMOS pipes M7, (W/L)8It is the breadth length ratio of nMOS pipes M8.Voltage V is understood by formula (7)CWith
Voltage VoutBetween relation it is related with the ratio of the breadth length ratio of nMOS pipe M7 and nMOS pipes M8, it is in a linear relationship.When nMOS is managed
The width of M7, M8 are long to be determined, voltage VCWith voltage VoutBetween relation also determine therewith.We set the width of nMOS pipes M7 and M8
The ratio of long ratio is less than 1, then voltage VCWith VoutBetween directly proportional, voltage VCWith VoutRise and raise.
As voltage VoutChange, if its variable quantity is Δ Vout, can be obtained by formula (6)
Understood to work as Δ V by formula (8)outFor timing, voltage VCRise, as Δ VoutDuring to bear, voltage VCReduce.
When the 1.2nd, assuming that nMOS pipes M8 is in linear zone, the electric current for flowing through nMOS pipes M8 is
The gate source voltage V of nMOS pipes M7GS7, obtained by formula (1) (5)
Obtained by formula (3) (4) (9) (10)
Above formula is arranged
To formula (11) derivation, obtain
(W/L)7It is the breadth length ratio of nMOS pipes M7, (W/L)8It is the breadth length ratio of nMOS pipes M8.Voltage V is understood by formula (12)CWith
VoutBetween relation it is related with the ratio of the breadth length ratio of nMOS pipes M7 and M8, it is in a linear relationship.When the width of nMOS pipes M7, M8 are long
Determine, voltage VCWith VoutBetween relation also determine therewith.We are by setting the breadth length ratio of nMOS pipes M7 and M8, formula
(12) value under radical sign is more than zero, then voltage VCWith VoutBetween directly proportional, voltage VCWith VoutRise and raise.
As voltage VoutChange, if its variable quantity is Δ Vout, obtained by formula (11)
Understood to work as Δ V by formula (13)outFor timing, voltage VCRise, as Δ VoutDuring to bear, voltage VCReduce.
2nd, below we to flowing through power tube MPElectric current IPWith voltage VoutBetween relation analyzed：
From formula (8) (13), as voltage VoutChanges delta VoutWhen
ΔVC=α Δs Vout (14)
α is for constant and more than zero.
If the amplification factor of operational amplifier A MP is Av, the voltage variety at the 3rd node C that sets up an office is Δ VC, then transport
The exporting change amount for calculating amplifier AMP is
AMPout=AVΔVC (15)
The source of metal-oxide-semiconductor serves as a contrast voltage
VSB=VS-VB (16)
Operational amplifier A MP output terminals and power tube MPSubstrate is connected, therefore can be obtained by formula (14) (15) (16)
VSB=VSB-αAVΔVout (17)
VSBFor power tube MPSource electrode and substrate between voltage, VSFor power tube MPSource voltage, VBFor power tube MP
Underlayer voltage, V 'SBFor voltage VoutChanges delta VoutV afterwardsSB。
The threshold voltage of metal-oxide-semiconductor has following relation
It can be obtained by formula (17) (18) (19)
VTHIt is metal-oxide-semiconductor threshold voltage, γ is body-effect coefficient, VSBIt is that source serves as a contrast electrical potential difference, VTH0With Φ F and temperature, technique
It is related, the V when constant temperatureTH0It is constant with Φ F；IPTo flow through power tube MPElectric current, VGSPFor power tube MPGrid source electricity
Pressure, VTPFor pMOS pipe threshold voltages.
From formula (20), as Δ VoutFor on the occasion of when, include Δ VoutRadical sign item in value reduce, therefore quadratic term
Interior value is to increase, therefore electric current IPIt is to reduce.As Δ VoutFor negative value when, include Δ VoutRadical sign item in value increase
Greatly, the value therefore in quadratic term is to reduce, therefore electric current IPIt is increase.
As voltage VoutDuring rise, the voltage V of the 3rd node C of point is understood by formula (8) (13)CWith voltage VoutIt is synchronous
, therefore voltage VCAlso increase, through operational amplifier A MP inverting inputs, the output terminal output electricity of operational amplifier A MP
Buckling is low, and power tube M is understood by formula (17)PUnderlayer voltage reduce, power tube MPSource lining voltage VSBRise, can by formula (20)
Know power tube MPThreshold voltage VTHRise, power tube MPElectric current IPReduce, and then by voltage VoutPull back.Similarly, electricity is worked as
Press VoutDuring reduction, voltage VCReduce, the rise of operational amplifier A MP output voltages, power tube M is understood by formula (17)PSubstrate electricity
Pressure rise, power tube MPSource lining voltage VSBReduce, power tube M is understood by formula (20)PThreshold voltage VTHReduce, power tube MP
Electric current IPIncrease, and then by voltage VoutDraw high, make VoutRecover normal condition, steady load voltage.
Second control loop 12：
Under stable state, the electric current I of nMOS pipes M6 is flowed through6It can be obtained by formula (21)
VGS6=Vbias3 (22)
Because in the bias voltage V of nMOS pipe M6 source electrodesbias3It is fixed, therefore nMOS is flowed through knowable to formula (21) (22)
The electric current I of pipe M66It is constant.Flow through the electric current I of nMOS pipes M66It is the electric current I for flowing through pMOS pipes M33Twice.As voltage VoutDrop
Low, the electric current for flowing through M5 reduces, therefore flows through the electric current I of nMOS pipes M44Increase, electric current I4Increase be equal to electric current I5Reduction
Amount.I4Increase reduce the voltage at point A, therefore, flow through MPElectric current increase, draw high output voltage, make voltage VoutRecover
Normal condition, steady load voltage；As voltage VoutDuring rise, the electric current increase of M5 is flowed through, therefore flows through the electric current I of M44Reduce,
Electric current I4Increase be equal to I5Reduction amount.I4Reduction raise the voltage at point A, therefore, flow through MPElectric current reduce,
Output voltage is dragged down, makes voltage VoutRecover normal condition.
Control loop 13：
Refering to what is shown in Fig. 3, it is followed successively by from top to bottom：Voltage VoutSequence diagram, voltage VASequence diagram, NOT gate INV2 is defeated
The sequence diagram of outlet, the sequence diagram of NOT gate INV1 output terminals, the sequence diagram with door AND1 output terminals, voltage VBSequence diagram, it is non-
The sequence diagram of door INV5 output terminals, the sequence diagram of NOT gate INV4 output terminals, the sequence diagram with door AND2 output terminals.
The voltage V of first node AAWhen not changing, by NOT gate INV2, INV1 and with door AND1, output
It is low level to nMOS pipe M2 grids.As the voltage V of section point BBWhen not changing, by NOT gate INV6, INV5,
INV4 and door AND2 and NOT gate INV3, it is high level to be output to pMOS pipe M1 grid voltages.Therefore pMOS pipe M1 and nMOS pipes M2
It is in off state under normal circumstances.
Understood to work as voltage V by control loop 12outDuring reduction, voltage VAReducing, NOT gate INV2 receives low level pulse,
High level pulse is exported, NOT gate INV1, which receives high level pulse, can produce low level pulse, but produce low level pulse
Before, because the delay that INV1 is produced, INV1 and INV2 have of short duration output and are produced for the situation of high level, at this time with door
AND1 can receive two high level pulses, export high level pulse, turn on nMOS pipes M2, drag down the voltage of A points, flow through MP
Electric current increase, feed back to voltage Vout, make voltage VoutRecover normal condition, steady load voltage；
As voltage VoutSuddenly during rise, B point voltages VBA high level pulse is produced therewith.Therefore NOT gate INV6 can connect
A high level pulse is received, exports low level pulse, by NOT gate INV5, INV5 output high level pulses.INV4 is received
High level pulse, it should produce low level arteries and veins.But before the low level pulse is produced, because the reason for the delay of INV4,
INV4 and INV5 has that of short duration signal is identical, all the situation for high level, is all at this time high level pulse with door AND2 inputs,
Therefore it is high level pulse with door AND2 outputs, exports a low level pulse by NOT gate INV3, turn on pMOS pipes M1.Draw
The voltage of high first node A, flows through MPElectric current reduce, feed back to voltage Vout, make voltage VoutRecover normal condition, stablize negative
Carry voltage.
The time delay that NOT gate produces is tpd, its value can obtain by formula (24)
tpdValue be generally several nanoseconds.Wherein tPHLIt is from the midpoint of input waveform rising edge to defeated for turn on delay time
Go out the time that the midpoint of waveform trailing edge is undergone.tPLHBy time delay, to be from the midpoint of input waveform trailing edge to defeated
Go out the time that the midpoint of waveform rising edge is undergone.
The LDO circuit of the invention tackles the change of load voltage using three control loops, there is provided load transient
Responding ability, by emulation, the load transient that the LDO circuit of the invention improves 10% with the contrast of existing LDO circuit is rung
Should be able to power.
The better embodiment of the utility model is illustrated above, but the invention be not limited to it is described
Embodiment, those skilled in the art can also make a variety of equivalent changes on the premise of without prejudice to the utility model spirit
Type or replacement, these equivalent modifications or replacement are all contained in the application claim limited range.
Claims (3)
1. a kind of more loop substrate dynamic bias LDO circuits of numerical model analysis, including：Power tube MP, it is characterised in that further include：
PMOS pipe M1, M3, M5, nMOS pipes M2, M4, M6, M7, M8, operational amplifier A MP, NOT gate INV1, INV2, INV3, INV4,
INV5, INV6, with door AND1, AND2, the pMOS pipes M1, M3, power tube MPSource electrode be connected respectively with power vd D, it is described
The grid of pMOS pipes M1 is connected with the output terminal of the NOT gate INV3, and the input terminal of the NOT gate INV3 is with described with door AND2's
Output terminal connects, described to be connected with an input terminal of door AND2 with the output terminal of the NOT gate INV4, described another with door AND2
The input terminal with the NOT gate INV4, the output terminal of the NOT gate INV5 are connected one input terminal respectively, and the NOT gate INV4's is defeated
Enter end to be connected with the output terminal of the NOT gate INV5, the input terminal of the NOT gate INV5 and the output terminal of the NOT gate INV6 connect
Connect, the input terminal of the NOT gate INV6, the source electrode of the nMOS pipes M4, the draining of the nMOS pipes M6, the pMOS pipes M5
Drain electrode is all connected to section point, the draining of described nMOS pipes M2, M4, the power tube MPGrid, described pMOS pipes M1, M3
Drain, the input terminal of the NOT gate INV2 is all connected to first node, the output terminal of the NOT gate INV2 respectively with it is described non-
The input terminal of door INV1, it is described be connected with an input terminal of door AND1, the output terminal of the NOT gate INV1 and described and door AND1
Another input terminal connection, described to be connected with the output terminal of door AND1 with the grid of the nMOS pipes M2, the power tube MP's
Drain electrode, the draining of the source electrode of the pMOS pipes M5, the nMOS pipes M7, the grid of described nMOS pipes M7, M8 are all connected to described
The voltage output end of LDO circuit, the source electrode of the nMOS pipes M7, the inverting input of the operational amplifier, nMOS pipes
The drain electrode of M8 is all connected to the 3rd node, the output terminal of the operational amplifier A MP and the power tube MPSubstrate connection, institute
The in-phase input end for stating operational amplifier A MP is connected with reference voltage, and the grid of described pMOS pipes M3, M5, nMOS pipe M4, M6 are equal
Bias voltage is connected, the substrate of described pMOS pipes M1, M3 are connected with power vd D respectively, described nMOS pipes M2, M4, M6, M7, M8
Substrate be connected respectively with ground GND, the source electrode of described nMOS pipes M2, M6, M8 are connected with ground GND respectively.
A kind of 2. more loop substrate dynamic bias LDO circuits of numerical model analysis according to claim 1, it is characterised in that：Institute
State power tube MPManaged for pMOS.
A kind of 3. more loop substrate dynamic bias LDO circuits of numerical model analysis according to claim 1 or 2, it is characterised in that：
The reference voltage is the output voltage of band-gap reference circuit.
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| CN201721345338.6U CN207301846U (en) | 2017-10-16 | 2017-10-16 | A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis |
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| CN201721345338.6U CN207301846U (en) | 2017-10-16 | 2017-10-16 | A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis |
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| CN201721345338.6U Withdrawn - After Issue CN207301846U (en) | 2017-10-16 | 2017-10-16 | A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107544605A (en) * | 2017-10-16 | 2018-01-05 | 佛山科学技术学院 | A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107544605A (en) * | 2017-10-16 | 2018-01-05 | 佛山科学技术学院 | A kind of more loop substrate dynamic bias LDO circuits of numerical model analysis |
| CN107544605B (en) * | 2017-10-16 | 2023-11-28 | 佛山科学技术学院 | Digital-analog hybrid multi-loop substrate dynamic bias LDO circuit |
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