CN108227815A - Adaptive dynamic bias LDO circuit applied to low-voltage output - Google Patents
Adaptive dynamic bias LDO circuit applied to low-voltage output Download PDFInfo
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- CN108227815A CN108227815A CN201810223884.5A CN201810223884A CN108227815A CN 108227815 A CN108227815 A CN 108227815A CN 201810223884 A CN201810223884 A CN 201810223884A CN 108227815 A CN108227815 A CN 108227815A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses the adaptive dynamic bias LDO circuit applied to low-voltage output, including：Control circuit, generating circuit from reference voltage, feedback circuit, load circuit, power tube M12, the control circuit include：PMOS tube M1, M2, M3, M4, M12, NMOS tube M5, M6, M7, M8, M9, capacitance C1, C2, the generating circuit from reference voltage include：NMOS tube M10, M11, operational amplifier EA, reference voltage circuit bandgap, the feedback circuit include：NMOS tube M13, M14, the load circuit include：Load capacitance CL, load resistance RL.The circuit structure of the invention, relative to existing LDO circuit, has good load transient response ability using control circuit as core, adaptable to voltage output.The circuit structure can be widely applied to SoC chip.
Description
Technical field
The present invention relates to a kind of system for adjusting electric variable or magnetic variable, more particularly to a kind of LDO (Low Dropout
Regulator, LDO, low pressure difference linear voltage regulator) circuit.
Background technology
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) circuit is widely used in hyundai electronics
Equipment is not changed and loaded the burning voltage of variation for providing by supply voltage.Typical application scenarios are such as in biomedicine
In application, this kind equipment is generally more small-sized, and power supply is generally accumulator, therefore improves the service life of accumulator, to this kind of small
The meaning of type electronic equipment is especially great.When equipment is in idle condition, standby mode or during sleep pattern, LDO circuit can be with
Ultralow quiescent current is provided to reduce power consumption.
Typical LDO structures as shown in Figure 1, including：Reference voltage Vref, error amplifier EA, power tube a1, electric resistance partial pressure
Device a2, current source a3.The LDO circuit detects output voltage Vout automatically by resitstance voltage divider a2, and error amplifier EA is continuous
Current source a3 is adjusted so as to maintain output voltage Vout stable in rated voltage.There are load transients for the LDO circuit of the structure
Responding ability is not strong, can not be to the voltage fast reaction of output the problem of.
Invention content
The purpose of the present invention is：A kind of reaction and the LDO circuit adaptable to voltage output are provided.
The present invention solve its technical problem solution be：Adaptive dynamic bias LDO applied to low-voltage output
Circuit, including：Control circuit, generating circuit from reference voltage, feedback circuit, load circuit, power tube M12；The control circuit
Including：PMOS tube M1, M2, M3, M4, M12, NMOS tube M5, M6, M7, M8, M9, capacitance C1, C2, described M1, M2, M3, M4, M12
Source electrode connect with power vd D, the grid of the grid of the M1 and M2 connect, and the drain electrode of the M1 is connect with the drain electrode of M8,
The grid of the M2 is connect with its drain electrode, and the drain electrode of the M2 is connect with the drain electrode of the M5, the grid of the M5 respectively with
One end of capacitance C1, the feedback voltage end a connections of feedback circuit, the drain electrode of the other end and M12 of the capacitance C1 connects, described
Drain electrode of the source electrode of M5 respectively with the source electrode of M6, M7 is connect, the M6 drain electrode respectively with the drain electrode of M3, the drain electrode of M4, M12's
Grid connects, the reference voltage end b connections of the grid and generating circuit from reference voltage of the M6, the grid of the M3 and the grid of M4
Pole connects, and the grid of the M3 is connect with its drain electrode, and the grid of the M4 is connect with its drain electrode, the drain electrode difference of the M4
With the drain electrode of M9, the grid of M7, one end connection of C2, the grid of the grid of the M9 and M8 connects, the grid of the M8 and its
Drain electrode connection, the other end of described M7, M8, M9, C2 connects over the ground respectively, the substrate of described M1, M2, M3, M4, M12 with
Power vd D connections, the substrate of described M5, M6, M7, M8, M9 are connected to ground；The generating circuit from reference voltage includes：NMOS
Pipe M10, M11, operational amplifier EA, reference voltage circuit bandgap, the exportable 1.25V of reference voltage circuit bandgap
Reference voltage, the output terminal of the reference voltage circuit bandgap is connect with the in-phase input end of operational amplifier EA, described
The inverting input of operational amplifier EA is connect with its output terminal, and the output terminal of the operational amplifier EA is respectively with M10's
Grid, source electrode connection, the grid of the M10 and the grid of M11 connect, and the drain electrode of the source electrode and M11 of the M10 connects, the source of M10
Source electrode, substrate of the tie point of the drain electrode of pole and M11 for the reference voltage end b, the M11 of generating circuit from reference voltage 2, M10
Substrate connect over the ground respectively；The feedback circuit includes：NMOS tube M13, M14, leakage, grid and the application of the M13
In the output terminal c connections of the adaptive dynamic bias LDO circuit of low-voltage output, the grid connection of the M13 grids and M14,
The drain electrode of the source electrode of M13 and M14 connect, and the tie point of the drain electrode of the source electrode and M14 of the M13 is the feedback voltage end a, institute
Source electrode, the substrate of M14 is stated, the substrate of M13 connects over the ground respectively；The load circuit includes：Load capacitance CL, load resistance RL,
The CLOne end connects the output terminal c, and the other end connects over the ground, the RLWith CLAnd it connects.
Further, the M12 is PMOS power tubes.
Further, the reference voltage circuit bandgap is band-gap reference circuit.
The beneficial effects of the invention are as follows：The circuit structure of the invention is using control circuit as core, relative to existing
LDO circuit has good load transient response ability, adaptable to voltage output.The circuit structure can extensive use
In SoC chip.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described.Obviously, described attached drawing is the part of the embodiment of the present invention rather than all implements
Example, those skilled in the art without creative efforts, can also be obtained according to these attached drawings other designs
Scheme and attached drawing.
Fig. 1 is the structure diagram of typical LDO circuit in background technology；
Fig. 2 is the LDO circuit structure diagram of the invention；
Fig. 3 is the control loop situation of change of the control circuit when output voltage Vout is increased；
Fig. 4 is the control loop situation of change of the control circuit when output voltage Vout is reduced.
Specific embodiment
The technique effect of the design of the present invention, concrete structure and generation is carried out below with reference to embodiment and attached drawing clear
Chu is fully described by, to be completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is this hair
Bright part of the embodiment rather than whole embodiments, based on the embodiment of the present invention, those skilled in the art is not paying
The other embodiment obtained under the premise of creative work, belongs to the scope of protection of the invention.In addition, be previously mentioned in text
All connection/connection relations not singly refer to component and directly connect, and refer to be added deduct by adding according to specific implementation situation
Few couple auxiliary, to form more preferably coupling structure.Each technical characteristic in the invention, in not conflicting conflict
Under the premise of can be with combination of interactions.
Embodiment 1, is below in conjunction with the accompanying drawings further elaborated the invention.
With reference to figure 2, applied to the adaptive dynamic bias LDO circuit of low-voltage output, including：Control circuit 1, with reference to electricity
Generation circuit 2 is pressed, feedback circuit 3, load circuit 4, power tube M12, the M12 are PMOS power tubes；The control circuit 1 is wrapped
It includes：PMOS tube M1, M2, M3, M4, M12, NMOS tube M5, M6, M7, M8, M9, capacitance C1, C2, described M1, M2, M3, M4, M12's
Source electrode is connect with power vd D, and the grid of the M1 and the grid of M2 connect, and the drain electrode of the M1 is connect with the drain electrode of M8, institute
The grid for stating M2 is connect with its drain electrode, and the drain electrode of the M2 is connect with the drain electrode of the M5, the grid of the M5 respectively with electricity
Hold one end of C1, the feedback voltage end a connections of feedback circuit 3, the drain electrode of the other end and M12 of the capacitance C1 connects, described
Drain electrode of the source electrode of M5 respectively with the source electrode of M6, M7 is connect, the M6 drain electrode respectively with the drain electrode of M3, the drain electrode of M4, M12's
Grid connects, and the grid of the M6 connect with the reference voltage end b of generating circuit from reference voltage 2, the grid of the M3 and M4's
Grid connects, and the grid of the M3 is connect with its drain electrode, and the grid of the M4 is connect with its drain electrode, the drain electrode point of the M4
Not with the drain electrode of M9, the grid of M7, one end connection of C2, the grid of the grid of the M9 and M8 connects, the grid of the M8 with
Its drain electrode connection, the other end of described M7, M8, M9, C2 connect over the ground respectively, and the substrate of described M1, M2, M3, M4, M12 are equal
It is connect with power vd D, the substrate of described M5, M6, M7, M8, M9 are connected to ground；The generating circuit from reference voltage 2 includes：
NMOS tube M10, M11, operational amplifier EA, reference voltage circuit bandgap, the reference voltage circuit bandgap are exportable
The reference voltage of 1.25V, the output terminal of the reference voltage circuit bandgap connect with the in-phase input end of operational amplifier EA
It connects, the inverting input of the operational amplifier EA is connect with its output terminal, the output terminal difference of the operational amplifier EA
It being connect with grid, the source electrode of M10, the grid of the M10 and the grid of M11 connect, and the drain electrode of the source electrode and M11 of the M10 connects,
Source electrode, lining of the tie point of the drain electrode of the source electrode and M11 of M10 for the reference voltage end b, the M11 of generating circuit from reference voltage 2
Bottom, the substrate of M10 connect over the ground respectively；The feedback circuit 3 includes：NMOS tube M13, M14, leakage, grid and the institute of the M13
State the grid of the output terminal c connections of the adaptive dynamic bias LDO circuit applied to low-voltage output, the M13 grids and M14
Connection, the drain electrode of the source electrode and M14 of M13 connect, and the tie point of the drain electrode of the source electrode and M14 of the M13 is the feedback voltage
A, source electrode, the substrate of the M14 are held, the substrate of M13 connects over the ground respectively；The load circuit 4 includes：Load capacitance CL, bear
Carry resistance RL, the CLOne end connects the output terminal c, and the other end connects over the ground, the RLWith CLAnd it connects.
As an optimization, the reference voltage circuit bandgap is band-gap reference circuit.Reference voltage circuit can be improved
The voltage-regulation coefficient of bandgap.
Quantitative analysis is carried out to the LDO circuit of the invention below：
Feedback voltage Vfb at a of feedback voltage end is to synchronize variation with the output voltage Vout of output terminal c.It can by Fig. 2
Know that the connection mode of M13 is connected for diode, therefore in saturation region, M14 is likely to be at saturation region, it is also possible in linear
Area.
1.1 hypothesis M14 are in saturation region, pass through the electric current I of M1313, pass through the electric current I of M1414。
VGS11=Vout (3)
VGS10=Vout-Vfb (4)
I13=I14 (5)
Wherein Ki=μn,pCox(W/L)iI=1,2 ...
It is obtained by formula (1) (2) (3) (4) (5)
Formula (6) derivation is obtained
1.2 when M14 is operated in triode region, and current formula is
VDS14=Vfb (9)
It can be obtained by formula (1) (5)
It can be obtained by formula (3) (4) (8) (9) (10)
Formula (11) derivation can be obtained
Vout is output voltage, and Vfb is feedback voltage, VGSIt is the gate source voltage of metal-oxide-semiconductor, VDSIt is the leakage of CMOS transistor
Source voltage.VTHIt is the threshold voltage of CMOS tube.μ n are the mobilities of electronics, and μ p are the mobilities in hole.Cox is unit area grid
Capacitance.W is conducting channel width, and L is conducting channel length, and (W/L) is the breadth length ratio of CMOS transistor.
We can make its value be more than zero by adjusting M13 and M14 breadth length ratios in formula (7), and formula (12) its value is big
In zero.Therefore, just, therefore the derivative it can be seen from formula (7) and (12) between feedback voltage Vfb and output voltage Vout is
Proportional relationship between them.Feedback voltage Vfb changes with the variation of output voltage Vout.
Generating circuit from reference voltage 2：
M10, M11 are identical with the circuit structure that M13, M14 are formed in generating circuit from reference voltage 2, reference voltage circuit
The voltage that bandgap is provided is 1.25V, and M10, M11 are operated in saturation region, therefore the voltage Vref of reference voltage end b：
By formula (13) it is found that generating circuit from reference voltage 2 can generate less than the reference voltage Vref of 1.25V.So as to make
LDO circuit output voltage range breaks away from feedback factor limitation.
Control circuit 1：
As shown in Fig. 2, M5, M2 are the common-source stage circuit connected using diode.The electric current for flowing through M5 is
VGS5=Vfb (15)
The electric current that M5 can must be flowed through by formula (14) (15) is
I5=I8 (17)
By the analysis to feedback circuit 3 it is found that when output voltage Vout is increased, the feedback voltage Vfb of feedback voltage end a
Raising understands that the electric current for flowing through M5 increases by formula (16)；When output voltage Vout is reduced, the feedback voltage of feedback voltage end a
Vfb is reduced, and formula (16) understands that the electric current for flowing through M5 reduces.
Because M1, M2 form current-mirror structure, therefore, the electric current for flowing through M8 is equal with the electric current for flowing through M5, and flows through M5
Electric current increase, the electric current for flowing through M8 just increases, and the electric current for flowing through M5 reduces, and the electric current for flowing through M8 is reduced by.The connection of M8 again
Mode is connected for diode, is equivalent to a small-signal resistance.If the resistance value of M8 is RM8, then the grid voltage of M9 is
VGS9=I8RM8 (18)
M9, M4 composition are using current source as the common-source stage circuit of load, wherein grid voltage of the output for M7.M4 is equivalent to electricity
Stream source, resistance value 1/g4, the electric current for flowing through M9 is
The grid voltage of M7 is
VGS7=VDD-I9(1/g4) (20)
It can be obtained by formula (17) (19) (20)
Understand that the grid voltage of M7 reduces when the electric current for flowing through M8 increases by formula (21), when the electric current of M8 reduces, M7
Grid voltage raising.
The electric current for flowing through M7 is
When the grid voltage raising of M7, the electric current increase of M7 is flowed through；When the voltage of M7 reduces, the electric current for flowing through M7 subtracts
It is small.
The electric current for flowing through M7 as shown in Figure 2 again is equal to the electric current for flowing through M5 and flows through the sum of electric current of M6, i.e.,
I7=I5+I6 (23)
It can be obtained by analyzing above, when the electric current for flowing through M5 increases, the electric current for flowing through M7 reduces, by formula (23) it is found that stream
Electric current through M6 reduces；When the electric current for flowing through M5 reduces, the electric current increase of M7 is flowed through, by formula (23) it is found that flowing through the electricity of M6
Stream increase.
By formula (23) it is found that when the electric current I7 for flowing through M7 is constant, the electric current increase of M5 is flowed through, then the electric current for flowing through M6 subtracts
Small, vice versa.And the grid voltage of M7 is dynamic electric voltage, the variation tendency of electric current is identical with M6, therefore can be to output
The reacting condition of voltage is more flexible rapid.
Power tube M12：
As shown in Figure 2, M3 is the mode of diode connection, is considered as small-signal resistance, if its resistance value is RM3, then may be used
The grid voltage of power tube M12 is：
VGS12=I6RM3 (24)
The electric current for flowing through M12 is：
Output voltage is again
Vout=I12·Zout (26)
Zout is output impedance.
If the curent change for flowing through M6 is Δ I6, then can be obtained by formula (24) (25) (26)
It understands to reduce as the electric current I6 for flowing through M6 by formula (27), Δ I6 is negative, and output voltage reduces, and restores normal condition；
Understand that Δ I6 is just, output voltage raising restores normal condition when the electric current I6 increases for flowing through M6.
To sum up, with reference to figure 3, when output voltage Vout is increased, the variation of the control loop of control circuit 1 is as follows：By right
The analysis of feedback circuit 3 understands that feedback voltage Vfb increases, and the grid voltage of M5 also increases, and understands to flow by formula (16)
Electric current increase through M5.M1, M2 form current-mirror structure, therefore flow through the electric current increase of M8.The electric current increase of M8 is flowed through, by formula
(21) understanding the grid voltage of M7 reduces, therefore the electric current for flowing through M7 reduces.Again because flowing through the electric current of M5 and flowing through the electricity of M6
Stream is equal to the electric current for flowing through M7, therefore when the electric current for flowing through M5 increases, the electric current for flowing through M6 reduces, and have the electric current for flowing through M7
Reduce, then the reduction for flowing through M6 electric currents is rapider.The electric current for flowing through M6 reduces, and output voltage Vout drops are understood by formula (27)
It is low, restore normal.Wherein, the upward aid mark of arrow refers to that the electric current at this increases in Fig. 3, the downward auxiliary mark of arrow
Note refers to that the electric current at this reduces, and the aid mark of upper protuberance refers to the voltage raising at this, the aid mark of lower protuberance
Refer to that the voltage at this reduces.
With reference to figure 4, when output voltage Vout is reduced, the control loop variation of control circuit 1 is as follows：By to feedback circuit
Analysis understand that feedback voltage Vfb decreases, the grid voltage of M5 also decreases, and is understood to flow through the electric current of M5 by formula (16)
Reduce.M1, M2 form current-mirror structure, therefore the electric current for flowing through M8 reduces.The electric current for flowing through M8 reduces, and M7 is understood by formula (21)
Grid voltage raising, therefore flow through M7 electric current increase.It is flowed through again because the electric current for flowing through M5 is equal to the electric current for flowing through M6
The electric current of M7, therefore when the electric current for flowing through M5 reduces, flow through the electric current increase of M6, and have the electric current increase for flowing through M7, then it flows
Increase through M6 electric currents is rapider.The electric current increase of M6 is flowed through, output voltage Vout raisings are understood by formula (27), are restored just
Often.Wherein, the upward aid mark of arrow refers to that the electric current at this increases in Fig. 4, and the downward aid mark of arrow refers to
Electric current at this reduces, and the aid mark of upper protuberance refers to the voltage raising at this, and the aid mark of lower protuberance refers to this
The voltage at place reduces.
By emulation testing it is found that the LDO circuit of the invention has good load relative to traditional LDO circuit
Transient response ability, it is adaptable to voltage output.
The better embodiment of the present invention is illustrated, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent modifications under the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent modifications or replacement are all contained in the application claim limited range.
Claims (3)
1. the adaptive dynamic bias LDO circuit applied to low-voltage output, which is characterized in that including：Control circuit (1), ginseng
Examine voltage generation circuit (2), feedback circuit (3), load circuit (4), power tube M12；
The control circuit (1) includes：PMOS tube M1, M2, M3, M4, M12, NMOS tube M5, M6, M7, M8, M9, capacitance C1, C2,
The source electrode of described M1, M2, M3, M4, M12 are connect with power vd D, and the grid of the M1 and the grid of M2 connect, the M1's
Drain electrode is connect with the drain electrode of M8, and the grid of the M2 is connect with its drain electrode, and the drain electrode of the M2 is connect with the drain electrode of the M5,
The grid of M5 one end with capacitance C1 respectively, the feedback voltage end a connections of feedback circuit (3), the capacitance C1's is another
End is connect with the drain electrode of M12, and the drain electrode of the source electrode of the M5 respectively with the source electrode of M6, M7 is connect, the drain electrode of the M6 respectively with
The drain electrode of M3, the drain electrode of M4, the grid connection of M12, the grid of the M6 and the reference voltage end of generating circuit from reference voltage (2)
The grid of b connections, the grid of the M3 and M4 connect, and the grid of the M3 is connect with its drain electrode, the grid of the M4 and its
Drain electrode connection, the M4 drain electrode respectively with the drain electrode of M9, the grid of M7, C2 one end connection, the grid and M8 of the M9
Grid connection, the grid of the M8 connect with its drain electrode, and the other end of described M7, M8, M9, C2 connect over the ground respectively, institute
The substrate for stating M1, M2, M3, M4, M12 is connect with power vd D, and the substrate of described M5, M6, M7, M8, M9 are connected to ground；
The generating circuit from reference voltage (2) includes：NMOS tube M10, M11, operational amplifier EA, reference voltage circuit
Bandgap, the reference voltage of the exportable 1.25V of reference voltage circuit bandgap, the reference voltage circuit bandgap
Output terminal connect with the in-phase input end of operational amplifier EA, the inverting input of the operational amplifier EA and its output
End connection, the output terminal of the operational amplifier EA are connect respectively with the grid of M10, source electrode, the grid of the M10 and the grid of M11
Pole connects, and the drain electrode of the source electrode and M11 of the M10 connects, and the tie point of the drain electrode of the source electrode and M11 of M10 is produced for reference voltage
Source electrode, the substrate of the reference voltage end b, the M11 of raw circuit (2), the substrate of M10 connect over the ground respectively；
The feedback circuit (3) includes：NMOS tube M13, M14, the leakage of the M13, grid are applied to low-voltage output with described
Adaptive dynamic bias LDO circuit output terminal c connections, the grid of the M13 grids and M14 connects, the source electrode of M13 with
The drain electrode connection of M14, the tie point of the drain electrode of the source electrode and M14 of the M13 are the feedback voltage end a, the source of the M14
Pole, substrate, the substrate of M13 connect over the ground respectively；
The load circuit (4) includes：Load capacitance CL, load resistance RL, the CLOne end connects the output terminal c, the other end
It connects over the ground, the RLWith CLAnd it connects.
2. the adaptive dynamic bias LDO circuit according to claim 1 applied to low-voltage output, it is characterised in that：
The M12 is PMOS power tubes.
3. the adaptive dynamic bias LDO circuit according to claim 1 or 2 applied to low-voltage output, feature exists
In：The reference voltage circuit bandgap is band-gap reference circuit.
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| CN201810223884.5A CN108227815B (en) | 2018-03-19 | 2018-03-19 | Self-adaptive dynamic bias LDO circuit applied to low-voltage output |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810223884.5A CN108227815B (en) | 2018-03-19 | 2018-03-19 | Self-adaptive dynamic bias LDO circuit applied to low-voltage output |
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| CN108227815B CN108227815B (en) | 2023-11-28 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110928350A (en) * | 2019-12-11 | 2020-03-27 | 国网山东省电力公司济南供电公司 | Power supply with wide input voltage |
| CN111880596A (en) * | 2020-07-07 | 2020-11-03 | 芯创智（北京）微电子有限公司 | Dynamic bias circuit applied to ultralow static current LDO |
| CN112698679A (en) * | 2020-12-18 | 2021-04-23 | 上海联影医疗科技股份有限公司 | Voltage self-adaptive adjusting system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111880596B (en) * | 2020-07-07 | 2022-01-18 | 芯创智（北京）微电子有限公司 | Dynamic bias circuit applied to ultralow static current LDO |
| CN112698679A (en) * | 2020-12-18 | 2021-04-23 | 上海联影医疗科技股份有限公司 | Voltage self-adaptive adjusting system |
| CN112698679B (en) * | 2020-12-18 | 2022-07-05 | 上海联影医疗科技股份有限公司 | Voltage self-adaptive adjusting system |
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