CN110568895A - Circuit for LDO adaptive leakage compensation - Google Patents
Circuit for LDO adaptive leakage compensation Download PDFInfo
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- CN110568895A CN110568895A CN201910961954.1A CN201910961954A CN110568895A CN 110568895 A CN110568895 A CN 110568895A CN 201910961954 A CN201910961954 A CN 201910961954A CN 110568895 A CN110568895 A CN 110568895A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a circuit for LDO adaptive leakage compensation, wherein the grid of a power supply PMOS (P-channel metal oxide semiconductor) tube MPP of an LDO is connected with the output of an error amplifier EA, and the circuit is characterized in that: the circuit is connected between a source electrode and a drain electrode of the MPP, and the circuit is formed by connecting a sampling PMOS tube MPS and a pair of NMOS tubes, wherein a grid electrode of the MPS and common sources of the MPP and the MPS are both connected with an input VIN, a common drain electrode of the MPP and MN2 is an output VOUT, a common drain electrode of the MPS and MN1 is connected with common grid electrodes of MN1 and MN2, and common sources of the two NMOS tubes are grounded; and the size ratio of MPS to MPP is 1: the size ratio of K1, MN1 and MN2 was 1: k2, K2 is greater than K1. The adaptive compensation circuit has simple and practical structure, adaptively tracks the generated leakage current by sampling the PMOS tube, and completely removes the leakage current by the connected NMOS tubes, thereby ensuring the output stability of the LDO in the temperature conversion environment, generating no static current in the circuit at normal temperature and being beneficial to optimizing design parameters.
Description
Technical Field
The invention relates to a circuit design for optimizing the performance of an LDO (low dropout regulator), in particular to a circuit for compensating electric leakage of the LDO in response to temperature fluctuation self-adaption.
Background
the conventional linear voltage regulator, such as 78XX series chips, requires that the input voltage is at least 2V ~ 3V higher than the output voltage, otherwise the conventional linear voltage regulator cannot work normally, but in some cases, the condition is obviously too harsh, such as 5V to 3.3V, the voltage difference between the input and the output is only 1.7V, and obviously the condition does not meet the working condition of the conventional linear voltage regulator.
An LDO is a linear regulator that uses a transistor or Field Effect Transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. By droop voltage is meant the minimum value of the difference between the input voltage and the output voltage required by the regulator to maintain the output voltage within 100mV above or below its nominal value. LDO (low dropout) regulators with a positive output voltage typically use a power transistor (also called pass device) as the PNP. This transistor allows saturation so the regulator can have a very low dropout voltage, typically around 200 mV; in contrast, the voltage drop of the conventional linear regulator using the NPN composite power transistor is about 2V. The negative output LDO uses an NPN as its pass device, which operates in a similar mode as the PNP device of the positive output LDO.
However, when the operating environment of the LDO with a positive output voltage is heated, the POWER supply MOS (POWER MOS) thereof will generate leakage current with increased proportionality, and if the load current of the LDO is smaller than the leakage current in the operating state, the output performance of the LDO will be greatly reduced, and the LDO will be abnormal.
Disclosure of Invention
The invention aims to provide a circuit for LDO adaptive leakage compensation, which eliminates the influence of self-generated leakage current on the output performance of the LDO in a high-temperature environment.
The technical solution of the present invention for achieving the above object is a circuit for LDO adaptive leakage compensation, wherein a gate of a power supply PMOS transistor MPP of the LDO is connected to an output of an error amplifier EA, and the circuit is characterized in that: the circuit is connected between a source electrode and a drain electrode of a power supply PMOS (P-channel metal oxide semiconductor) tube MPP, and the circuit is formed by connecting a sampling PMOS tube MPS and a pair of NMOS (N-channel metal oxide semiconductor) tubes, wherein a grid electrode of the sampling PMOS tube MPS and common sources of the two PMOS tubes MPP and MPS are both connected with an input VIN, a common drain electrode of the power supply PMOS tube MPP and an NMOS tube MN2 is an output VOUT, a common drain electrode of the sampling PMOS tube MPS and an NMOS tube MN1 is connected with common grid electrodes of the NMOS tubes MN1 and MN2, and the common sources of; and the size ratio of the sampling PMOS to the power supply PMOS is 1: k1, the size ratio of the NMOS tubes MN1 and MN2 is 1: k2, K2 is greater than K1.
Furthermore, one input end of the error amplifier EA is connected to the reference voltage VREF, and the other input end is connected to the load feedback voltage VFB.
Further, in the size ratio, K2 is N times or more of K1, and N is a natural number greater than 2.
The improved design of the self-adaptive compensation circuit has the prominent substantive characteristics and remarkable progressiveness: the circuit is simple in structure and practical, the generated leakage current is tracked in a self-adaptive mode through the sampling PMOS tube, the leakage current is completely removed through the connected NMOS tubes, the output stability of the LDO under the temperature transformation environment can be guaranteed, the circuit does not have the generation of static current at normal temperature, and the optimization of design parameters is facilitated.
Drawings
Fig. 1 is a schematic diagram of a circuit structure for LDO adaptive leakage compensation according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.
The designer of the invention aims at the problems that the POWER MOS generates electric leakage at high temperature and greatly influences the output of the LDO when the current of the LDO exceeds the load current, integrates the experience of the industry for many years, and innovatively provides an electric leakage compensation circuit which aims at reducing the electric leakage so as to ensure the normal output of the LDO.
To more specifically understand, the schematic diagram of the circuit structure for LDO adaptive leakage compensation according to the present invention shown in fig. 1 can be seen. The grid of a power supply PMOS pipe MPP of the LDO is connected with the output of an error amplifier EA, the positive input end of the amplifier EA is connected with a reference voltage VREF, and the negative input end of the amplifier EA is connected with a load feedback voltage VFB. As a specific feature of the current optimization and improvement, the leakage compensation circuit is connected between the source and drain output VOUT of the power supply PMOS transistor MPP, and is formed by connecting a sampling PMOS transistor MPS and a pair of NMOS transistors MN1 and MN2, wherein the gate of the sampling PMOS transistor MPS and the common source of the two PMOS transistors MPP and MPS are both connected to the input VIN, the common drain of the power supply PMOS transistor MPP and NMOS transistor MN2 is the output VOUT, the common drain of the sampling PMOS transistor MPS and NMOS transistor MN1 is connected to the common gate of the NMOS transistors MN1 and MN2, and the common source of the two NMOS transistors is grounded. Therefore, the sampling PMOS tube can well track the leakage current generated by the power supply PMOS, and the size ratio of the sampling PMOS to the power supply PMOS is set to be 1: k1, namely when the leakage current is not generated, there is no sampling current, when the leakage current with any trend change is generated, the sampling PMOS tube will track the sampling current of the leakage current with 1/K1, and on the other hand, the size ratio of a pair of NMOS tubes MN1 and MN2 is 1: k2, the aforementioned resulting sampled current is amplified by a factor of K2 through the pair of NMOS transistors. In general, K2 is greater in magnitude than K1, and in a preferred size ratio, K2 may be N times or more as great as K1, with N being a natural number greater than 2, or any natural number more than twice as great as K1. The purpose of the power supply circuit is to ensure that when high-temperature leakage current is generated, the NMOS transistor MN2 can pull down current from the power supply PMOS transistor MPP to be larger than the leakage current generated by the MPP, so that the output VOUT can still keep normal output even under the zero-load condition.
In summary, with reference to the detailed description of the illustrated embodiments, the improved circuit design of the present invention has the following substantial features and significant improvements: the circuit is simple in structure and practical, the generated leakage current is tracked in a self-adaptive mode through the sampling PMOS tube, the leakage current is completely removed through the connected NMOS tubes, the output stability of the LDO under the temperature transformation environment can be guaranteed, and the compensation circuit does not generate static current under the normal temperature, so that the optimization design parameters are facilitated. Meanwhile, the circuit structure is simple, the occupied area of the newly added device is small, and the practicability is obviously improved.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and modifications and equivalents within the scope of the claims may be made by those skilled in the art and are included in the scope of the present invention.
Claims (3)
1. The utility model provides a circuit that is used for LDO adaptive leakage compensation, wherein the grid of the power supply PMOS pipe MPP of LDO meets with the output of error amplifier EA, its characterized in that: the circuit is connected between a source electrode and a drain electrode of a power supply PMOS (P-channel metal oxide semiconductor) tube MPP, and the circuit is formed by connecting a sampling PMOS tube MPS and a pair of NMOS (N-channel metal oxide semiconductor) tubes, wherein a grid electrode of the sampling PMOS tube MPS and common sources of the two PMOS tubes MPP and MPS are both connected with an input VIN, a common drain electrode of the power supply PMOS tube MPP and an NMOS tube MN2 is an output VOUT, a common drain electrode of the sampling PMOS tube MPS and an NMOS tube MN1 is connected with common grid electrodes of the NMOS tubes MN1 and MN2, and the common sources of; and the size ratio of the sampling PMOS to the power supply PMOS is 1: k1, the size ratio of the NMOS tubes MN1 and MN2 is 1: k2, K2 is greater than K1.
2. The circuit of claim 1, wherein the LDO adaptive leakage compensation circuit comprises: one input end of the error amplifier EA is connected with a reference voltage VREF, and the other input end of the error amplifier EA is connected with a load feedback voltage VFB.
3. The circuit of claim 1, wherein the LDO adaptive leakage compensation circuit comprises: in the size ratio, K2 is more than N times of K1, and N is a natural number more than 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910961954.1A CN110568895A (en) | 2019-10-11 | 2019-10-11 | Circuit for LDO adaptive leakage compensation |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910961954.1A CN110568895A (en) | 2019-10-11 | 2019-10-11 | Circuit for LDO adaptive leakage compensation |
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| CN110568895A true CN110568895A (en) | 2019-12-13 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111930167A (en) * | 2020-07-07 | 2020-11-13 | 芯创智（北京）微电子有限公司 | Output stage bleeder circuit applied to ultralow quiescent current LDO |
| CN113672024A (en) * | 2021-07-21 | 2021-11-19 | 北京时代民芯科技有限公司 | Leakage current compensation circuit and method applied to low-power LDO (low dropout regulator) |
| CN113965060A (en) * | 2021-10-25 | 2022-01-21 | 中国电子科技集团公司第二十四研究所 | Leakage current eliminating circuit and method applied to LDO chip |
| CN114510106A (en) * | 2022-02-22 | 2022-05-17 | 电子科技大学 | Ultralow static power consumption leakage compensation circuit applied to high-temperature LDO (low dropout regulator) |
| US12032396B2 (en) | 2021-09-22 | 2024-07-09 | Winbond Electronics Corp. | Voltage generating circuit and semiconductor device for suppressing leakage current |
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| CN1499328A (en) * | 2002-10-31 | 2004-05-26 | ���µ�����ҵ��ʽ���� | Current leakage compensator and its compensating method |
| CN103543777A (en) * | 2012-07-13 | 2014-01-29 | 创杰科技股份有限公司 | Low dropout regulator and electronic device thereof |
| US20150097540A1 (en) * | 2013-10-04 | 2015-04-09 | Silicon Motion Inc. | Low-drop regulator apparatus and buffer stage circuit having higher voltage transition rate |
| CN110187733A (en) * | 2019-06-20 | 2019-08-30 | 江苏润石科技有限公司 | The low pressure difference linear voltage regulator of Earl benefit phenomenon can be eliminated |
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2019
- 2019-10-11 CN CN201910961954.1A patent/CN110568895A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499328A (en) * | 2002-10-31 | 2004-05-26 | ���µ�����ҵ��ʽ���� | Current leakage compensator and its compensating method |
| CN103543777A (en) * | 2012-07-13 | 2014-01-29 | 创杰科技股份有限公司 | Low dropout regulator and electronic device thereof |
| US20150097540A1 (en) * | 2013-10-04 | 2015-04-09 | Silicon Motion Inc. | Low-drop regulator apparatus and buffer stage circuit having higher voltage transition rate |
| CN110187733A (en) * | 2019-06-20 | 2019-08-30 | 江苏润石科技有限公司 | The low pressure difference linear voltage regulator of Earl benefit phenomenon can be eliminated |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111930167A (en) * | 2020-07-07 | 2020-11-13 | 芯创智（北京）微电子有限公司 | Output stage bleeder circuit applied to ultralow quiescent current LDO |
| CN113672024A (en) * | 2021-07-21 | 2021-11-19 | 北京时代民芯科技有限公司 | Leakage current compensation circuit and method applied to low-power LDO (low dropout regulator) |
| US12032396B2 (en) | 2021-09-22 | 2024-07-09 | Winbond Electronics Corp. | Voltage generating circuit and semiconductor device for suppressing leakage current |
| CN113965060A (en) * | 2021-10-25 | 2022-01-21 | 中国电子科技集团公司第二十四研究所 | Leakage current eliminating circuit and method applied to LDO chip |
| CN113965060B (en) * | 2021-10-25 | 2023-08-25 | 中国电子科技集团公司第二十四研究所 | Leakage current eliminating circuit and method applied to LDO chip |
| CN114510106A (en) * | 2022-02-22 | 2022-05-17 | 电子科技大学 | Ultralow static power consumption leakage compensation circuit applied to high-temperature LDO (low dropout regulator) |
| CN114510106B (en) * | 2022-02-22 | 2022-11-04 | 电子科技大学 | Ultralow static power consumption leakage compensation circuit applied to high-temperature LDO (low dropout regulator) |
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Application publication date: 20191213 |
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