CN113965060B - Leakage current eliminating circuit and method applied to LDO chip - Google Patents

Leakage current eliminating circuit and method applied to LDO chip Download PDF

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Publication number
CN113965060B
CN113965060B CN202111239466.3A CN202111239466A CN113965060B CN 113965060 B CN113965060 B CN 113965060B CN 202111239466 A CN202111239466 A CN 202111239466A CN 113965060 B CN113965060 B CN 113965060B
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tube
leakage current
current
electrode
circuit
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CN113965060A (en
Inventor
王菡
罗凯
陈波
杨丰
李鹏
苟超
梁盛铭
廖鹏飞
刘昱含
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CETC 24 Research Institute
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CETC 24 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a leakage current eliminating circuit and a leakage current eliminating method applied to an LDO chip. The cancellation circuit comprises a leakage current sampling circuit, a current output circuit and a current amplifying circuit which are connected with each other; the leakage current sampling circuit is connected with the output end of the LDO and samples the leakage current of a power tube of the LDO; the current output circuit is connected with the base electrode of the buffer circuit in the LDO, detects the working state of the power tube according to the potential of the base electrode of the buffer circuit, and outputs the sampled leakage current when the power tube enters the cut-off region; the current amplifying circuit is connected with the output end of the LDO, amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube. The invention can accurately sample and offset the leakage current of the power tube, and avoid the deviation of the LDO output voltage from a typical value during no-load.

Description

Leakage current eliminating circuit and method applied to LDO chip
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a leakage current eliminating circuit and a leakage current eliminating method applied to a linear voltage regulator (Linear voltage regulators, LDO) chip.
Background
The linear voltage stabilizer can provide stable and pure power supply voltage for load devices, and the main application direction of the linear voltage stabilizer is to supply power for high-performance electronic devices. For application fields such as portable electronic equipment, a battery power supply system is generally adopted, and the power consumption of a linear voltage stabilizer can directly influence the overall power consumption of the system and influence the service time and standby time of the equipment. Therefore, reducing the power consumption of the linear voltage regulator is of great importance to portable electronic devices.
Fig. 1 is a schematic diagram of a conventional LDO circuit structure with low power consumption, in which an embedded design is used for internal bandgap reference and error op-amp to reduce the bias current of the control module. In order to reduce the bias current of the feedback resistor network, the feedback resistors RF1 and RF2 are designed by adopting high-resistance resistors, the bias current is usually in nA level, and the static power consumption of the LDO can be greatly reduced.
To reduce overall system power consumption, the internal functional modules of the portable device often operate in a standby or off state. The disadvantage of the low power LDO is that the power transistor MP is turned off due to the minimum bias current of the feedback resistor when the LDO is in an idle state. The MOS tube in the cut-off state has cut-off leakage current, and the leakage current can flow into feedback resistors RF1 and RF2 with high resistance values, so that the output voltage VOUT deviates from a typical value obviously, and the accuracy of the output voltage of the LDO is reduced.
Disclosure of Invention
In order to overcome the defect that the leakage current of the power tube causes the deviation of the output voltage of the LDO during no-load, the invention provides a novel leakage current eliminating circuit and a corresponding eliminating method thereof, which can accurately eliminate the leakage current of the power tube under no-load and have the characteristics of simple structure and low power consumption.
In order to achieve the above purpose, the present invention provides the following technical solutions:
in a first aspect of the present invention, the present invention provides a leakage current cancellation circuit applied to an LDO chip, the cancellation circuit including a leakage current sampling circuit, a current output circuit, and a current amplifying circuit connected to each other; the leakage current sampling circuit is connected with the output end of the LDO and samples the leakage current of a power tube of the LDO; the current output circuit is connected with the base electrode of the LDO internal buffer circuit, detects the working state of the power tube according to the potential of the base electrode of the power tube buffer circuit, and outputs the sampled leakage current when the power tube enters the cut-off region; the current amplifying circuit is connected with the output end of the LDO, amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube.
Further, the leakage current sampling circuit comprises a PMOS tube MS, an NPN tube Q11, an NPN tube Q12, an NPN tube Q13 and a PNP tube Q14; the grid electrode and the source electrode of the MS tube are connected with a power supply VIN, and the drain electrode of the MS tube is connected with the emitter electrode of the Q14 tube; the collector of the Q11 tube is connected with the power supply VIN, the base is connected with the LDO output VOUT, and the emitter is connected with the base of the Q14 tube and the collector of the Q12 tube; the base electrode and the collector electrode of the Q13 tube are connected with the collector electrode of the Q14 tube and the base electrode of the Q12 tube, the emitter electrode of the Q12 tube is connected with GND, and the emitter electrode of the Q12 tube is connected with GND.
Further, the leakage current sampling circuit may further include a PMOS tube MS, a PMOS tube M23, a PMOS tube M24, an NPN tube Q21, and an NPN tube Q22; the grid electrode and the source electrode of the MS tube are in short circuit and connected with a power supply VIN, and the drain electrode of the MS tube is connected with the source electrode of the M24 tube; the source electrode of the M23 tube is connected with the output VOUT, and the grid electrode and the drain electrode of the M24 tube are connected with the collector electrode of the Q21 tube; the source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube; the base electrode of the Q21 pipe is connected with the base electrode of the Q22 pipe, and the emitters of the Q21 pipe and the Q22 pipe are connected with GND.
Further, the current output circuit comprises an NPN tube Q16, an NPN tube Q17, an NPN tube Q18, a PNP tube Q15, a PNP tube Q19 and a current source IB2; the emitter of the Q15 tube is connected with the power supply VIN, the base and the collector are connected with the base of the Q16 tube and one end of the current source IB2, the collector of the Q16 tube is connected with the power supply VIN, the emitter is connected with the collector of the Q18 tube and the emitter of the Q17 tube, the base of the Q17 tube is connected with a certain base potential VB in the LDO, the base of the Q18 tube is connected with the base of the Q13 tube, the emitter is connected with GND, the emitter of the Q19 tube is connected with the power supply VIN, and the base and the collector of the Q17 tube are connected with the base of the Q20 tube.
Further, the current amplifying circuit includes a PNP transistor Q20, an NMOS transistor M1, and an NMOS transistor M2; the emitter of the Q20 tube is connected with the power supply VIN, the collector is connected with the grid electrode of the M1 tube, the drain electrode of the M2 tube and the grid electrode of the M1 tube, the source electrode of the M1 tube is connected with GND, the source electrode of the M2 tube is connected with GND, and the drain electrode of the M2 tube is connected with the LDO output VOUT.
Further, the current output circuit may further include an NMOS transistor M25, an NMOS transistor M26, an NPN transistor Q24, a PNP transistor Q23, and a PNP transistor Q25; the drain electrode of the M25 tube is connected with a power supply VIN, the grid electrode of the M25 tube is connected with the base electrode and the collector electrode of the Q23 tube, and the source electrode of the M25 tube is connected with the collector electrode of the Q24 tube and the source electrode of the M26 tube; the grid electrode of the M26 is connected with the buffer stage base electrode potential VB in the LDO, and the drain electrode of the M26 is connected with the base electrode and the collector electrode of the Q25 pipe; the emitters of the Q23 pipe and the Q25 pipe are connected with a power supply VIN, and the emitter of the Q24 pipe is connected with GND.
In a second aspect of the present invention, the present invention further provides a leakage current cancellation method applied to an LDO chip, the method comprising:
the leakage current sampling circuit is connected with the output ends of the power supply VIN and the LDO and samples the leakage current of the power tube MP;
the current output circuit mirrors the sampled leakage current, detects the working state of the power tube MP according to the base potential of the LDO buffer stage, and outputs the sampled leakage current when the power tube MP enters the interception area;
the current amplifying circuit amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube MP.
Further, the leakage current sampling circuit is connected with the power supply VIN and the output end of the LDO, the leakage current of the sampled power tube MP comprises that the gate electrode of an MS tube of the leakage current sampling circuit is connected with the power supply VIN, the leakage current of the power tube is sampled, the base electrode of an NPN tube Q11 of the leakage current sampling circuit is connected with the output voltage VOUT, the current of the MS tube is mirrored through an NPN tube Q13 and an NPN tube Q12 of the leakage current sampling circuit to serve as the bias current of the Q11 tube, and the emitter potential of a PNP tube Q14 of the leakage current sampling circuit is clamped as VOUT, wherein the number ratio of the power tube MP to the sampling tube MS is m 1.
Further, the leakage current sampling circuit is connected with the output ends of the power supply VIN and the LDO, and the leakage current sampled by the power tube MP further comprises an M23 tube source electrode in the leakage current sampling circuit connected with the output VOUT, and a grid electrode and a drain electrode connected with the grid electrode of the M24 tube and the collector electrode of the Q21 tube; the source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube. The grid source potential of the M23 tube is equal to that of the M24 tube, the source potential of the M24 tube is clamped to be VOUT, the influence of the channel modulation effect of the sampling tube MS on the sampling current is eliminated, and the sampling precision of the leakage current is ensured, wherein the number ratio of the power tube MP to the sampling tube MS is M1.
Further, the current output circuit mirrors the sampled leakage current, and detects the working state of the power tube MP according to the base potential of the power tube buffer circuit, when the power tube MP enters the cut-off region, the sampled leakage current is output to an NPN tube Q18 including the current output circuit, the NPN tube Q15 and the NPN tube Q16 are respectively connected with bias current signals of the current source, the NPN tube Q17 of the current output circuit receives the base potential signal of the LDO power tube buffer circuit, when the power tube of the LDO is cut off, the gate potential VP of the power tube is the current VIN, and under the bias current control of the current source, the Q18 tube current is output to the PNP tube Q19 tube through the Q17 and mirrored output to the current amplifying circuit.
Further, in the current output circuit, the drain electrode of the M25 tube is connected with the power supply VIN, the grid electrode is connected with the base electrode and the collector electrode of the Q23 tube, and the source electrode is connected with the collector electrode of the Q24 tube and the source electrode of the M26 tube. The gate of M26 is connected with the base electrode VB of the Q9 tube of the buffer stage in figure 1, and the drain is connected with the base electrode and the collector electrode of the Q25 tube. When the power tube MP is turned off, the grid potential VP of the power tube is the power source VIN, and the VB potential is VIN-V BE,Q9 . Since the current source IB1 now enters the linear region, the bias current is small, V BE,Q9 Less than V BE,Q23 While the gate potential of the M26 tube is higher than that of the M25 tube, the current of the Q24 tube is output to the Q25 tube through the M26 tube and mirrored to the Q26 tube.
Further, the current amplifying circuit amplifies the sampled leakage current and then injects the amplified leakage current into the output end, and counteracting the leakage current of the power tube MP includes amplifying the current of the PNP tube Q20 in the current amplifying circuit by M times, and outputting the amplified current signal to the NMOS tube M1 and the NMOS tube M2 forming the current mirror; the output end of the LDO is output from the drain electrode of the M2 pipe, wherein the number ratio of the NMOS pipe M1 to the NMOS pipe M2 is 1: m; m represents the number ratio of the power tube MP to the sampling tube MS in the leakage current sampling circuit.
In a third aspect of the present invention, the present invention further provides a linear voltage regulator, including a leakage current cancellation circuit applied to an LDO chip according to the first aspect of the present invention.
The invention has the beneficial effects that:
(1) The invention can accurately sample and offset the leakage current of the power tube, and avoid the deviation of the LDO output voltage from a typical value during no-load;
(2) The power tube leakage current sampling and counteracting circuit is simple in structure and low in design complexity, and can finish sampling and counteracting of the power tube leakage current only by three groups of circuits;
(3) The circuit has small bias current and can not obviously increase the power consumption of the system.
Drawings
FIG. 1 is a diagram of a conventional LDO with low power consumption;
FIG. 2 is a schematic diagram of a leakage current cancellation circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a leakage current cancellation circuit according to a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a leakage current cancellation circuit according to another preferred embodiment of the present invention;
fig. 5 is a flowchart of a leakage current eliminating method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 2 is a block diagram of a leakage current cancellation circuit applied to an LDO chip according to an embodiment of the present invention, where the cancellation circuit includes a leakage current sampling circuit, a current output circuit, and a current amplifying circuit connected to each other as shown in fig. 2; the leakage current sampling circuit is connected with the output end of the LDO and samples the leakage current of a power tube of the LDO; the current output circuit is connected with the base potential VB of the LDO, detects the working state of the power tube according to the sampled leakage current, and outputs the sampled leakage current when the power tube enters a cut-off region; the current amplifying circuit is connected with the output end of the LDO, amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube.
Fig. 3 is a schematic diagram of a leakage current cancellation circuit according to a preferred embodiment of the present invention, as shown in fig. 3:
the leakage current sampling circuit comprises a PMOS tube MS, an NPN tube Q11, an NPN tube Q12, an NPN tube Q13 and a PNP tube Q14. The grid electrode and the source electrode of the MS tube are connected with a power supply VIN, the drain electrode of the MS tube is connected with the emitter electrode of the Q14 tube, the collector electrode of the Q11 tube is connected with the power supply, the base electrode of the Q11 tube is connected with an LDO output VOUT, the emitter electrode of the MS tube is connected with the base electrode of the Q14 tube and the collector electrode of the Q12 tube, the base electrode and the collector electrode of the Q13 tube are connected with the collector electrode of the Q14 tube and the base electrode of the Q12 tube, the emitter electrode of the Q13 tube is connected with GND, and the emitter electrode of the Q12 tube is connected with GND.
The current output circuit comprises an NPN tube Q16, an NPN tube Q17, an NPN tube Q18, a PNP tube Q15, a PNP tube Q19 and a current source IB 2. The emitter of the Q15 tube is connected with a power supply VIN, the base and the collector of the Q16 tube are connected with one end of a current source IB2, the collector of the Q16 tube is connected with the power supply VIN, the emitter of the Q16 tube is connected with the collector of the Q18 tube and the emitter of the Q17 tube, the base of the Q17 tube is connected with the base of the Q13 tube in the buffer stage Q9 tube in the figure 1, the base of the Q18 tube is connected with the base of the Q13 tube, the emitter of the Q19 tube is connected with the power supply VIN, and the base and the collector of the Q17 tube are connected with the base of the Q20 tube.
The current amplifying circuit comprises a PNP tube Q20, an NMOS tube M1 and an NMOS tube M2. The emitter of the Q20 tube is connected with the power supply VIN, the collector is connected with the grid electrode of the M1 tube, the drain electrode of the M2 tube and the grid electrode of the M1 tube, the source electrode of the M1 tube is connected with GND, the source electrode of the M2 tube is connected with GND, and the drain electrode of the M2 tube is connected with the LDO output VOUT.
Fig. 4 is a schematic diagram of a leakage current cancellation circuit according to an embodiment of the present invention, as shown in fig. 4:
the leakage current sampling circuit comprises a PMOS tube MS, a PMOS tube M23, a PMOS tube M24, an NPN tube Q21 and an NPN tube Q22; the grid electrode and the source electrode of the MS tube are in short circuit and connected with a power supply VIN, and the drain electrode of the MS tube is connected with the source electrode of the M24 tube; the source electrode of the M23 tube is connected with the output VOUT, and the grid electrode and the drain electrode of the M24 tube are connected with the collector electrode of the Q21 tube; the source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube; the base electrode of the Q21 pipe is connected with the base electrode of the Q22 pipe, and the emitters of the Q21 pipe and the Q22 pipe are connected with GND.
The current output circuit further comprises an NMOS tube M25, an NMOS tube M26, an NPN tube Q24, a PNP tube Q23 and a PNP tube Q25; the drain electrode of the M25 tube is connected with a power supply VIN, the grid electrode of the M25 tube is connected with the base electrode and the collector electrode of the Q23 tube, and the source electrode of the M25 tube is connected with the collector electrode of the Q24 tube and the source electrode of the M26 tube; the grid electrode of the M26 is connected with the buffer stage base electrode potential VB in the LDO, and the drain electrode of the M26 is connected with the base electrode and the collector electrode of the Q25 pipe; the emitters of the Q23 pipe and the Q25 pipe are connected with a power supply VIN, and the emitter of the Q24 pipe is connected with GND.
The current amplifying circuit comprises a PNP tube Q26, an NMOS tube M21 and an NMOS tube M22. The emitter of the Q26 tube is connected with the power supply VIN, the collector is connected with the grid electrode of the M21 tube, the drain electrode of the M22 tube, the source electrode of the M21 tube is connected with GND, the source electrode of the M22 tube is connected with GND, and the drain electrode of the M22 tube is connected with the LDO output VOUT.
It is understood that the current amplifying circuit in this embodiment may not be adjusted, and the leakage current sampling circuit and the current output circuit may be adjusted correspondingly according to actual situations.
Fig. 5 is a flowchart of a leakage current eliminating method applied to an LDO chip according to an embodiment of the present invention, as shown in fig. 5, the method includes:
101. the leakage current sampling circuit is connected with the output ends of the power supply VIN and the LDO and samples the leakage current of the power tube MP;
in a preferred embodiment of the invention, a gate electrode of an MS tube of the leakage current sampling circuit is connected with a power supply VIN to sample leakage current of a power tube, a base electrode of an NPN tube Q11 of the leakage current sampling circuit is connected with an output voltage VOUT, the current of the MS tube is mirrored through an NPN tube Q13 and an NPN tube Q12 of the leakage current sampling circuit to serve as bias current of a Q11 tube, and an emitter potential of a PNP tube Q14 of the leakage current sampling circuit is clamped to be VOUT.
In other embodiments of the present invention, the leakage current sampling circuit is connected to the output terminals of the power supply VIN and the LDO, and the sampling of the leakage current of the power transistor MP further includes that the source electrode of the M23 transistor in the leakage current sampling circuit is connected to the output VOUT, and the gate electrode and the drain electrode are connected to the gate electrode of the M24 transistor and the collector electrode of the Q21 transistor; the source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube. The grid source potential of the M23 tube is equal to that of the M24 tube, the source potential of the M24 tube is clamped to be VOUT, the influence of the channel modulation effect of the sampling tube MS on the sampling current is eliminated, and the sampling precision of the leakage current is ensured, wherein the number ratio of the power tube MP to the sampling tube MS is M1.
102. The current output circuit mirrors the sampled leakage current, detects the working state of the power tube MP according to the base potential of the LDO buffer stage, and outputs the sampled leakage current when the power tube MP enters the interception area;
in the preferred embodiment of the invention, an NPN tube Q18 of the current output circuit mirrors leakage current sampled by the leakage current sampling circuit, a PNP tube Q15 and an NPN tube Q16 are respectively connected with bias current signals of a current source, an NPN tube Q17 of the current output circuit receives base potential signals of an LDO, when a power tube of the LDO is cut off, grid potential VP of the power tube is current VIN, and under the control of the bias current of the current source, the current of the Q18 tube is output to a PNP tube Q19 tube through the Q17 and is mirrored and output to the current amplifying circuit.
In other embodiments, the drain of the M25 tube in the current output circuit is connected to the power source VIN, the gate is connected to the base and collector of the Q23 tube, and the source is connected to the collector of the Q24 tube and the source of the M26 tube. The gate of M26 is connected with the base electrode VB of the Q9 tube of the buffer stage in figure 1, and the drain is connected with the base electrode and the collector electrode of the Q25 tube. When the power tube MP is turned off, the grid potential VP of the power tube is the power source VIN, and the VB potential is VIN-V BE,Q9 . Since the current source IB1 now enters the linear region, the bias current is small, V BE,Q9 Less than V BE,Q23 While the gate potential of the M26 tube is higher than that of the M25 tube, the current of the Q24 tube is output to the Q25 tube through the M26 tube and mirrored to the Q26 tube.
103. The current amplifying circuit amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube MP.
In the preferred embodiment of the invention, the current of the PNP tube Q20 in the current amplifying circuit is amplified by M times, and the amplified current signal is output to the NMOS tube M1 and the NMOS tube M2 which form a current mirror; the output from the drain of the M2 pipe is output to the output end of the LDO.
In order to correspond to another embodiment of the present invention, the current of the PNP transistor Q26 in the current amplifying circuit is amplified by M times, and the amplified current signal is output to the NMOS transistor M21 and the NMOS transistor M22 that constitute the current mirror; the output from the drain of the M22 pipe is output to the output end of the LDO.
The working principle of the invention is as follows:
when no load exists, the power tube MP of the LDO enters a cut-off region, and the grid potential VP of the MP tube is the power supply VIN. The grid electrode of the MS tube is connected with a power supply VIN, the leakage current of the power tube is sampled, and the number ratio of the leakage current to the MP of the power tube is 1: m. The base electrode of the Q11 tube is connected with the output voltage VOUT, the current of the MS tube is used as the bias current of the Q11 tube through the mirror images of the Q13 tube and the Q12 tube, the emitter potential of the Q14 tube is clamped into VOUT, the influence of the MS channel modulation effect of the sampling tube on the sampling current is eliminated, and the sampling precision of the leakage current is ensured.
The Q18 tube mirrors the leakage current sampled by the MS tube. Q15 tube bias current is IB2, and Q16 tube base electrode potential is VIN-V BE,Q15 . The base electrode of the Q17 tube is connected with the base electrode VB of the buffer stage Q9 tube in figure 1, when the power tube MP is cut off, the grid potential VP of the power tube is the power supply VIN, and the VB potential is VIN-V BE,Q9 . Since the current source IB1 now enters the linear region, the bias current is small, V BE,Q9 Less than V BE,Q15 And the base potential of the Q17 pipe is higher than that of the Q16 pipe, so the current of the Q18 pipe is output to the Q19 pipe through the Q17 pipe and mirrored to the Q20 pipe.
In the embodiment of the invention, the ratio of the current mirror M1 to the current mirror M2 is designed to be 1: m, the current of the Q20 tube is amplified by m times and then output to the output end VOUT of the linear voltage stabilizer, and m is the number ratio of the power tube MP to the sampling tube MS, so that the leakage current of the power tube MP can be accurately counteracted, and the deviation of the LDO output voltage during no-load is avoided.
Similarly, in the leakage current sampling circuit, the source electrode of the M23 tube is connected with the output VOUT, and the grid electrode and the drain electrode of the M24 tube are connected with the collector electrode of the Q21 tube. The source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube. The gate source potentials of the M23 tube and the M24 tube are equal, the source potential of the M24 tube is clamped into VOUT, the influence of the sampling tube MS channel modulation effect on the sampling current is eliminated, and the sampling precision of the leakage current is ensured. In the current output circuit, the drain electrode of the M25 tube is connected with a power supply VIN, the grid electrode is connected with the base electrode and the collector electrode of the Q23 tube, and the source electrode is connected with the collector electrode of the Q24 tube and the source electrode of the M26 tube. M26 grid is connected with the base of the buffer stage Q9 tube in FIG. 1And a pole VB, and a drain electrode connected with the base electrode and the collector electrode of the Q25 tube. When the power tube MP is turned off, the grid potential VP of the power tube is the power source VIN, and the VB potential is VIN-V BE,Q9 . Since the current source IB1 now enters the linear region, the bias current is small, V BE,Q9 Less than V BE,Q23 While the gate potential of the M26 tube is higher than that of the M25 tube, the current of the Q24 tube is output to the Q25 tube through the M26 tube and mirrored to the Q26 tube.
In an embodiment of the present invention, the present invention further provides a linear voltage regulator, including a leakage current cancellation circuit applied to an LDO chip according to the first aspect of the present invention.
The leakage current eliminating circuit applied to the LDO chip, the leakage current eliminating method applied to the LDO chip and the corresponding linear voltage stabilizer provided by the embodiment of the invention belong to the same conception of the invention, the corresponding features of the circuit can be cited with each other, the invention is not described in detail, and meanwhile, the technical effects of the circuit are corresponding, and the invention is not described in detail.
In the description of the present invention, it should be understood that the terms "coaxial," "bottom," "one end," "top," "middle," "another end," "upper," "one side," "top," "inner," "outer," "front," "center," "two ends," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. The leakage current eliminating circuit applied to the LDO chip is characterized by comprising a leakage current sampling circuit, a current output circuit and a current amplifying circuit which are connected with each other; the leakage current sampling circuit is connected with the output end of the LDO and samples the leakage current of a power tube of the LDO; the current output circuit is connected with the base electrode of the buffer circuit in the LDO, detects the working state of the power tube according to the potential of the base electrode of the buffer circuit, and outputs the sampled leakage current when the power tube enters the cut-off region; the current amplifying circuit is connected with the output end of the LDO, amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube.
2. The leakage current cancellation circuit applied to the LDO chip according to claim 1, wherein the leakage current sampling circuit comprises a PMOS transistor MS, an NPN transistor Q11, an NPN transistor Q12, an NPN transistor Q13, and a PNP transistor Q14; the grid electrode and the source electrode of the MS tube are in short circuit and connected with a power supply VIN, and the drain electrode of the MS tube is connected with the emitter electrode of the Q14 tube; the collector of the Q11 tube is connected with the power supply VIN, the base is connected with the LDO output VOUT, and the emitter is connected with the base of the Q14 tube and the collector of the Q12 tube; the base electrode and the collector electrode of the Q13 tube are connected with the collector electrode of the Q14 tube and the base electrode of the Q12 tube, the emitter electrode of the Q12 tube is connected with GND, and the emitter electrode of the Q12 tube is connected with GND.
3. The leakage current cancellation circuit applied to the LDO chip as claimed in claim 1, wherein the leakage current sampling circuit comprises a PMOS tube MS, a PMOS tube M23, a PMOS tube M24, an NPN tube Q21 and an NPN tube Q22; the grid electrode and the source electrode of the MS tube are in short circuit and connected with a power supply VIN, and the drain electrode of the MS tube is connected with the source electrode of the M24 tube; the source electrode of the M23 tube is connected with the output VOUT, and the grid electrode and the drain electrode of the M24 tube are connected with the collector electrode of the Q21 tube; the source electrode of the M24 tube is connected with the drain electrode of the sampling tube MS, and the drain electrode is connected with the collector electrode and the base electrode of the Q22 tube; the base electrode of the Q21 pipe is connected with the base electrode of the Q22 pipe, and the emitter electrode of the Q21 pipe and the emitter electrode of the Q22 pipe are connected with GND.
4. The leakage current cancellation circuit applied to the LDO chip according to claim 1, wherein the current output circuit comprises an NPN transistor Q16, an NPN transistor Q17, an NPN transistor Q18, a PNP transistor Q15, a PNP transistor Q19, and a current source IB2; the emitter of the Q15 tube is connected with a power supply VIN, the base and the collector of the Q16 tube are connected with one end of a base and a current source IB2, the collector of the Q16 tube is connected with the power supply VIN, the emitter of the Q16 tube is connected with the collector of the Q18 tube and the emitter of the Q17 tube, the base of the Q17 tube is connected with a buffer circuit base VB in an LDO, the base of the Q18 tube is connected with the leakage current sampling circuit, the other ends of the emitter and the current source IB2 are connected with GND, the emitter of the Q19 tube is connected with the power supply VIN, and the base and the collector of the Q17 tube are connected with the current amplifying circuit.
5. The leakage current cancellation circuit applied to the LDO chip according to claim 1, wherein the current output circuit comprises an NMOS transistor M25, an NMOS transistor M26, an NPN transistor Q24, a PNP transistor Q23, a PNP transistor Q25, and a current source IB3; the drain electrode of the M25 tube is connected with a power supply VIN, the grid electrode of the M25 tube is connected with the base electrode and the collector electrode of the Q23 tube and one end of a current source IB3, and the source electrode of the M25 tube is connected with the collector electrode of the Q24 tube and the source electrode of the M26 tube; the grid electrode of the M26 is connected with the base electrode VB of the buffer circuit in the LDO, and the drain electrode of the M26 is connected with the base electrode and the collector electrode of the Q25 pipe; the emitter of the Q23 pipe and the emitter of the Q25 pipe are connected with a power supply VIN, the emitter of the Q24 pipe and the other end of the current source IB3 are connected with GND, and the base electrode of the Q24 pipe is connected with the leakage current sampling circuit.
6. The leakage current cancellation circuit applied to the LDO chip according to claim 1, wherein the current amplification circuit comprises a PNP transistor Q20, an NMOS transistor M1, and an NMOS transistor M2; the emitter of the Q20 tube is connected with the power supply VIN, the base is connected with the current output circuit, the collector is connected with the grid electrode of the M1 tube, the drain electrode of the M2 tube and the grid electrode of the M1 tube, the source electrode of the M1 tube is connected with GND, the source electrode of the M2 tube is connected with GND, and the drain electrode of the M2 tube is connected with the LDO output VOUT.
7. A leakage current cancellation method applied to an LDO chip, the method comprising:
the leakage current sampling circuit is connected with the output ends of the power supply VIN and the LDO and samples the leakage current of the power tube MP;
the current output circuit mirrors the sampled leakage current, detects the working state of the power tube MP according to the base potential of the LDO buffer stage, and outputs the sampled leakage current when the power tube MP enters a cut-off region;
the current amplifying circuit amplifies the sampled leakage current and then injects the amplified leakage current into the output end to offset the leakage current of the power tube MP.
8. The method for eliminating leakage current applied to an LDO chip according to claim 7, wherein the leakage current sampling circuit is connected to a power supply VIN and an output end of the LDO, the leakage current of the sampled power tube MP comprises that a gate electrode of an MS tube of the leakage current sampling circuit is connected to the power supply VIN, the leakage current of the power tube is sampled, a base electrode of an NPN tube Q11 of the leakage current sampling circuit is connected to an output voltage VOUT, the current of the MS tube is mirrored through an NPN tube Q13 and an NPN tube Q12 of the leakage current sampling circuit to serve as bias current of the Q11 tube, and an emitter potential of a PNP tube Q14 of the leakage current sampling circuit is clamped to be VOUT, wherein the number ratio of the power tube MP to the sampling tube MS is m 1.
9. The method for eliminating leakage current applied to LDO chip according to claim 7, wherein said current output circuit mirrors the sampled leakage current, and detects the working state of the power tube MP according to the base potential of the power tube buffer circuit, when said power tube MP enters the cut-off region, the sampled leakage current is outputted to the NPN tube Q18 including the current output circuit, the PNP tube Q15 and the NPN tube Q16 are respectively connected with the bias current signal of the current source, the base pole and the collector of the Q15 are short-circuited and then connected with the current source, the base pole of the Q16 is connected with the current source, the NPN tube Q17 of the current output circuit receives the base potential signal of the buffer circuit inside the LDO, when the power tube of the LDO is cut-off, the gate potential VP of the power tube is the current VIN, the current of the Q18 is outputted to the PNP tube Q19 through the Q17 under the control of the bias current of the current source, and is mirror-image outputted to the current amplifying circuit.
10. The method of eliminating leakage current applied to LDO chip as claimed in claim 7, wherein the current amplifying circuit amplifies the sampled leakage current and injects the amplified leakage current into the output terminal, and counteracting the leakage current of the power transistor MP comprises amplifying the current of the PNP transistor Q20 in the current amplifying circuit by M times and outputting the amplified current signal to the NMOS transistors M1 and M2 constituting the current mirror; the output end of the LDO is output from the drain electrode of the M2 pipe, wherein the number ratio of the NMOS pipe M1 to the NMOS pipe M2 is 1: m; m represents the number ratio of the power tube MP to the sampling tube MS in the leakage current sampling circuit.
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Citations (4)

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CN108062139A (en) * 2018-02-06 2018-05-22 上海毅栈半导体科技有限公司 A kind of LDO circuit of the LDO circuit of ultra low quiescent power consumption and the ultra low quiescent power consumption of driving heavy load
CN110568895A (en) * 2019-10-11 2019-12-13 思瑞浦微电子科技（苏州）股份有限公司 Circuit for LDO adaptive leakage compensation
CN111930167A (en) * 2020-07-07 2020-11-13 芯创智（北京）微电子有限公司 Output stage bleeder circuit applied to ultralow quiescent current LDO
CN112241192A (en) * 2019-07-17 2021-01-19 半导体元件工业有限责任公司 Output current limiter of linear voltage stabilizer

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US8836303B2 (en) * 2010-12-21 2014-09-16 St-Ericsson Sa Active leakage consuming module for LDO regulator
US9625924B2 (en) * 2015-09-22 2017-04-18 Qualcomm Incorporated Leakage current supply circuit for reducing low drop-out voltage regulator headroom

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108062139A (en) * 2018-02-06 2018-05-22 上海毅栈半导体科技有限公司 A kind of LDO circuit of the LDO circuit of ultra low quiescent power consumption and the ultra low quiescent power consumption of driving heavy load
CN112241192A (en) * 2019-07-17 2021-01-19 半导体元件工业有限责任公司 Output current limiter of linear voltage stabilizer
CN110568895A (en) * 2019-10-11 2019-12-13 思瑞浦微电子科技（苏州）股份有限公司 Circuit for LDO adaptive leakage compensation
CN111930167A (en) * 2020-07-07 2020-11-13 芯创智（北京）微电子有限公司 Output stage bleeder circuit applied to ultralow quiescent current LDO

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