CN117311433A - Soft-start low-dropout linear voltage stabilizing circuit - Google Patents
Soft-start low-dropout linear voltage stabilizing circuit Download PDFInfo
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- CN117311433A CN117311433A CN202311472440.2A CN202311472440A CN117311433A CN 117311433 A CN117311433 A CN 117311433A CN 202311472440 A CN202311472440 A CN 202311472440A CN 117311433 A CN117311433 A CN 117311433A
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- 230000000087 stabilizing effect Effects 0.000 title claims abstract description 30
- 238000005070 sampling Methods 0.000 claims abstract description 37
- 230000003321 amplification Effects 0.000 claims abstract description 34
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 34
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims description 23
- 230000008859 change Effects 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 description 7
- 239000003381 stabilizer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 3
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- 230000002159 abnormal effect Effects 0.000 description 1
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- 230000006641 stabilisation Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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Abstract
The application relates to a soft start's low dropout linear voltage regulator circuit, this circuit includes: the device comprises an adjusting tube, a driving circuit, a sampling circuit, an error amplification voltage conversion circuit and a soft start circuit, wherein the adjusting tube, the driving circuit, the sampling circuit and the error amplification voltage conversion circuit are connected between a voltage input end and a voltage output end; the soft start circuit comprises a generating circuit, an operational amplifier and a third enhanced NMOS tube; the generating circuit is arranged between the voltage input end and the grounding end; the positive and negative input ends of the operational amplifier are respectively connected with the input end of the sampling circuit and the generating circuit, the output end of the operational amplifier is connected with the grid electrode of the third enhanced NMOS tube, the source electrode of the third enhanced NMOS tube is connected with the error amplification voltage conversion circuit, and the drain electrode of the third enhanced NMOS tube is connected with the voltage input end. The low-voltage linear voltage stabilizing circuit solves the technical problems that in the related art, a reference source is adopted by the low-voltage linear voltage stabilizing circuit, the circuit output is easy to generate surge, and the circuit is easy to damage.
Description
Technical Field
The application relates to the technical field of low-voltage stabilization, in particular to a soft-start low-dropout linear voltage stabilizing circuit.
Background
A linear voltage regulator is a common device in a circuit for providing a stable voltage, and the conventional voltage regulator requires an input voltage at least 2 v-3 v higher than an output voltage, otherwise, the voltage regulator cannot work normally. However, in the related art, particularly, portable electronic devices, a voltage stabilizing device having a smaller voltage difference between an input voltage and an output voltage, which is a low-dropout linear voltage stabilizer LDO (Low DropOut Regulator), is required.
In the related art, in order to achieve a higher starting speed, a reference voltage of a circuit of a reference source is also directly hopped, and when the reference source is used as a reference source of a voltage stabilizing circuit, the output of the voltage stabilizer can easily generate higher surge, so that the circuit is damaged.
Aiming at the problems that a reference source is adopted in a low-voltage linear voltage stabilizing circuit in the related technology, the circuit output is easy to generate surge and the circuit is easy to be damaged, no effective solution is proposed at present.
Disclosure of Invention
The embodiment of the invention provides a soft-start low-dropout linear voltage stabilizing circuit, which at least solves the technical problems that the low-voltage linear voltage stabilizing circuit in the related art adopts a reference source mode, so that the circuit output is easy to generate surge and the circuit is easy to be damaged.
The embodiment of the invention provides a soft-start low-dropout linear voltage stabilizing circuit, which comprises: the device comprises an adjusting tube connected between a voltage input end and a voltage output end, an output voltage sampling circuit used for sampling the input end of the circuit, an error amplification voltage conversion circuit used for generating a reference voltage according to the sampled output voltage and converting the reference voltage into a corresponding current which is compared with the reference current, a double-driving circuit used for driving the adjusting tube according to the change of the error amplification voltage, and a soft start circuit used for realizing the soft start of the circuit; the soft start circuit comprises a generating circuit, an operational amplifier A and a third enhanced NMOS tube N3; the generation circuit is arranged between the voltage input end and the grounding end and is used for generating a slope signal; the positive and negative input ends of the operational amplifier A are respectively connected with the input end of the sampling circuit and the generating circuit and used for comparing the voltage of the input end of the sampling circuit and the voltage of the slope signal, the output end of the operational amplifier A is connected with the grid electrode of the third enhanced NMOS tube N3, the source electrode of the third enhanced NMOS tube N3 is connected with the error amplification voltage conversion circuit, and the drain electrode of the third enhanced NMOS tube is connected with the voltage input end.
As an alternative embodiment, the generating circuit includes: a current source I1 and a capacitor C1; the current source I1 is arranged on a circuit between the voltage input end and the operational amplifier A, one end of the capacitor C1 is connected with the current source I1 and the operational amplifier A, and the other end of the capacitor C1 is grounded.
As an alternative embodiment, one end of the capacitor C1 connected to the operational amplifier a is connected to the positive input end of the operational amplifier a; and the negative input end of the operational amplifier A is connected with the output end of the sampling circuit.
As an alternative embodiment, the output end of the operational amplifier a is grounded through a zener diode ZD 1; the negative electrode of the zener diode ZD1 is connected with the output end of the operational amplifier a, and the positive electrode of the zener diode ZD1 is grounded.
As an alternative embodiment, the error amplifying voltage conversion circuit includes: the first enhancement type NMOS tube N1 and the depletion type NMOS tube DN1; the grid electrode of the first enhanced NMOS tube N1 is connected with the output end of the sampling circuit, the source electrode of the first enhanced NMOS tube N1 is grounded, and the drain electrode of the first enhanced NMOS tube N1 is connected with the source electrode of the depletion NMOS tube DN1; the source electrode and the grid electrode of the depletion type NMOS tube DN1 are in short circuit, and the drain electrode of the depletion type NMOS tube DN1 is connected with the source electrode of the third enhancement type NMOS tube N3.
As an alternative embodiment, the drain electrode of the third enhancement NMOS transistor N3 is connected to the voltage input terminal, and the source electrode of the third enhancement NMOS transistor N3 is connected to the drain electrode of the depletion NMOS transistor DN1 of the error amplification voltage conversion circuit.
As an alternative embodiment, the driving circuit includes: the second enhanced NMOS tube N2 and the first enhanced PMOS tube P1; the grid electrode of the second enhanced NMOS tube N2 is connected with the drain electrode of the first enhanced NMOS tube N1 and the source electrode of the depletion NMOS tube DN1, the source electrode of the second enhanced NMOS tube N2 is grounded, and the drain electrode of the second enhanced NMOS tube N2 is connected with the drain electrode of the first enhanced PMOS tube P1; the source electrode of the first enhanced PMOS tube P1 is connected with the voltage input end, and the grid electrode of the first enhanced PMOS tube P1 is connected with the grid electrode of the adjusting tube.
As an optional embodiment, the adjusting tube is a second enhancement PMOS tube P2; the grid electrode of the second enhanced PMOS tube P2 is connected with the grid electrode of the first enhanced PMOS tube P1 of the driving circuit, the drain electrode of the second enhanced PMOS tube P2 is connected with the voltage output end, and the source electrode of the second enhanced PMOS tube P2 is connected with the voltage input end.
As an alternative embodiment, the sampling circuit includes: a first resistor R1 and a second resistor R2; the first resistor R1 and the second resistor R2 are connected in series between the voltage output end and the grounding end, one end of the first resistor R1 is connected with the voltage output end, and the other end of the first resistor R1 is connected with the second resistor and outputs the sampling output voltage; one end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is grounded.
The low dropout linear voltage regulator provided by the embodiment of the invention comprises an input end, an output end and a low dropout linear voltage regulator circuit arranged between the input end and the output end, wherein the low dropout linear voltage regulator circuit is any one of the low dropout linear voltage regulator circuits; the input end is connected with the voltage input end of the low dropout linear voltage stabilizing circuit, and the output end is connected with the voltage output end of the low dropout linear voltage stabilizing circuit.
According to the low-dropout linear voltage stabilizing circuit provided by the embodiment of the invention, the generation circuit generates the ramp signal with a certain rising speed, the operational amplifier is used for comparing the ramp signal with the sampled output voltage, and the gate voltage of the third enhanced NMOS tube N3 is controlled to slowly rise, so that the circuit is slowly electrified, the jump of the voltage of the circuit is avoided, the output of the circuit is caused to surge, and the safety and the reliability of the circuit are improved. And the reference voltage is generated by matching with the error amplification voltage conversion circuit to replace the traditional reference source, so that the problem that the circuit output is easy to generate surge and the circuit is easy to damage due to the adoption of the reference source mode of the low-voltage linear voltage stabilizing circuit in the related technology is solved.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the invention, from which other embodiments can be obtained for a person skilled in the art without inventive effort.
Fig. 1 is a schematic diagram of a soft-start low dropout linear voltage regulator circuit according to an embodiment of the present invention.
Reference numerals illustrate:
DN 1-depletion NMOS transistor; p1-a first enhancement PMOS tube; p2-a second enhanced PMOS tube; n1-a first enhanced NMOS tube; n2-a second enhanced NMOS tube; n3-a third enhanced NMOS tube; r1 is a first resistor; r2-a second resistor; c1-capacitance; i1-a current source; a-an operational amplifier; ZD 1-zener diode.
Detailed Description
Embodiments of the present embodiment will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present embodiments are illustrated in the accompanying drawings, it is to be understood that the present embodiments may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present embodiments. It should be understood that the drawings and the embodiments of the present embodiments are presented for purposes of illustration only and are not intended to limit the scope of the embodiments.
In the related art, reference sources of LDOs commonly include depletion NMOS, enhancement NMOS, and capacitors. The drain electrode of the depletion type NMOS tube is connected with a power supply VDD, the grid electrode of the depletion type NMOS tube is in short circuit with the source electrode, the grid electrode of the depletion type NMOS tube is in short circuit with the drain electrode, the grid electrode of the depletion type NMOS tube is in short circuit with the source electrode, the grid electrode of the depletion type NMOS tube is connected with the drain electrode of the enhancement type NMOS tube to form an output reference voltage Vref of the reference voltage generating circuit, the capacitor is connected in parallel with the source electrode and the drain electrode of the enhancement type NMOS tube, the reference voltage Vref is connected with the capacitor to GND, and the source end of the enhancement type NMOS tube is connected to GND. The drain current of the enhancement NMOS transistor is equal to the current of the depletion transistor reference current source, so the gate-to-source voltage (Vgs) of the enhancement NMOS transistor is equal to the output reference voltage Vref.
The starting speed of the depletion tube reference circuit is very high, and the threshold voltage of the depletion NMOS tube is negative, so that the gate source of the depletion NMOS tube is short-circuited GS The reference voltage Vref also jumps directly with VDD when the power supply VDD suddenly jumps from 0 to the operating voltage, and it is difficult to avoid the occurrence of a surge during the power supply power-up process. When the reference source is used as a reference source for the voltage stabilizer, the output of the voltage stabilizer is easy to generate higher surge, which can cause abnormal operation and even damage of a system adopting the output power supply of the voltage stabilizer.
Because the circuit of the reference source can directly jump for a faster starting speed, when the reference source is used as a reference source of the voltage stabilizing circuit, the output of the voltage stabilizer can easily generate higher surge, and the circuit is damaged.
According to the low-dropout linear voltage stabilizing circuit provided by the embodiment of the invention, the generation circuit generates the ramp signal with a certain rising speed, the operational amplifier is used for comparing the ramp signal with the sampled output voltage, and the gate voltage of the third enhanced NMOS tube N3 is controlled to slowly rise, so that the circuit is slowly electrified, the jump of the voltage of the circuit is avoided, the output of the circuit is caused to surge, and the safety and the reliability of the circuit are improved. And the reference voltage is generated by matching with the error amplification voltage conversion circuit to replace the traditional reference source, so that the problem that the circuit output is easy to generate surge and the circuit is easy to damage due to the adoption of the reference source mode of the low-voltage linear voltage stabilizing circuit in the related technology is solved.
Fig. 1 is a schematic diagram of a soft-start low dropout linear voltage regulator circuit according to an embodiment of the present invention, as shown in fig. 1, provided by the embodiment of the present invention, including: the circuit comprises an adjusting tube connected between a voltage input end and a voltage output end, an output voltage sampling circuit used for sampling the input end of the circuit, an error amplification voltage conversion circuit used for generating a reference voltage according to the sampled output voltage and converting the reference voltage into a corresponding current which is compared with the reference current, a driving circuit used for driving the adjusting tube according to the change of the error amplification voltage, and a soft start circuit used for realizing the soft start of the circuit.
The soft start circuit comprises a generating circuit, an operational amplifier A and a third enhanced NMOS tube N3; the generation circuit is arranged between the voltage input end and the grounding end and is used for generating a slope signal; the positive and negative input ends of the operational amplifier A are respectively connected with the input end of the sampling circuit and the generating circuit and used for comparing the voltage of the input end of the sampling circuit and the voltage of the slope signal, the output end of the operational amplifier A is connected with the grid electrode of the third enhanced NMOS tube N3, the source electrode of the third enhanced NMOS tube N3 is connected with the error amplification voltage conversion circuit, and the drain electrode of the third enhanced NMOS tube is connected with the voltage input end.
According to the low-dropout linear voltage stabilizing circuit provided by the embodiment of the invention, the generation circuit generates the ramp signal with a certain rising speed, the operational amplifier is used for comparing the ramp signal with the sampled output voltage, and the gate voltage of the third enhanced NMOS tube N3 is controlled to slowly rise, so that the circuit is slowly electrified, the jump of the voltage of the circuit is avoided, the output of the circuit is caused to surge, and the safety and the reliability of the circuit are improved.
The sampling circuit is connected with the voltage output end, and the output voltage of the low-dropout linear voltage stabilizing circuit is collected, so that the sampling is needed due to the fact that the output voltage changes in real time according to a load, and the subsequent output voltage is adjusted according to the sampled voltage.
The error amplification voltage conversion circuit is respectively connected with the soft start circuit and the sampling circuit, the sampling circuit is used for transmitting the output voltage to the error amplification voltage conversion circuit after sampling the output voltage, the reference voltage is generated and converted into the error amplification voltage after the corresponding current and the reference current are compared with each other, the reference voltage is the voltage value which is expected to be reached after the subsequent output voltage is sampled, and the corresponding current is the current corresponding to the reference voltage. The reference current is the current value that the corresponding current needs to reach.
The error amplification voltage conversion circuit can generate reference voltage and corresponding current thereof, output error amplification voltage after comparing the reference voltage with the reference current, and does not adopt a high-power consumption reference source any more so as to reduce power consumption and noise, and a proper driving current is selected through the driving circuit, so that the power supply rejection ratio and response speed are improved.
The error amplification voltage conversion circuit is connected with the driving circuit, the obtained error amplification voltage is sent to the driving circuit, and the driving circuit controls the conduction state of the adjusting tube connected between the voltage input end and the voltage output end according to the change of the error amplification voltage, so that the voltage of the voltage output end is adjusted, and the purpose of stabilizing the circuit is achieved. The driving circuit can select proper driving current, and improves the power supply rejection ratio and the response speed.
The soft start circuit obtains input voltage from a voltage input end, transmits the input voltage to an anode input end of the operational amplifier, samples and obtains sampling output voltage from a voltage output end, transmits the sampling output voltage to a cathode input end of the comparator, compares the input voltage and the output voltage through the operational amplifier, and acts on a grid electrode of the third enhanced NMOS tube N3 according to a comparison result, so that the third enhanced NMOS tube N3 is in soft conduction when the circuit is started, namely, when the voltage of the circuit jumps from 0 to normal voltage, the grid electrode of the third enhanced NMOS tube N3 can slowly increase the voltage.
Therefore, soft start of the low-dropout linear voltage stabilizing circuit is realized, the purpose of protecting a power supply or a complex voltage output end is further realized, and the safety and the reliability of the circuit are improved.
Specifically, the rising speed of the RAMP signal determines the time and speed of the soft start, and the faster the rising speed of the RAMP signal, the faster the voltage of the third enhancement NMOS transistor N3 rises, whereas the slower the rising speed of the RAMP signal, the slower the voltage of the third enhancement NMOS transistor N3 rises. The rising speed of the RAMP signal is determined by the generating circuit.
As an alternative embodiment, the generating circuit comprises: a current source I1 and a capacitor C1; the current source I1 is arranged on a circuit between the voltage input end and the operational amplifier A, one end of the capacitor C1 is connected with the current source I1 and the operational amplifier A, and the other end of the capacitor C1 is grounded.
The generating circuit comprises a current source I1 and a capacitor C1; the current source I1 is arranged on a circuit between the voltage input end and the operational amplifier A, one end of the capacitor C1 is connected with the current source I1 and the operational amplifier A, and the other end of the capacitor C1 is grounded; the grid electrode of the third enhanced NMOS tube N3 is connected with the output end of the operational amplifier A, the drain electrode of the third enhanced NMOS tube N3 is connected with the voltage input end, and the source electrode of the third enhanced NMOS tube N3 is connected with the error amplification voltage conversion circuit.
The grid electrode of the third enhanced NMOS tube N3 is connected with the output end of the operational amplifier A, and the drain electrode of the third enhanced NMOS tube N3 is connected with the voltage input end. Therefore, according to the comparison result of the operational amplifier A, the third enhancement NMOS transistor N3 acts on the grid electrode, so that the adjusting transistor is in soft conduction when the circuit is started.
The generating circuit is used for generating a voltage Ramp signal Ramp of the voltage input end according to the capacitor C1. The purpose of the current source I1 is to generate a Ramp voltage, that is, a voltage Ramp signal Ramp, by flowing a fixed current of the current source I1 into the capacitor C1. By using the current source and the capacitor C1 of the generating circuit, the voltage Ramp signal Ramp is obtained, so that the soft conduction of the adjusting tube during circuit starting and the soft starting of the low-dropout linear voltage stabilizing circuit are realized.
As an alternative embodiment, one end of the capacitor C1 connected with the operational amplifier a is connected to the positive input end of the operational amplifier a; the negative input end of the operational amplifier A is connected with the output end of the sampling circuit.
One end of the capacitor C1 connected with the operational amplifier a is connected to the positive input end of the operational amplifier a, that is, the positive input end of the operational amplifier a is input with the voltage Ramp signal Ramp, and the negative input end of the operational amplifier a is connected with the output end of the sampling circuit, that is, the negative input end of the operational amplifier a is input with the output voltage.
When the circuit is started, the voltage at the voltage input end jumps from 0 to the target voltage, the capacitor C1 is gradually boosted, and a Ramp signal Ramp is formed along with the increase of time. The grid electrode of the third enhanced NMOS tube N3 is slowly boosted, so that the control circuit is slowly electrified, and the aim of soft start is fulfilled.
As an alternative embodiment, the output end of the operational amplifier a is grounded through the zener diode ZD 1; the negative electrode of the zener diode ZD1 is connected with the output end of the operational amplifier a, and the positive electrode of the zener diode ZD1 is grounded.
The gate voltage of the third enhanced NMOS tube N3 is gradually increased along with soft start, and the final voltage upper limit is clamped at a fixed value by the voltage stabilizing diode ZD1, so that the third enhanced NMOS tube N3 forms the driving function of a Source Follower, the drain voltage of the depletion type NMOS tube DN1 of the error amplification voltage conversion circuit cannot fluctuate along with VIN voltage, and the power supply rejection ratio of the whole control circuit is improved.
As an alternative embodiment, the error amplifying voltage conversion circuit includes: the first enhancement type NMOS tube N1 and the depletion type NMOS tube DN1; the grid electrode of the first enhanced NMOS tube N1 is connected with the output end of the sampling circuit, the source electrode of the first enhanced NMOS tube N1 is grounded, and the drain electrode of the first enhanced NMOS tube N1 is connected with the source electrode of the depletion NMOS tube DN1; the source electrode and the grid electrode of the depletion type NMOS tube DN1 are in short circuit, and the drain electrode of the depletion type NMOS tube DN1 is connected with the source electrode of the third enhancement type NMOS tube N3.
The reference voltage is generated by connecting the gate and source of the depletion type NMOS transistor DN1, and the Vgs voltage of the first enhancement type NMOS transistor N1 is the reference voltage. Depletion type NMOS transistor DN1 is an NMOS transistor, and the source is not directly grounded, so DN1 requires the use of an isolated device.
The enhancement type first enhancement type NMOS tube N1 and the depletion type NMOS tube DN1 are connected in series to generate a reference voltage. The reference voltage generating circuit is based on the principle that the grid electrode and the source electrode of a depletion type NMOS tube DN1 are short-circuited and then act as a current source which is connected with the drain electrode of a first enhancement type NMOS tube N1, and the current of the grid electrode and the source electrode is consistentThe gate voltage of the first enhancement NMOS transistor N1 is the reference voltage, and the reference voltage can be obtainedV ref ：
Wherein V is N1 Heel V DN1 Represent threshold voltages of the enhancement mode first enhancement mode NMOS transistor N1 and the depletion mode NMOS transistor DN1, respectively, k N1 =μnc OX (W/L) N1 ，kDN1＝μnC OX (W/L) DN1 The threshold value of the depletion type NMOS is negative, and the threshold values of the depletion type NMOS and the enhancement type NMOS are both negative temperature coefficients, and the width-to-length ratio (W/L) of the enhancement type first enhancement type NMOS tube N1 is reasonably selected N1 Width ratio (W/L) of depletion type NMOS transistor DN1 DN1 The reference voltage Vref with zero temperature coefficient can be obtained. In the embodiment, the error amplification voltage conversion circuit has the functions of converting the reference voltage into corresponding current, comparing the current and amplifying the error, so that the layout area is reduced.
The magnitude of the corresponding current is determined by Vgs (reference voltage) of N1, and the reference current is the current magnitude of DN 1. Since DN1 is in series with N1, both are equal. The Vgs of N1 is regulated by combining all the modules to form a feedback loop so that the drain current of N1 is equal to the reference current represented by DN1, and the Vgs is called the reference voltage only when the drain current of N1 is equal to the reference current.
As an alternative embodiment, the drain of the third enhancement NMOS transistor N3 is connected to the voltage input terminal, and the source of the third enhancement NMOS transistor N3 is connected to the drain of the depletion NMOS transistor DN1 of the error amplification voltage conversion circuit.
The upper limit of the gate voltage of the third enhanced NMOS transistor N3 is clamped at a fixed value by the zener diode ZD1, so that the third enhanced NMOS transistor N3 forms a driving function of a Source Follower, and the drain voltage of the depletion NMOS transistor DN1 of the error amplification voltage conversion circuit cannot fluctuate along with the voltage of the voltage input end, thereby improving the power supply rejection ratio of the whole control circuit.
As an alternative embodiment, the driving circuit includes: the second enhanced NMOS tube N2 and the first enhanced PMOS tube P1; the grid electrode of the second enhanced NMOS tube N2 is connected with the drain electrode of the first enhanced NMOS tube N1 and the source electrode of the depletion NMOS tube DN1, the source electrode of the second enhanced NMOS tube N2 is grounded, and the drain electrode of the second enhanced NMOS tube N2 is connected with the drain electrode of the first enhanced PMOS tube P1; the source electrode of the first enhanced PMOS tube P1 is connected with the voltage input end, and the grid electrode of the first enhanced PMOS tube P1 is connected with the grid electrode of the adjusting tube.
The driving circuit comprises a second enhanced NMOS tube N2 and a first enhanced PMOS tube P1, wherein the grid electrode of the second enhanced NMOS tube N2 is connected with the output end of the error amplification voltage conversion circuit and is used for receiving error amplification voltage converted from reference voltage.
The source electrode of the second enhanced NMOS tube N2 is grounded, and the drain electrode of the second enhanced NMOS tube N2 is connected with the drain electrode of the first enhanced PMOS tube P1; the source electrode of the first enhanced PMOS tube P1 is connected with the voltage input end, and the grid electrode of the first enhanced PMOS tube P1 is connected with the grid electrode of the adjusting tube. The first enhancement type PMOS tube P1 and the adjusting tube, namely the second enhancement type PMOS tube P2, form a current mirror, and copy the drain current of the second enhancement type PMOS tube P2.
The grid electrode of the first enhanced NMOS tube N1 is used as the input end of the error amplification voltage conversion circuit to be connected between the resistor R1 and the resistor R2, and the grid electrode voltage V of the enhanced first enhanced NMOS tube N1 N1S ＝R2*V OUT /(r1+r2); if V is N1S Lower than the reference voltage V ref The error amplification voltage V is outputted from the error amplification voltage conversion circuit N2S Rise, V N2S Controlling the grid voltage of the second enhanced NMOS transistor N2, V N2S The drain V of the second enhanced NMOS transistor N2 is raised N2Y Reduce, the drain current of the first enhancement PMOS tube P1 is increased, and the grid voltage V of the second enhancement PMOS tube P2 is further increased P2S (i.e. V N2Y ) Lowering V P2S Reducing the output voltage V OUT The voltage rises and the output voltage V OUT Is set to be the sampling voltage V of N1S Followed by elevation; otherwise, if the voltage V is sampled N1S Higher than the reference voltage V ref V is then N2S Lowering V N2Y And V P2S Raise and thereby lower V OUT Voltage is V N1S The voltage is stabilized at the reference voltage value V ref 。
As an alternative embodiment, the adjusting tube is a second enhancement PMOS tube P2; the grid electrode of the second enhanced PMOS tube P2 is connected with the grid electrode of the first enhanced PMOS tube P1 of the driving circuit, the drain electrode of the second enhanced PMOS tube P2 is connected with the voltage output end, and the source electrode of the second enhanced PMOS tube P2 is connected with the voltage input end.
The grid electrode of the second enhanced PMOS tube P2 is connected to the driving circuit, and the state of the second enhanced PMOS tube P2 is controlled according to the error amplification voltage to adjust the output voltage, so that the control effect is better.
As an alternative embodiment, the sampling circuit comprises: a first resistor R1 and a second resistor R2; the first resistor R1 and the second resistor R2 are connected in series between the voltage output end and the grounding end, one end of the first resistor R1 is connected with the voltage output end, and the other end of the first resistor R1 is connected with the second resistor and outputs the output voltage; one end of the second resistor R2 is connected with the other end of the first resistor R1, and the other end of the second resistor R2 is grounded.
The sampling circuit includes: a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series between the voltage output end and the grounding end, and the connection part of the first resistor R1 and the second resistor R2 outputs sampling voltage.
The low-dropout linear voltage regulator provided by the embodiment of the invention comprises an input end, an output end and a low-dropout linear voltage regulator circuit arranged between the input end and the output end, wherein the low-dropout linear voltage regulator circuit is any one of the low-dropout linear voltage regulator circuits; the input end is connected with the voltage input end of the low dropout linear voltage stabilizing circuit, and the output end is connected with the voltage output end of the low dropout linear voltage stabilizing circuit.
It should be noted that the term "comprising" and its variants as used in the embodiments of the present invention are open-ended, i.e. "including but not limited to". The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. References to "one or more" modifications in the examples of the invention are intended to be illustrative rather than limiting, and it will be understood by those skilled in the art that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise.
The term "embodiment" in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. The various embodiments in this specification are described in a related manner, with identical and similar parts being referred to each other. In particular, for apparatus, devices, system embodiments, the description is relatively simple as it is substantially similar to method embodiments, see for relevant part of the description of method embodiments.
The above examples merely represent a few embodiments of the present invention, which are described in more detail and are not to be construed as limiting the scope of the patent claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of the invention should be assessed as that of the appended claims.
Claims (10)
1. A soft-start low dropout linear voltage regulator circuit, comprising: the device comprises an adjusting tube connected between a voltage input end and a voltage output end, an output voltage sampling circuit used for sampling the input end of the circuit, an error amplification voltage conversion circuit used for generating a reference voltage according to the sampled output voltage and converting the reference voltage into a corresponding current which is compared with the reference current, a driving circuit used for driving the adjusting tube according to the change of the error amplification voltage, and a soft start circuit used for realizing the soft start of the circuit; wherein,
the soft start circuit comprises a generating circuit, an operational amplifier (A) and a third enhanced NMOS tube (N3); the generation circuit is arranged between the voltage input end and the grounding end and is used for generating a slope signal; the positive and negative input ends of the operational amplifier (A) are respectively connected with the input end of the sampling circuit and the generating circuit and used for comparing the voltage of the input end of the sampling circuit and the voltage of the slope signal, the output end of the operational amplifier (A) is connected with the grid electrode of the third enhanced NMOS tube (N3), the source electrode of the third enhanced NMOS tube (N3) is connected with the error amplification voltage conversion circuit, and the drain electrode of the third enhanced NMOS tube is connected with the voltage input end.
2. The low dropout linear regulator circuit according to claim 1, wherein said generating circuit comprises: a current source (I1) and a capacitor (C1);
the current source (I1) is arranged on a circuit between the voltage input end and the operational amplifier (A), one end of the capacitor (C1) is connected with the current source (I1) and the operational amplifier (A), and the other end of the capacitor (C1) is grounded.
3. The low dropout linear voltage regulator circuit according to claim 2, wherein one end of said capacitor (C1) connected to said operational amplifier (a) is connected to the positive input terminal of said operational amplifier (a);
the negative input end of the operational amplifier (A) is connected with the output end of the sampling circuit.
4. A low dropout linear voltage regulator circuit according to claim 3, wherein the output of the operational amplifier (a) is connected to ground through a zener diode (ZD 1);
the negative electrode of the voltage stabilizing diode (ZD 1) is connected with the output end of the operational amplifier (A), and the positive electrode of the voltage stabilizing diode (ZD 1) is grounded.
5. The low dropout linear voltage regulator circuit according to claim 1, wherein said error amplifying voltage converting circuit comprises: a first enhancement NMOS tube (N1) and a depletion NMOS tube (DN 1);
the grid electrode of the first enhanced NMOS tube (N1) is connected with the output end of the sampling circuit, the source electrode of the first enhanced NMOS tube (N1) is grounded, and the drain electrode of the first enhanced NMOS tube (N1) is connected with the source electrode of the depletion NMOS tube (DN 1);
the source electrode and the grid electrode of the depletion type NMOS tube (DN 1) are in short circuit, and the drain electrode of the depletion type NMOS tube (DN 1) is connected with the source electrode of the third enhancement type NMOS tube (N3).
6. The low dropout linear voltage regulator circuit according to claim 5, wherein a drain of the third enhancement NMOS (N3) is connected to the voltage input terminal, and a source of the third enhancement NMOS (N3) is connected to a drain of a depletion NMOS (DN 1) of the error amplifying voltage converting circuit.
7. The low dropout linear regulator circuit according to claim 1, wherein said drive circuit comprises: a second enhanced NMOS tube (N2) and a first enhanced PMOS tube (P1);
the grid electrode of the second enhanced NMOS tube (N2) is connected with the drain electrode of the first enhanced NMOS tube (N1) and the source electrode of the depletion NMOS tube (DN 1), the source electrode of the second enhanced NMOS tube (N2) is grounded, and the drain electrode of the second enhanced NMOS tube (N2) is connected with the drain electrode of the first enhanced PMOS tube (P1);
the source electrode of the first enhanced PMOS tube (P1) is connected with the voltage input end, and the grid electrode of the first enhanced PMOS tube (P1) is connected with the grid electrode of the adjusting tube.
8. The low dropout linear regulator circuit according to claim 7, wherein said regulator tube is a second enhancement PMOS tube (P2);
the grid electrode of the second enhanced PMOS tube (P2) is connected with the grid electrode of the first enhanced PMOS tube (P1) of the driving circuit, the drain electrode of the second enhanced PMOS tube (P2) is connected with the voltage output end, and the source electrode of the second enhanced PMOS tube (P2) is connected with the voltage input end.
9. The low dropout linear regulator circuit according to claim 1, wherein said sampling circuit comprises: a first resistor (R1) and a second resistor (R2);
the first resistor (R1) and the second resistor (R2) are connected in series between the voltage output end and the grounding end, one end of the first resistor (R1) is connected with the voltage output end, and the other end of the first resistor (R1) is connected with the second resistor and outputs the sampling output voltage;
one end of the second resistor (R2) is connected with the other end of the first resistor (R1), and the other end of the second resistor (R2) is grounded.
10. A soft-start low dropout linear regulator comprising an input terminal, an output terminal, and a low dropout linear regulator circuit disposed between the input terminal and the output terminal, the low dropout linear regulator circuit being the low dropout linear regulator circuit of any one of claims 1 to 9;
the input end is connected with the voltage input end of the low dropout linear voltage stabilizing circuit, and the output end is connected with the voltage output end of the low dropout linear voltage stabilizing circuit.
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| CN202311472440.2A CN117311433A (en) | 2023-11-07 | 2023-11-07 | Soft-start low-dropout linear voltage stabilizing circuit |
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| CN202311472440.2A CN117311433A (en) | 2023-11-07 | 2023-11-07 | Soft-start low-dropout linear voltage stabilizing circuit |
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| CN113110694A (en) * | 2021-04-30 | 2021-07-13 | 南京邮电大学 | Low dropout regulator circuit with current surge suppression |
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| JPH10283048A (en) * | 1997-04-10 | 1998-10-23 | Toshiba Corp | Constant current circuit |
| US20100164579A1 (en) * | 2008-11-14 | 2010-07-01 | Beniamin Acatrinei | Low cost ultra versatile mixed signal controller circuit |
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