CN202533829U - Non-capacitance low-voltage-differential linear voltage stabilizing system and bias current adjusting circuit thereof - Google Patents

Abstract

The utility model relates to the field of design of an integrated circuit, and provides a non-capacitance low-differential-voltage linear voltage stabilizing system and a bias current adjusting circuit thereof. According to the utility model, the non-capacitance low-differential-voltage linear voltage stabilizing system is internally provided with the bias current adjusting circuit comprising a static voltage signal generating module, a high-pass filtering module and a current adjusting module, and a bias current of the linear voltage stabilizing system is subjected to adaptability adjustment according to an output current variation condition of a non-capacitance low-differential-voltage linear voltage stabilizer, so that the purpose of dynamically adjusting the bias current can be realized, the power consumption of the non-capacitance low-differential-voltage linear voltage stabilizer can be reduced, and a transient response speed of the non-capacitance low-differential-voltage linear voltage stabilizer is enhanced. Therefore, the problems of ultrahigh power consumption and low transient response speed of the conventional non-capacitance low-differential-voltage linear voltage stabilizer can be solved.

Description

No capacitor type low pressure difference linearity voltage-stabilizing system and bias current adjustment circuit thereof

Technical field

The utility model belongs to the IC design field, relates in particular to a kind of no capacitor type low pressure difference linearity voltage-stabilizing system and bias current thereof adjustment circuit.

Background technology

(Low-Dropout regulator LDO) as important power management module, is widely used in various handheld devices and the portable type electronic product low pressure difference linear voltage regulator.

At present, low pressure difference linear voltage regulator is divided into capacitor type and two big types of no capacitor types, and wherein, the capacitor type low pressure difference linear voltage regulator is meant the low pressure difference linear voltage regulator of the outer big electric capacity of traditional strap.With respect to capacitor type LDO, no capacitor type LDO is simple in structure because of possessing, cost is low and be convenient to integrated advantage obtains using comparatively widely.

Yet, in no capacitor type LDO, cause the power consumption of whole LDO circuit too high owing to the circuit bias electric current can't obtain rapid adjustment when its output current changes, and transient response speed is slow.Therefore, there is the problem that power consumption is too high and transient response speed is slow in existing no capacitor type low pressure difference linear voltage regulator.

The utility model content

The purpose of the utility model is to provide a kind of bias current adjustment circuit that does not have capacitor type low pressure difference linearity voltage-stabilizing system, is intended to solve the problem that the existing power consumption of existing no capacitor type low pressure difference linear voltage regulator is too high and transient response speed is slow.

The utility model is achieved in that a kind of bias current adjustment circuit that does not have a capacitor type low pressure difference linearity voltage-stabilizing system, and with direct supply and do not have the capacitor type low pressure difference linear voltage regulator and be connected, said bias current adjustment circuit comprises:

The output terminal of the said direct supply of power supply termination; First control end is connected with Section Point with the first node of said no capacitor type low pressure difference linear voltage regulator respectively with second control end, generates the quiescent voltage signal generation module of two different quiescent voltage signals according to the change in voltage of the first node of said no capacitor type low pressure difference linear voltage regulator and Section Point;

The output terminal of the said direct supply of power supply termination; The first input end and second input end connect first output terminal and second output terminal of said quiescent voltage signal generation module respectively, said two different quiescent voltage signals are carried out the high-pass filtering module of Filtering Processing;

The output terminal of the said direct supply of power supply termination; First control end is connected with second output terminal with first output terminal of said high-pass filtering module respectively with second control end; The bias current end of the said no capacitor type low pressure difference linear voltage regulator of Current Regulation termination, two current regulating module that different quiescent voltage signals is regulated the bias current of said no capacitor type low pressure difference linear voltage regulator crossing according to said high-pass filtering resume module.

Another purpose of the utility model also is to provide a kind of no capacitor type low pressure difference linearity voltage-stabilizing system; Said no capacitor type low pressure difference linearity voltage-stabilizing system comprises direct supply, no capacitor type low pressure difference linear voltage regulator and bias current adjustment circuit; Said bias current adjustment circuit is connected with said direct supply and said no capacitor type low pressure difference linear voltage regulator, and said bias current adjustment circuit comprises:

The output terminal of the said direct supply of power supply termination; First control end is connected with Section Point with the first node of said no capacitor type low pressure difference linear voltage regulator respectively with second control end, generates the quiescent voltage signal generation module of two different quiescent voltage signals according to the change in voltage of the first node of said no capacitor type low pressure difference linear voltage regulator and Section Point;

The output terminal of the said direct supply of power supply termination; The first input end and second input end connect first output terminal and second output terminal of said quiescent voltage signal generation module respectively, said two different quiescent voltage signals are carried out the high-pass filtering module of Filtering Processing;

The output terminal of the said direct supply of power supply termination; First control end is connected with second output terminal with first output terminal of said high-pass filtering module respectively with second control end; The bias current end of the said no capacitor type low pressure difference linear voltage regulator of Current Regulation termination, two current regulating module that different quiescent voltage signals is regulated the bias current of said no capacitor type low pressure difference linear voltage regulator crossing according to said high-pass filtering resume module.

In the utility model; Through in no capacitor type low pressure difference linearity voltage-stabilizing system, adopting the bias current adjustment circuit that comprises said quiescent voltage signal generation module, said high-pass filtering module and said current regulating module; Output current situation of change according to no capacitor type low pressure difference linear voltage regulator is carried out accommodation to its bias current; Thereby realize the dynamically purpose of adjustment bias current; Reach the power consumption that reduces no capacitor type low pressure difference linear voltage regulator simultaneously, and promote the effect of its transient response speed, solved the problem that the existing power consumption of existing no capacitor type low pressure difference linear voltage regulator is too high and transient response speed is slow.

Description of drawings

Fig. 1 is the modular structure figure of the bias current adjustment circuit of the no capacitor type low pressure difference linearity voltage-stabilizing system that provides of the utility model embodiment;

Fig. 2 is the basic circuit structure figure of existing no capacitor type low pressure difference linear voltage regulator;

Fig. 3 is the exemplary circuit structural drawing of the bias current adjustment circuit of the no capacitor type low pressure difference linearity voltage-stabilizing system that provides of the utility model embodiment.

Embodiment

For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

In the utility model embodiment; Through in no capacitor type low pressure difference linearity voltage-stabilizing system, adopting the bias current adjustment circuit that comprises quiescent voltage signal generation module, high-pass filtering module and current regulating module; Output current situation of change according to no capacitor type low pressure difference linear voltage regulator is carried out accommodation to its bias current; Thereby realize the dynamically purpose of adjustment bias current; Reach the power consumption that reduces no capacitor type low pressure difference linear voltage regulator simultaneously, and promote the effect of its transient response speed.

Fig. 1 shows the modular structure of the bias current adjustment circuit of the no capacitor type low pressure difference linearity voltage-stabilizing system that the utility model embodiment provides, and for the ease of explanation, only shows the part relevant with the utility model embodiment, and details are as follows:

The bias current of no capacitor type low pressure difference linearity voltage-stabilizing system adjustment circuit 100, with direct supply 200 and do not have capacitor type low pressure difference linear voltage regulator 300 and be connected, this bias current adjustment circuit 100 comprises:

The output terminal of power supply termination direct supply 200; First control end is connected with Section Point VBN with the first node VBP of no capacitor type low pressure difference linear voltage regulator 300 respectively with second control end, generates the quiescent voltage signal generation module 101 of two different quiescent voltage signals according to the change in voltage of the first node of no capacitor type low pressure difference linear voltage regulator 300 and Section Point.

The output terminal of power supply termination direct supply 200; The first input end and second input end connect first output terminal and second output terminal of quiescent voltage signal generation module 101 respectively, said two different quiescent voltage signals are carried out the high-pass filtering module 102 of Filtering Processing.

The output terminal of power supply termination direct supply 200; First control end is connected with second output terminal with first output terminal of high-pass filtering module 102 respectively with second control end; The Current Regulation termination does not have the bias current end IB of capacitor type low pressure difference linear voltage regulator 300, two current regulating module 103 that different quiescent voltage signals is regulated the bias current of no capacitor type low pressure difference linear voltage regulator 300 handling according to high-pass filtering module 102.

In the utility model embodiment; Fig. 2 shows the circuit structure of no capacitor type low pressure difference linear voltage regulator 300; No capacitor type low pressure difference linear voltage regulator 300 is introduced WV Vin from direct supply 200; VBP, VBN and IB are respectively first node, Section Point and the bias current end of no capacitor type low pressure difference linear voltage regulator 300; The electric current I B_EA of current source I1 place branch road is the bias current of no capacitor type low pressure difference linear voltage regulator 300, and PMOS pipe Mpb is the output stage of no capacitor type low pressure difference linear voltage regulator 300, and its conducting electric current is the output current of no capacitor type low pressure difference linear voltage regulator 300.When the conducting electric current of PMOS pipe Mpb changes; The output voltage of whole no capacitor type low pressure difference linear voltage regulator 300 also can change; The voltage of Section Point VBN also can be along with variation; Through detecting the change in voltage of Section Point VBN, then can obtain the situation of change of the output current of no capacitor type low pressure difference linear voltage regulator 300 fast.The dotted line left side is the error amplifying circuit of no capacitor type low pressure difference linear voltage regulator 300, and the dotted line right side is the output-stage circuit of no capacitor type low pressure difference linear voltage regulator 300.

The circuit structure of no capacitor type low pressure difference linear voltage regulator 300 shown in Figure 2 is the basic circuit structure among the existing no capacitor type LDO; For other no capacitor type low pressure difference linear voltage regulators; The bias current adjustment circuit that the utility model embodiment is provided is suitable for too; The circuit structure of the no capacitor type low pressure difference linear voltage regulator that therefore, more than provides is not in order to limit the scope of application of the utility model.

Fig. 3 shows the exemplary circuit structure of the bias current adjustment circuit of the no capacitor type low pressure difference linearity voltage-stabilizing system that the utility model embodiment provides, and for the ease of explanation, only shows the part relevant with the utility model embodiment, and details are as follows:

As the utility model one embodiment, quiescent voltage signal generation module 101 comprises:

PMOS pipe Mp1, NMOS pipe Mn1, PMOS pipe Mp2, NMOS pipe Mn2, PMOS pipe Mp3, NMOS pipe Mn3, PMOS pipe Mp4 and NMOS pipe Mn4;

The source electrode of PMOS pipe Mp1 and the power end and first control end that grid is respectively quiescent voltage signal generation module 101; The drain electrode of PMOS pipe Mp1 connects the drain electrode of NMOS pipe Mn1; The grid of NMOS pipe Mn1 is second control end of quiescent voltage signal generation module 101; The source electrode of NMOS pipe Mn1 connects equipotential ground; The source electrode of PMOS pipe Mp2 connects the source electrode of PMOS pipe Mp1, and the grid of the grid of PMOS pipe Mp2 and NMOS pipe Mn2 is connected to the drain electrode of PMOS pipe Mp1 altogether, and the drain electrode of the drain electrode of PMOS pipe Mp2 and NMOS pipe Mn2 connects and form first output terminal of quiescent voltage signal generation module 101 altogether; The source electrode of NMOS pipe Mn2 connects equipotential ground; The source electrode of PMOS pipe Mp3 is connected with the source electrode of PMOS pipe Mp2 and the grid of PMOS pipe Mp1 respectively with grid, and the drain electrode of PMOS pipe Mp3 connects the drain electrode of NMOS pipe Mn3, and the grid of NMOS pipe Mn3 and source electrode connect grid and the equipotential ground of NMOS pipe Mn1 respectively; The source electrode of PMOS pipe Mp4 connects the source electrode of PMOS pipe Mp3; The grid of the grid of PMOS pipe Mp4 and NMOS pipe Mn4 is connected to the drain electrode of PMOS pipe Mp3 altogether, and the drain electrode of the drain electrode of PMOS pipe Mp4 and NMOS pipe Mn4 connects and form second output terminal of quiescent voltage signal generation module 101 altogether, and the source electrode of NMOS pipe Mn4 connects equipotential ground.

As the utility model one embodiment, high-pass filtering module 102 comprises:

Capacitor C 1, resistance R 1, resistance R 2 and capacitor C 2;

The first input end of the just very high-pass filtering module of capacitor C 1 102; First end of the negative pole of capacitor C 1 and resistance R 1 connects and forms first output terminal of high-pass filtering module 102 altogether; The second termination equipotential ground of resistance R 1; Second input end of the just very high-pass filtering module of capacitor C 2 102, first end of resistance R 2 is the power end of high-pass filtering module 102, second end of resistance R 2 and the negative pole of capacitor C 2 connect and form second output terminal of high-pass filtering module 102 altogether.

As the utility model one embodiment, current regulating module 103 comprises:

NMOS pipe Mns, PMOS pipe Mps, PMOS pipe Mpb1, PMOS pipe Mpb2, PMOS pipe Mpb3, current source Ib, NMOS pipe Mnb1 and NMOS pipe Mnb2;

The grid of NMOS pipe Mns is first control end of current regulating module 103; The drain electrode of NMOS pipe Mns is connected with drain electrode with the source electrode of PMOS pipe Mps respectively with source electrode; The source electrode of the source electrode of the source electrode of PMOS pipe Mpb1, PMOS pipe Mpb2 and PMOS pipe Mpb3 connects and forms the power end of current regulating module 103 altogether; The drain electrode of PMOS pipe Mpb1 connects the source electrode of PMOS pipe Mps; The grid of PMOS pipe Mpb1 is connected with the grid of PMOS pipe Mpb2 and the grid of PMOS pipe Mpb3 simultaneously; The drain electrode of PMOS pipe Mpb2 is connected with the drain electrode of PMOS pipe Mps and the drain electrode of NMOS pipe Mnb1 simultaneously, the drain electrode that the input end of current source Ib and output terminal meet PMOS pipe Mpb3 respectively and equipotential, the drain electrode that NMOS manages Mnb1 with manage the Mnb2 grid with NMOS again after grid connects altogether and be connected; The drain electrode of NMOS pipe Mnb2 is the Current Regulation end of current regulating module 103, and the source electrode of the source electrode of NMOS pipe Mnb1 and NMOS pipe Mnb2 is connected to equipotential ground altogether.

In the utility model embodiment, PMOS pipe Mpb1, PMOS pipe Mpb2 and PMOS pipe Mpb3 three's dimension scale is N: 1: 1, wherein N was the positive integer greater than 1; PMOS pipe Mpb1, PMOS pipe Mpb2 and PMOS pipe Mpb3 three's conducting electric current is respectively Ib1, Ib2 and Ib3, wherein Ib1＞Ib2=Ib3.

Below in conjunction with Fig. 2 and Fig. 3 the principle of work of bias current adjustment circuit 100 is described in detail:

When no capacitor type low pressure difference linear voltage regulator 300 is in homeostasis; Through the size of PMOS pipe Mp1, NMOS pipe Mn1, PMOS pipe Mp3 and NMOS pipe Mn3 is set; Make the voltage of node Vo1 and node Vo2 be respectively Vin (Vin is the output voltage of direct supply 200) and 0; Manage after phase inverter that Mn4 forms carries out the anti-phase processing to the voltage of node Vo1 and node Vo2 respectively through the phase inverter formed by PMOS pipe Mp2 and NMOS pipe Mn2 with by PMOS pipe Mp4 and NMOS; The voltage of node Vo1_N and node Vo2_N is respectively 0 and Vin, and the voltage of node Vo1_N and node Vo2_N is two different quiescent voltage signals that quiescent voltage signal generation module 101 generates.Respectively the voltage signal of node Vo1_N and node Vo2_N is carried out Filtering Processing through Hi-pass filter of forming by capacitor C 1 and resistance R 1 and the Hi-pass filter of forming by capacitor C 2 and resistance R 2 subsequently; Then the voltage of node N1 and node N2 is respectively 0 and Vin; So; NMOS pipe Mns and PMOS pipe Mps all end; The conducting current Ib 2 that the current mirror of being made up of NMOS pipe Mnb1 and NMOS pipe Mnb2 is managed Mpb2 with PMOS is mirrored to NMOS and manages Mnb2 and belong on the branch road, does not equal Ib2 so there is the bias current IB_EA of capacitor type low pressure difference linear voltage regulator 300, and then the error amplifying circuit on dotted line right side works in the bias state of super low-power consumption among Fig. 2.

When the load current of no capacitor type low pressure difference linear voltage regulator 300 by little electric current during to big current step saltus step, its output voltage can descend, the voltage of node VFB is along with decline; The voltage of Section Point VBN rises simultaneously, thereby makes the voltage of node Vo1 be pulled low to 0, and the voltage of node Vo2 raises and is Vin; Then this moment, node Vo1_N output voltage was Vin, and node Vo2_N output voltage is 0, and the voltage of node N1 and node N2 is also being followed and become Vin and 0 respectively; So; NMOS pipe Mns and the equal conducting of PMOS pipe Mps, the conducting current Ib 1 of NMOS pipe Mnb1 is by on the branch road of NMOS pipe Mnb1 mirror image to NMOS pipe Mnb2 place, therefore; The bias current IB_EA of no capacitor type low pressure difference linear voltage regulator 300 equals Ib1+Ib2; Bias current IB_EA is enhanced, and the error amplifying circuit that orders about in the no capacitor type low pressure difference linear voltage regulator 300 charges to the stray capacitance of PMOS pipe Mpb, and then the voltage of node VO is dragged down fast; Thereby PMOS pipe Mpb output current is increased, satisfy actual load current demand with the output current that reaches no capacitor type low pressure difference linear voltage regulator 300.

When the load current of no capacitor type low pressure difference linear voltage regulator 300 by big electric current during to little current step saltus step, its output voltage can rise, the voltage of node VFB is along with rising; The voltage of Section Point VBN descends simultaneously, thereby the voltage of node Vo1 is drawn high to Vin, and the voltage drop of node Vo2 is low to moderate 0; Then this moment, node Vo1_N output voltage was 0, and node Vo2_N output voltage is Vin, and the voltage of node N1 and node N2 is also being followed and become 0 and Vin respectively; So; NMOS pipe Mns and PMOS pipe Mps all end, and NMOS pipe Mnb1 manages PMOS on conducting current Ib 2 mirror images to the NMOS pipe Mnb2 place branch road of Mpb2, therefore; The bias current IB_EA of no capacitor type low pressure difference linear voltage regulator 300 is reduced to Ib2; Bias current IB_EA is weakened, thereby PMOS pipe Mpb output current is reduced, and satisfies actual load current demand with the output current that reaches no capacitor type low pressure difference linear voltage regulator 300.

Bias current through 100 pairs of no capacitor type low pressure difference linear voltage regulators 300 of above-mentioned bias current adjustment circuit is adjusted to control the size of its output current; Promoted the output current switching rate of no capacitor type low pressure difference linear voltage regulator 300; Increase its loop bandwidth, and reached the purpose that promotes its transient response performance.

Another purpose of the utility model embodiment also is to provide a kind of no capacitor type low pressure difference linearity voltage-stabilizing system; This no capacitor type low pressure difference linearity voltage-stabilizing system comprises direct supply 200, no capacitor type low pressure difference linear voltage regulator 300 and bias current adjustment circuit 100; Bias current adjustment circuit 100 is with direct supply 200 and do not have capacitor type low pressure difference linear voltage regulator 300 and be connected, and bias current is adjusted circuit 100 and comprised:

The output terminal of power supply termination direct supply 200; First control end is connected with Section Point VBN with the first node VBP of no capacitor type low pressure difference linear voltage regulator 300 respectively with second control end, generates the quiescent voltage signal generation module 101 of two different quiescent voltage signals according to the change in voltage of the first node of no capacitor type low pressure difference linear voltage regulator 300 and Section Point.

The output terminal of power supply termination direct supply 200; The first input end and second input end connect first output terminal and second output terminal of quiescent voltage signal generation module 101 respectively, said two different quiescent voltage signals are carried out the high-pass filtering module 102 of Filtering Processing.

The output terminal of power supply termination direct supply 200; First control end is connected with second output terminal with first output terminal of high-pass filtering module 102 respectively with second control end; The Current Regulation termination does not have the bias current end IB of capacitor type low pressure difference linear voltage regulator 300, two current regulating module 103 that different quiescent voltage signals is regulated the bias current of no capacitor type low pressure difference linear voltage regulator 300 handling according to high-pass filtering module 102.

In the utility model embodiment; Through in no capacitor type low pressure difference linearity voltage-stabilizing system, adopting the bias current adjustment circuit that comprises quiescent voltage signal generation module, high-pass filtering module and current regulating module; Output current situation of change according to no capacitor type low pressure difference linear voltage regulator is carried out accommodation to its bias current; Thereby realize the dynamically purpose of adjustment bias current; Reach the power consumption that reduces no capacitor type low pressure difference linear voltage regulator simultaneously, and promote the effect of its transient response speed, solved the problem that the existing power consumption of existing no capacitor type low pressure difference linear voltage regulator is too high and transient response speed is slow.

The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection domain of the utility model.

Claims (8)

1. bias current adjustment circuit that does not have a capacitor type low pressure difference linearity voltage-stabilizing system with direct supply and do not have the capacitor type low pressure difference linear voltage regulator and be connected, is characterized in that said bias current adjustment circuit comprises:

The output terminal of the said direct supply of power supply termination; First control end is connected with Section Point with the first node of said no capacitor type low pressure difference linear voltage regulator respectively with second control end, generates the quiescent voltage signal generation module of two different quiescent voltage signals according to the change in voltage of the first node of said no capacitor type low pressure difference linear voltage regulator and Section Point;

The output terminal of the said direct supply of power supply termination; The first input end and second input end connect first output terminal and second output terminal of said quiescent voltage signal generation module respectively, said two different quiescent voltage signals are carried out the high-pass filtering module of Filtering Processing;

The output terminal of the said direct supply of power supply termination; First control end is connected with second output terminal with first output terminal of said high-pass filtering module respectively with second control end; The bias current end of the said no capacitor type low pressure difference linear voltage regulator of Current Regulation termination, two current regulating module that different quiescent voltage signals is regulated the bias current of said no capacitor type low pressure difference linear voltage regulator crossing according to said high-pass filtering resume module.

2. bias current adjustment circuit as claimed in claim 1 is characterized in that said quiescent voltage signal generation module comprises:

PMOS pipe Mp1, NMOS pipe Mn1, PMOS pipe Mp2, NMOS pipe Mn2, PMOS pipe Mp3, NMOS pipe Mn3, PMOS pipe Mp4 and NMOS pipe Mn4;

The source electrode of said PMOS pipe Mp1 and the power end and first control end that grid is respectively said quiescent voltage signal generation module; The drain electrode of said PMOS pipe Mp1 connects the drain electrode of said NMOS pipe Mn1; The grid of said NMOS pipe Mn1 is second control end of said quiescent voltage signal generation module; The source electrode of said NMOS pipe Mn1 connects equipotential ground; The source electrode of said PMOS pipe Mp2 connects the source electrode of said PMOS pipe Mp1; The grid of the grid of said PMOS pipe Mp2 and said NMOS pipe Mn2 is connected to the drain electrode of said PMOS pipe Mp1 altogether; The drain electrode of the drain electrode of said PMOS pipe Mp2 and said NMOS pipe Mn2 connects and forms first output terminal of said quiescent voltage signal generation module altogether, and the source electrode of said NMOS pipe Mn2 connects equipotential ground, and the source electrode of said PMOS pipe Mp3 is connected with the source electrode of said PMOS pipe Mp2 and the grid of said PMOS pipe Mp1 respectively with grid; The drain electrode of said PMOS pipe Mp3 connects the drain electrode of said NMOS pipe Mn3; The grid of said NMOS pipe Mn3 and source electrode connect grid and the equipotential ground of said NMOS pipe Mn1 respectively, and the source electrode of said PMOS pipe Mp4 connects the source electrode of said PMOS pipe Mp3, and the grid of the grid of said PMOS pipe Mp4 and said NMOS pipe Mn4 is connected to the drain electrode of said PMOS pipe Mp3 altogether; The drain electrode of the drain electrode of said PMOS pipe Mp4 and said NMOS pipe Mn4 connects and forms second output terminal of said quiescent voltage signal generation module altogether, and the source electrode of said NMOS pipe Mn4 connects equipotential ground.

3. bias current adjustment circuit as claimed in claim 1 is characterized in that said high-pass filtering module comprises:

Capacitor C 1, resistance R 1, resistance R 2 and capacitor C 2;

The first input end of the just very said high-pass filtering module of said capacitor C 1; First end of the negative pole of said capacitor C 1 and said resistance R 1 connects and forms first output terminal of said high-pass filtering module altogether; The second termination equipotential ground of said resistance R 1; Second input end of the just very said high-pass filtering module of said capacitor C 2; First end of said resistance R 2 is the power end of said high-pass filtering module, and second end of said resistance R 2 and the negative pole of said capacitor C 2 connect and form second output terminal of said high-pass filtering module altogether.

4. bias current adjustment circuit as claimed in claim 1 is characterized in that said current regulating module comprises:

NMOS pipe Mns, PMOS pipe Mps, PMOS pipe Mpb1, PMOS pipe Mpb2, PMOS pipe Mpb3, current source Ib, NMOS pipe Mnb1 and NMOS pipe Mnb2;

The grid of said NMOS pipe Mns is first control end of said current regulating module; The drain electrode of said NMOS pipe Mns is connected with drain electrode with the source electrode of said PMOS pipe Mps respectively with source electrode; The source electrode of the source electrode of the source electrode of said PMOS pipe Mpb1, said PMOS pipe Mpb2 and said PMOS pipe Mpb3 connects and forms the power end of said current regulating module altogether; The drain electrode of said PMOS pipe Mpb1 connects the source electrode of said PMOS pipe Mps; The grid of said PMOS pipe Mpb1 is connected with the grid of said PMOS pipe Mpb2 and the grid of said PMOS pipe Mpb3 simultaneously; The drain electrode of said PMOS pipe Mpb2 is connected with the drain electrode of said PMOS pipe Mps and the drain electrode of said NMOS pipe Mnb1 simultaneously; The input end of said current source Ib and output terminal connect drain electrode and the equipotential ground of said PMOS pipe Mpb3 respectively; The drain electrode of said NMOS pipe Mnb1 with is connected with said NMOS pipe Mnb2 grid again after grid connects altogether, the drain electrode of said NMOS pipe Mnb2 is the Current Regulation end of said current regulating module, the source electrode that the source electrode of said NMOS pipe Mnb1 and said NMOS manage Mnb2 with being connected to equipotential altogether.

5. no capacitor type low pressure difference linearity voltage-stabilizing system; It is characterized in that; Said no capacitor type low pressure difference linearity voltage-stabilizing system comprises direct supply, no capacitor type low pressure difference linear voltage regulator and bias current adjustment circuit; Said bias current adjustment circuit is connected with said direct supply and said no capacitor type low pressure difference linear voltage regulator, and said bias current adjustment circuit comprises:

The output terminal of the said direct supply of power supply termination; First control end is connected with Section Point with the first node of said no capacitor type low pressure difference linear voltage regulator respectively with second control end, generates the quiescent voltage signal generation module of two different quiescent voltage signals according to the change in voltage of the first node of said no capacitor type low pressure difference linear voltage regulator and Section Point;

The output terminal of the said direct supply of power supply termination; The first input end and second input end connect first output terminal and second output terminal of said quiescent voltage signal generation module respectively, said two different quiescent voltage signals are carried out the high-pass filtering module of Filtering Processing;

The output terminal of the said direct supply of power supply termination; First control end is connected with second output terminal with first output terminal of said high-pass filtering module respectively with second control end; The bias current end of the said no capacitor type low pressure difference linear voltage regulator of Current Regulation termination, two current regulating module that different quiescent voltage signals is regulated the bias current of said no capacitor type low pressure difference linear voltage regulator crossing according to said high-pass filtering resume module.

6. no capacitor type low pressure difference linearity voltage-stabilizing system as claimed in claim 5 is characterized in that, said quiescent voltage signal generation module comprises:

PMOS pipe Mp1, NMOS pipe Mn1, PMOS pipe Mp2, NMOS pipe Mn2, PMOS pipe Mp3, NMOS pipe Mn3, PMOS pipe Mp4 and NMOS pipe Mn4;

The source electrode of said PMOS pipe Mp1 and the power end and first control end that grid is respectively said quiescent voltage signal generation module; The drain electrode of said PMOS pipe Mp1 connects the drain electrode of said NMOS pipe Mn1; The grid of said NMOS pipe Mn1 is second control end of said quiescent voltage signal generation module; The source electrode of said NMOS pipe Mn1 connects equipotential ground; The source electrode of said PMOS pipe Mp2 connects the source electrode of said PMOS pipe Mp1; The grid of the grid of said PMOS pipe Mp2 and said NMOS pipe Mn2 is connected to the drain electrode of said PMOS pipe Mp1 altogether; The drain electrode of the drain electrode of said PMOS pipe Mp2 and said NMOS pipe Mn2 connects and forms first output terminal of said quiescent voltage signal generation module altogether, and the source electrode of said NMOS pipe Mn2 connects equipotential ground, and the source electrode of said PMOS pipe Mp3 is connected with the source electrode of said PMOS pipe Mp2 and the grid of said PMOS pipe Mp1 respectively with grid; The drain electrode of said PMOS pipe Mp3 connects the drain electrode of said NMOS pipe Mn3; The grid of said NMOS pipe Mn3 and source electrode connect grid and the equipotential ground of said NMOS pipe Mn1 respectively, and the source electrode of said PMOS pipe Mp4 connects the source electrode of said PMOS pipe Mp3, and the grid of the grid of said PMOS pipe Mp4 and said NMOS pipe Mn4 is connected to the drain electrode of said PMOS pipe Mp3 altogether; The drain electrode of the drain electrode of said PMOS pipe Mp4 and said NMOS pipe Mn4 connects and forms second output terminal of said quiescent voltage signal generation module altogether, and the source electrode of said NMOS pipe Mn4 connects equipotential ground.

7. no capacitor type low pressure difference linearity voltage-stabilizing system as claimed in claim 5 is characterized in that said high-pass filtering module comprises:

Capacitor C 1, resistance R 1, resistance R 2 and capacitor C 2;

The first input end of the just very said high-pass filtering module of said capacitor C 1; First end of the negative pole of said capacitor C 1 and said resistance R 1 connects and forms first output terminal of said high-pass filtering module altogether; The second termination equipotential ground of said resistance R 1; Second input end of the just very said high-pass filtering module of said capacitor C 2; First end of said resistance R 2 is the power end of said high-pass filtering module, and second end of said resistance R 2 and the negative pole of said capacitor C 2 connect and form second output terminal of said high-pass filtering module altogether.

8. no capacitor type low pressure difference linearity voltage-stabilizing system as claimed in claim 1 is characterized in that said current regulating module comprises:

NMOS pipe Mns, PMOS pipe Mps, PMOS pipe Mpb1, PMOS pipe Mpb2, PMOS pipe Mpb3, current source Ib, NMOS pipe Mnb1 and NMOS pipe Mnb2;

The grid of said NMOS pipe Mns is first control end of said current regulating module; The drain electrode of said NMOS pipe Mns is connected with drain electrode with the source electrode of said PMOS pipe Mps respectively with source electrode; The source electrode of the source electrode of the source electrode of said PMOS pipe Mpb1, said PMOS pipe Mpb2 and said PMOS pipe Mpb3 connects and forms the power end of said current regulating module altogether; The drain electrode of said PMOS pipe Mpb1 connects the source electrode of said PMOS pipe Mps; The grid of said PMOS pipe Mpb1 is connected with the grid of said PMOS pipe Mpb2 and the grid of said PMOS pipe Mpb3 simultaneously; The drain electrode of said PMOS pipe Mpb2 is connected with the drain electrode of said PMOS pipe Mps and the drain electrode of said NMOS pipe Mnb1 simultaneously; The input end of said current source Ib and output terminal connect drain electrode and the equipotential ground of said PMOS pipe Mpb3 respectively; The drain electrode of said NMOS pipe Mnb1 with is connected with said NMOS pipe Mnb2 grid again after grid connects altogether, the drain electrode of said NMOS pipe Mnb2 is the Current Regulation end of said current regulating module, the source electrode that the source electrode of said NMOS pipe Mnb1 and said NMOS manage Mnb2 with being connected to equipotential altogether.

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