CN102945059B - Low pressure difference linear voltage regulator and limit method of adjustment thereof - Google Patents
Low pressure difference linear voltage regulator and limit method of adjustment thereof Download PDFInfo
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Abstract
A kind of low pressure difference linear voltage regulator and limit method of adjustment thereof, the source electrode of the PMOS adjustment transistor of described low pressure difference linear voltage regulator connects the first voltage end, and drain electrode connects the first end of described first resistance, and grid connects the output terminal of described error amplifier; First electric current providing unit is suitable for producing reference current; Second electric current providing unit is suitable for producing and regulates electric current, and described adjustment electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator; The first input end input reference voltage of error amplifier, the second input end connects the second end of described first resistance and the first end of the second resistance, the bias current that bias current inputs inputs described reference current and regulates electric current superposition to produce; The first end of the first resistance is the output terminal of described low pressure difference linear voltage regulator; Second end of the second resistance connects the second voltage end; The magnitude of voltage of the first voltage end is greater than the magnitude of voltage of the second voltage end.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of low pressure difference linear voltage regulator and limit method of adjustment thereof.
Background technology
The linear mu balanced circuit (LowDropoutRegulator, LDO) of low voltage difference is step-down type dc linear voltage regulator, and along with the development of SOC technology, it is ubiquitous in sector applications such as computing machine, communication, instrument and meter, consumer electronics, monitoring camera-shootings.Although compared with DC-DC switching voltage converter, the efficiency of LDO is lower, but it has the advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so LDO occupies very large proportion in power management class chip always.
Along with the raising of integrated level, increasing LDO is as SOC(SystemonChip, SOC (system on a chip)) submodule of chip is given the module for power supply of certain key and is integrated in this SOC, and in powerful SOC, integrated multiple LDO module gives different module for power supply very general.Simultaneously along with the frequency of operation of SOC system improves constantly, digital circuit wherein brings power supply disturbance also more and more serious, and this just needs LDO to have the performance requirements such as High-speed transient response speed, high output voltage control accuracy, high PSRR, low noise.
As shown in Figure 1, existing LDO comprises error amplifier OP, current source IL1, PMOS adjust the degeneration factor that transistor MP and dividing potential drop feedback network etc. are formed.Described dividing potential drop feedback network comprises the first resistance R1, the second resistance R2.Described first resistance R1 and the second resistance R2 forms partial pressure unit, and branch pressure voltage is fed back to the normal phase input end of error amplifier OP.The negative-phase input of described error amplifier OP receives reference voltage vref.Described current source IL1 provides the bias current of error amplifier OP.
LDO shown in Fig. 1 generally has two limits: one is the P1 limit adjusting transistor MP gate terminal at PMOS, and another is the P2 limit at LDO output terminal OUT.For ensureing the frequency stability of LDO and enough phase margins, the spacing of P1 limit and P2 limit should be enough large.The demander of current LDO all wishes that the power consumption of LDO under ideal case is enough low, the circuit power consumption of electric resistance partial pressure sampling is very little, this makes the frequency of P2 limit very little, P1 limit cannot accomplish the phase stability that much meet loop less of the frequency of P2 limit, and the electric capacity of P2 is much larger than the electric capacity of P1 point.So when LDO is standby when low-power consumption, dominant pole can only be P2 limit (two limit medium frequency low be dominant pole).When LDO output end current increases, the frequency of P1 limit remains unchanged substantially, and the frequency of P2 limit becomes large gradually, and the difference on the frequency between P1 limit and P2 limit reduces, and causes frequency stability to be deteriorated.
Miller-compensated mode becomes and is difficult to effectively under the demand of LDO low-power consumption standby, and the mode of the external bulky capacitor of output terminal can obtain good effect.At the external bulky capacitor of LDO output terminal OUT, reduce the increase amplitude of P1 limit when LDO output end current increases, ensure that the difference on the frequency of P1 limit and P2 limit is enough large, guarantee the stability of LDO.
But the development trend of LDO more and more tends to the pin cancelling LDO output terminal, if without the pin of LDO output terminal, then the bulky capacitor in said method cannot be connected outward at sheet with LDO output terminal, LDO frequency stabilization sex chromosome mosaicism then can still exist.
Summary of the invention
The problem that the present invention solves is the frequency stabilization sex chromosome mosaicism how solving low pressure difference linear voltage regulator.
For solving the problem, the invention provides a kind of low-dropout linear voltage-regulating circuit, comprising: error amplifier, the first electric current providing unit, the second electric current providing unit, PMOS adjust transistor, the first resistance and the second resistance;
The source electrode that described PMOS adjusts transistor connects the first voltage end, and drain electrode connects the first end of described first resistance, and grid connects the output terminal of described error amplifier;
Described first electric current providing unit is suitable for producing reference current;
Described second electric current providing unit is suitable for producing and regulates electric current, and described adjustment electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
The first input end input reference voltage of described error amplifier, the second input end connects the second end of described first resistance and the first end of the second resistance, the bias current that bias current inputs inputs described reference current and regulates electric current superposition to produce;
The first end of described first resistance is the output terminal of described low pressure difference linear voltage regulator;
Second end of described second resistance connects the second voltage end;
The magnitude of voltage of described first voltage end is greater than the magnitude of voltage of the second voltage end.
The present invention also provides a kind of limit method of adjustment of low pressure difference linear voltage regulator, comprising:
There is provided reference current and regulate electric current, described adjustment electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
Superpose described reference current and regulate electric current, to obtain bias current;
The bias current inputs of the error amplifier in described bias current to described low pressure difference linear voltage regulator is provided.
Compared with prior art, technical solution of the present invention at least has the following advantages:
When load becomes large, the output end current of low pressure difference linear voltage regulator becomes large, and the P2 pole frequency of low pressure difference linear voltage regulator output terminal becomes large, and also strain is large mutually to regulate electric current, make the output impedance of error amplifier diminish like this, the P1 pole frequency that PMOS adjusts transistor gate becomes large.Because the frequency of P1 limit and P2 limit increases all to some extent, so both frequency-splittings can remain on enough large distance substantially, ensure that the stability of low pressure difference linear voltage regulator.
Regulate electric current also very little when load current is very little, the power consumption of low pressure difference linear voltage regulator entirety is very low.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of prior art mesolow difference linear voltage-stabilizing circuit;
Fig. 2 is the low pressure difference linear voltage regulator schematic diagram of the embodiment of the present invention one;
Fig. 3 is a kind of specific embodiment schematic diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the present invention one;
Fig. 4 is the low pressure difference linear voltage regulator schematic diagram of the embodiment of the present invention two of the present invention;
Fig. 5 is a kind of specific embodiment schematic diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the present invention two.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.
As shown in Figure 2, the embodiment of the present invention one provides a kind of low pressure difference linear voltage regulator, comprising: error amplifier OP, and the first electric current providing unit 11, second electric current providing unit 12, PMOS adjust transistor MP1, the first resistance R1 and the second resistance R2.
The source electrode that described PMOS adjusts transistor MP1 connects the first voltage end VDD, and drain electrode connects the first end of described first resistance R1, and grid connects the output terminal OUT1 of described error amplifier OP;
Described first electric current providing unit 11 is suitable for producing reference current;
Described second electric current providing unit 12 is suitable for producing and regulates electric current, and described adjustment electric current is associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator;
The first input end IN1 input reference voltage of described error amplifier OP1, second input end IN2 connects second end of described first resistance R1 and the first end of the second resistance R2, the bias current that bias current inputs BIAS inputs described reference current and regulates electric current superposition to produce;
The first end of described first resistance R1 is the output terminal OUT2 of described low pressure difference linear voltage regulator;
Second end of described second resistance R2 connects the second voltage end GND;
The magnitude of voltage of described first voltage end VDD is greater than the magnitude of voltage of the second voltage end GND.
Described first voltage end VDD can provide supply voltage, and described second voltage end GND can for providing ground voltage.
The adjustment electric current that described second electric current providing unit 12 provides increases with the electric current increase of the output terminal of described low-pressure linear voltage stabilizer.
In embodiment one, second electric current providing unit 12 is connected with the output terminal OUT1 of error amplifier OP1 with the bias current inputs BIAS of described error amplifier OP1 respectively, be suitable for the electric current being gathered the output terminal OUT2 of described low pressure difference linear voltage regulator by the voltage on described error amplifier OP1 output terminal OUT1, thus produce the adjustment electric current be associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator.Described adjustment electric current can increase with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator and increase.
Fig. 3 is a kind of specific embodiment of the embodiment of the present invention one.As shown in Figure 3, described second electric current providing unit 12 can comprise: the second PMOS transistor MP2 and the first current lens unit IL1.The source electrode of described second PMOS transistor MP2 connects described first voltage end VDD, and drain electrode connects the input end of described second current lens unit, and grid connects the grid that described PMOS adjusts transistor MP1; First output terminal of described second current lens unit IL1 connects the bias current inputs BIAS of described error amplifier OP, and the second output terminal connects described second voltage end GND.
The electric current that first resistance R1 and the second resistance R2 flows through is very little, so the electric current of the output terminal OUT2 of the drain current of the first transistor MP1 and low pressure difference linear voltage regulator is roughly equal.When considering that low pressure difference linear voltage regulator normally works, transistor is all in saturation region, equal and the transistor drain electric current that underlayer voltage is the same equal (ignoring channel-length modulation) of gate source voltage difference, so the drain current that the drain current of the second PMOS transistor MP2 and PMOS adjust transistor MP1 is roughly equal.Therefore, when low-power consumption, the drain current of the second PMOS transistor MP2 and the output terminal OUT2 approximately equal of low pressure difference linear voltage regulator.
Described first current lens unit IL1 can comprise: the first nmos pass transistor MN1 and the second nmos pass transistor MN2.The drain electrode of described first nmos pass transistor MN1 connects the grid of the first nmos pass transistor MN1 and the grid of the second nmos pass transistor MN2 and as the input end of described first current lens unit IL1, source electrode connects described second voltage end GND; The drain electrode of described second nmos pass transistor is as first output terminal of described first current lens unit IL1, and source electrode is as second output terminal of described first current lens unit IL1.
Described first electric current providing unit comprises the 5th nmos pass transistor MN5, and the drain electrode of described 5th nmos pass transistor MN5 connects the bias current inputs BIAS of described error amplifier OP, and source electrode connects described second voltage end GND, grid input offset voltage.
Described error amplifier OP can comprise: the 5th PMOS transistor, the 6th PMOS transistor, the 6th nmos pass transistor and the 7th nmos pass transistor.The source electrode of described 5th PMOS transistor connects described first voltage end VDD, and drain electrode connects the drain electrode of the grid of described 5th PMOS transistor, the grid of the 6th PMOS transistor and the 6th nmos pass transistor.The source electrode of described 6th PMOS transistor connects described first voltage end VDD, drain electrode connect described 7th nmos pass transistor drain electrode and as the output terminal OUT1 of described error amplifier OP.The source electrode of described 6th nmos pass transistor connects the source electrode of described 7th nmos pass transistor and as the bias current inputs BIAS of described error amplifier OP, grid is as the second input end IN2 of described error amplifier OP.The grid of described 7th nmos pass transistor is as the first input end IN1 of described error amplifier OP.
In the present embodiment one, the drain current that the drain current of the second PMOS transistor MP2 and PMOS adjust transistor MP1 is roughly equal, achieves the second electric current providing unit 12 gathers the output terminal OUT2 of low pressure difference linear voltage regulator electric current by the voltage on error amplifier OP1 output terminal OUT1.
The electric current that second PMOS transistor MP2 source electrode collects can be mirrored to the bias current inputs BIAS of error amplifier OP by the first current lens unit.
The second electric current providing unit 12 that the embodiment of the present invention one provides gathers the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator by the voltage on error amplifier OP1 output terminal OUT1, thus produces the adjustment electric current be associated with the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.
When load becomes large, the output terminal OUT2 ER effect of low pressure difference linear voltage regulator is large, and P2 limit (the output terminal OUT2 of low pressure difference linear voltage regulator) frequency becomes large.The output terminal OUT2 ER effect of low pressure difference linear voltage regulator causes greatly the adjustment electric current of the second electric current providing unit 12 also to become large, makes the output impedance of error amplifier OP diminish like this, and P1 limit (PMOS adjusts the grid of transistor MP1) frequency becomes large.Because the frequency of P1 limit and P2 limit increases all to some extent, so just can ensure that limit moves to identical direction, when sampling feedback coefficient is more than or equal to 1, the relative position of P1 limit and P2 limit just can not reduce, both frequency-splittings can remain on enough large distance substantially like this, ensure that the stability of low pressure difference linear voltage regulator.
As shown in Figure 4, the low pressure difference linear voltage regulator that embodiment two provides is with the difference of embodiment one: the second electric current providing unit 12 is connected with the output terminal OUT2 of low pressure difference linear voltage regulator with the bias current inputs BIAS of described error amplifier OP1 respectively, be suitable for the electric current directly gathering the output terminal OUT2 of described low pressure difference linear voltage regulator, thus produce the adjustment electric current be associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator.
Fig. 5 is a kind of specific embodiment of the embodiment of the present invention two.As shown in Figure 5, described second electric current providing unit 12 comprises: the second current lens unit IL2 and the 3rd current lens unit IL3.Described PMOS adjusts the first end of drain electrode by the described first resistance R1 of described second current lens unit IL2 connection of transistor MP1; The input end of described second current lens unit IL2 connects the drain electrode that described PMOS adjusts transistor MP1, and the first output terminal connects the first end of described first resistance R1, and the second output terminal connects the input end of described 3rd current lens unit IL3; First output terminal of described 3rd current lens unit IL3 connects the bias current inputs of described error amplifier, and the second output terminal connects described second voltage end GND.
Described second current lens unit IL2 can comprise: the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4.The source electrode of described 3rd PMOS transistor MP3 connects the source electrode of described 4th PMOS transistor MP4 and as the input end of described second current lens unit, grid connects the drain electrode of described 3rd PMOS transistor MP3 and the grid of the 4th PMOS transistor MP4 and as first output terminal of described second current lens unit IL2; The drain electrode of described 4th PMOS transistor MP4 is as second output terminal of described second current lens unit IL2.
Described 3rd current lens unit IL3 can comprise: the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4.The drain electrode of described 3rd nmos pass transistor MN3 connects the grid of the 3rd nmos pass transistor MN3 and the grid of the 4th nmos pass transistor MN4 and as the input end of described 3rd current lens unit IL3, source electrode connects described second voltage end GND; The drain electrode of described 4th nmos pass transistor MN4 is as first output terminal of described 3rd current lens unit IL3, and source electrode is as second output terminal of described 3rd current lens unit IL3.
In the present embodiment two, the drain current that PMOS can be adjusted transistor MP1 by the second current lens unit is mirrored to the input end of the 3rd current lens unit, thus realizes the collection of the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.
The second electric current providing unit 12 that the embodiment of the present invention two provides directly gathers the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator, thus produces the adjustment electric current be associated with the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.When load becomes large, the frequency of P2 limit becomes large, the adjustment electric current that second electric current providing unit 12 produces increases, make that the output impedance of error amplifier OP diminishes, P1 pole frequency becomes large, the frequency-splitting of P1 limit and P2 limit can remain on enough large distance substantially, ensure that the stability of low pressure difference linear voltage regulator.
In other embodiments, described first electric current providing unit can be realized by other bias current generating circuits in prior art.
In other embodiments, described second electric current providing unit can adopt CCCS or Voltage-controlled Current Source to realize.When described second electric current providing unit is CCCS, the control end of described CCCS is connected with the output terminal OUT2 of described low pressure difference linear voltage regulator.When described second electric current providing unit is Voltage-controlled Current Source, the grid that control end and the described PMOS of described Voltage-controlled Current Source adjust transistor is connected.
In other embodiments, described first current lens unit, the second current lens unit and the 3rd current lens unit also can adopt the current mirroring circuit of other types in prior art to realize.
The present invention also provides a kind of limit method of adjustment of low pressure difference linear voltage regulator, comprising:
Step S1, provide reference current and regulate electric current, described adjustment electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
Step S2, superposes described reference current and regulates electric current, to obtain bias current;
Step S3, provides the bias current inputs of the error amplifier in described bias current to described low pressure difference linear voltage regulator.
Optionally, providing in step S1 regulates electric current to comprise: gather the output end current of described low pressure difference linear voltage regulator to produce described adjustment electric current.
Optionally, providing in step S1 regulates electric current also can comprise: the PMOS gathered in described low pressure difference linear voltage regulator adjusts the gate terminal voltage of transistor to produce described adjustment electric current.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (4)
1. a low pressure difference linear voltage regulator, is characterized in that, comprising: error amplifier, the first electric current providing unit, the second electric current providing unit, PMOS adjust transistor, the first resistance and the second resistance;
The source electrode that described PMOS adjusts transistor connects the first voltage end, and grid connects the output terminal of described error amplifier;
Described first electric current providing unit is suitable for producing reference current;
Described second electric current providing unit is suitable for producing and regulates electric current, and described adjustment electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
The first input end input reference voltage of described error amplifier, the second input end connects the second end of described first resistance and the first end of the second resistance, the bias current that bias current inputs inputs described reference current and regulates electric current superposition to produce;
The first end of described first resistance is the output terminal of described low pressure difference linear voltage regulator;
Second end of described second resistance connects the second voltage end;
The magnitude of voltage of described first voltage end is greater than the magnitude of voltage of the second voltage end;
Described second electric current providing unit comprises: the second current lens unit and the 3rd current lens unit;
Described PMOS adjusts the first end of drain electrode by described first resistance of described second current lens unit connection of transistor;
The input end of described second current lens unit connects the drain electrode that described PMOS adjusts transistor, and the first output terminal connects the first end of described first resistance, and the second output terminal connects the input end of described 3rd current lens unit;
First output terminal of described 3rd current lens unit connects the bias current inputs of described error amplifier, and the second output terminal connects described second voltage end.
2. low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described second current lens unit comprises: the 3rd PMOS transistor and the 4th PMOS transistor;
The source electrode of described 3rd PMOS transistor connects the source electrode of described 4th PMOS transistor and as the input end of described second current lens unit, grid connects the drain electrode of described 3rd PMOS transistor and the grid of the 4th PMOS transistor and as the first output terminal of described second current lens unit;
The drain electrode of described 4th PMOS transistor is as the second output terminal of described second current lens unit.
3. low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described 3rd current lens unit comprises: the 3rd nmos pass transistor and the 4th nmos pass transistor;
The drain electrode of described 3rd nmos pass transistor connects the grid of the 3rd nmos pass transistor and the grid of the 4th nmos pass transistor and as the input end of described 3rd current lens unit, source electrode connects described second voltage end;
The drain electrode of described 4th nmos pass transistor is as the first output terminal of described 3rd current lens unit, and source electrode is as the second output terminal of described 3rd current lens unit.
4. low pressure difference linear voltage regulator as claimed in claim 1, is characterized in that, described adjustment electric current increases with the electric current increase of the output terminal of described low pressure difference linear voltage regulator.
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